JPH05218059A - Semiconductor device and its manufacture - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device having a high breakdown voltage between a base electrode and a collector region and a method capable of stably manufacturing the semiconductor device. The impurity is diffused from a sidewall spacer 26 containing a P-type impurity and a P-type diffusion layer 15 having a high impurity concentration, a P-type polycrystalline Si film 14 having a high impurity concentration serving as a base electrode, and an insulating film. The low impurity concentration P-type diffusion layers 17 and 27 thus formed serve as base regions, and the N-type diffusion layer 16 serves as an intrinsic collector region. For this reason,
High impurity concentration P-type polycrystalline Si film 1 which is a base electrode
4 and the N type diffusion layer 16 which is an intrinsic collector region, a P type diffusion layer 27 having a low impurity concentration is interposed.
Therefore, the polycrystalline Si film 14 and the diffusion layer 16 are not in contact with each other, and the reverse breakdown voltage between them is high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device called a lateral bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A lateral bipolar transistor does not require a buried layer or an epitaxial layer to be formed unlike a vertical bipolar transistor, and can be manufactured in a process substantially similar to that of a CMOS transistor.
It is suitable for manufacturing a CMOS integrated circuit device.

FIGS. 5 and 6 show such a lateral NPN.
Bipolar transistors (eg Extended Abstracts
of the 21st Conference on Solid State Devices and
Materials, Tokyo, 1989, pp.109-112 'CMOS Compatible
Lateral Bipolar Transistor for BiCMOS Technology '
1) shows a conventional example of the manufacturing method of FIG.

In this conventional example, as shown in FIG. 5, after a field oxide film 12 for element isolation and an active element region 13 are formed on a P type Si substrate 11 by the Locos method, a P type impurity is added. The containing polycrystalline Si film 14 is patterned.

Next, a high impurity concentration P-type diffusion layer 15 and a low impurity concentration N-type diffusion layer 16 are selectively formed in the active element regions 13 on both sides of the polycrystalline Si film 14.
Impurities are solid-layer diffused from the polycrystalline Si film 14 to the active element region 13 to form a P-type diffusion layer 17 having a low impurity concentration under the polycrystalline Si film 14.

Next, as shown in FIG. 6, the polycrystalline Si film 1
Side wall spacers 18 are formed on both sides of the polycrystalline silicon film 1
4 and the side wall spacer 18 are used as masks to form high impurity concentration N type diffusion layers 21 and 22 in the active element region 13.

In the lateral NPN bipolar transistor manufactured as described above, the polycrystalline Si film 14 is the base electrode, the diffusion layer 21 is the emitter region, and the diffusion layers 15 and 17 are the drift type base. It has become an area. Further, the diffusion layer 16 serves as an intrinsic collector region, and the diffusion layer 22 serves as a collector electrode extraction region.

[0008]

However, in the above-mentioned conventional lateral NPN bipolar transistor, as is apparent from FIG. 6, the intrinsic collector is formed on the high impurity concentration P-type polycrystalline Si film 14 which is the base electrode. The N-type diffusion layer 16 which is a region is in contact. For this reason, the reverse bias voltage between them is as low as about 6 to 7 V and cannot be used as a high breakdown voltage transistor.

Therefore, it is an object of the invention of the present application to provide a semiconductor device having a high breakdown voltage between a base electrode and a collector region and a method capable of stably manufacturing the semiconductor device.

[0010]

According to another aspect of the semiconductor device of the present invention, a first conductivity type electrode having a relatively high impurity concentration is formed on a first conductivity type semiconductor substrate, and a sidewall made of an insulating film is formed. A spacer is formed on at least one of the electrodes, and a diffusion layer of a first conductivity type having a relatively low impurity concentration is formed in a region of the semiconductor substrate in contact with the electrode and the sidewall spacer. A diffusion layer of the second conductivity type is formed in a region of the semiconductor substrate opposite to the electrode of the sidewall spacer.

According to a second aspect of the present invention, there is provided a first method of manufacturing a semiconductor device.
Forming a first conductivity type electrode on a conductivity type semiconductor substrate; forming a sidewall spacer made of an insulating film and containing impurities of the first conductivity type on at least one of the electrodes;
A step of diffusing a first conductivity type impurity from the electrodes and the sidewall spacers to the semiconductor substrate to form a first conductivity type diffusion layer; and using the electrodes and the sidewall spacers as a mask to form a semiconductor layer on the semiconductor substrate. And a step of forming a diffusion layer of the second conductivity type.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:
Forming a first conductivity type electrode on a conductivity type semiconductor substrate; forming a first sidewall spacer made of an insulating film and containing impurities of the first conductivity type on at least one of the electrodes; Forming a second sidewall spacer containing an impurity of the second conductivity type on the opposite side of the first sidewall spacer from the electrode; and forming a second sidewall spacer from the electrode and the first sidewall spacer to the semiconductor substrate. An impurity of one conductivity type is diffused to form a diffusion layer of the first conductivity type, and an impurity of the second conductivity type is diffused from the second sidewall spacer to the semiconductor substrate to form a diffusion layer of the second conductivity type. Forming process.

[0013]

According to another aspect of the semiconductor device of the present invention, when the first conductivity type electrode is the base electrode and the first conductivity type diffusion layer and the second conductivity type diffusion layer are the base region and the collector region, respectively, The region is in contact with the base region having a low impurity concentration, but is not in contact with the base electrode having a high impurity concentration.

In the method of manufacturing a semiconductor device according to the second aspect, the impurity concentration of the first conductivity type diffusion layer formed on the semiconductor substrate by diffusion of impurities from the electrodes and the sidewall spacers is lower than the impurity concentration of the electrodes. Moreover, the second conductive type diffusion layer formed on the semiconductor substrate by using the electrodes and the sidewall spacers as a mask is formed in a region of the sidewall spacers on the side opposite to the electrodes.

In the method of manufacturing a semiconductor device according to a third aspect of the present invention, the impurity concentration of the first conductivity type diffusion layer formed on the semiconductor substrate by diffusion of impurities from the electrodes and the first sidewall spacers is
It is lower than the impurity concentration of the electrode. In addition, the second side wall spacer is formed on the semiconductor substrate by diffusion of impurities from the second side wall spacer.
The conductive type diffusion layer is formed in a region of the first sidewall spacer opposite to the electrode.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a lateral NPN bipolar transistor will be described below with reference to FIGS. The components corresponding to those of the conventional example shown in FIGS. 5 and 6 are designated by the same reference numerals.

FIG. 1 shows this embodiment, and FIGS.
Indicates the manufacturing process. In order to manufacture this example, as shown in FIG. 2, a P type with a resistivity of 3 to 12 Ω · c was used.
The Si substrate 11 of about m has a film thickness of 30 by the Locos method.
A field oxide film 12 for element isolation and an active element region 13 of about 0 to 1000 nm are formed.

Thereafter, P-type impurities such as boron ions are removed by 1
Polycrystalline S containing a dose of about 0 ²⁰ to 10 ²¹ atoms cm ^-3
The i film 14 is deposited to a film thickness of about 150 to 600 nm by the CVD method, and the polycrystalline Si film 14 is processed into a pattern of the base electrode by the photolithography technique and the etching technique.

Then, the active element region 13 and the polycrystalline Si
After the SiO ₂ film 23 is formed on the entire surface of the film 14, a pattern covering only the active element region 13 on one side of the polycrystalline Si film 14 is formed into a Si film by photolithography and etching.
The O ₂ film 23 is processed. However, the SiO ₂ film 23 may be formed before the polycrystalline Si film 14 is formed.

Next, as shown in FIG. 3, a polycrystalline Si film 14 is formed.
The resist film 24 is patterned by photolithography so as to cover the active element region 13 on the side opposite to the SiO ₂ film 23. Then, the resist film 24 and the polycrystalline Si film 1
An impurity 25 which is a boron ion is ion-implanted into the active element region 13 with 4 and 4 as a mask with an energy of about 10 to 70 keV and at a dose of about 1 × 10 ¹⁴ to 1 × 10 ¹⁶ ions cm ⁻² .

Thereafter, heat treatment is performed to diffuse and activate the ion-implanted impurities 25 to form a P-type diffusion layer 15 having a high impurity concentration, and at the same time, impurities from the polycrystalline Si film 14 to the active element region 13 are doped. The P-type diffusion layer 17 having a low impurity concentration is formed by solid-phase diffusion.

Next, the resist film 24 is removed, and 10-2
A film thickness of 200 to 600 n containing B ₂ O _{3 of} about 0% by weight
A SiO ₂ film having a thickness of about m is deposited on the entire surface by the CVD technique. Then, the SiO ₂ film is subjected to anisotropic etching by RIE to form side wall spacers 26 made of the SiO ₂ film on both sides of the polycrystalline Si film 14, as shown in FIG.

In the active element region 13 where the SiO ₂ film 23 is not formed, the side wall spacer 26 is formed on the Si substrate 1.
1, but in the active element region 13 where the SiO ₂ film 23 is formed, the side wall spacers 26 have the SiO ₂ film 23.
It is formed on and does not contact the Si substrate 11.

For this reason, a heat treatment is carried out thereafter, and Si
In the active element region 13 where the O ₂ film 23 is not formed,
Impurities are solid-diffused from the side wall spacers 26 to the active element region 13 to form a P-type diffusion layer 27 having a low impurity concentration, but the active element region 13 in which the SiO ₂ film 23 is formed is formed.
Then, the impurity is not diffused from the side wall spacer 26 to the active element region 13 in the solid layer, and the diffusion layer is not formed.

After that, the resist film 28 is patterned by photolithography so as to cover the diffusion layer 15. Then, using the resist film 28, the polycrystalline Si film 14, and the sidewall spacers 26 as masks, the active element region 13 is doped with the impurities 31 which are phosphorus ions at an energy of about 10 to 50 keV and a dose of 1 × 10 ¹² to 1 × 10 ¹⁴ ions cm. Ion implantation is performed at a dose of about ^-2 . Then, heat treatment is performed to diffuse and activate the ion-implanted impurities 31 to form the N-type diffusion layer 16 having a low impurity concentration.

As a result, the diffusion layer 27 is sandwiched between the diffusion layers 16 and 17, and the width of the diffusion layer 27 is substantially equal to the width of the sidewall spacer 26. The width of the side wall spacer 26 can be set to a desired value of about 0.1 to 0.3 μm by controlling the film thickness of the SiO ₂ film for forming the side wall spacer 26. Therefore, the width of the diffusion layer 27 is also
It can be controlled in the range of about 0.1 to 0.3 μm.

Next, the resist film 28 is removed and the film thickness is reduced to 2
A SiO ₂ film having a thickness of about 00 to 600 nm is deposited on the entire surface by the CVD technique. Then, for this SiO ₂ film, R
Anisotropic etching by IE is performed to form the side wall spacers 32 made of a SiO ₂ film outside the side wall spacers 26, as shown in FIG. It is desirable that the sidewall spacer 32 does not contain impurities.

Thereafter, using the polycrystalline Si film 14 and the side wall spacers 26 and 32 as a mask, the active element region 13 is doped with an impurity 33, which is an arsenic ion, at an energy of about 10 to 100 keV, 1 × 10 ¹⁵ to 1 × 10 5. Ion implantation is performed at a dose of about ¹⁶ ions cm ^-2 . And heat treatment,
The ion-implanted impurities 33 are diffused and activated to form N-type diffusion layers 21 and 22 having a high impurity concentration.

Impurity 2 forming the diffusion layer 15
Since the diffusion coefficient of arsenic ions, which are impurities 33 forming the diffusion layer 21, is smaller than the diffusion coefficient of boron ions of 5, the diffusion layer 21 is formed in the diffusion layer 15.

In the lateral NPN bipolar transistor of this embodiment manufactured as described above, the polycrystalline Si film 1 is used.
4 is a base electrode, the diffusion layer 21 is an emitter region, and the diffusion layers 15, 17 and 27 are drift type base regions. Further, the diffusion layer 16 serves as an intrinsic collector region, and the diffusion layer 22 serves as a collector electrode extraction region.

In the lateral NPN bipolar transistor of this embodiment, as is clear from FIG. 1, a high impurity concentration P-type polycrystalline Si film 14 as a base electrode and an N-type diffusion layer 16 as an intrinsic collector region are provided. Since the P-type diffusion layer 27 having a low impurity concentration is interposed between the polycrystalline Si film 1 and
4 and the diffusion layer 16 are not in contact with each other. For this reason,
The withstand voltage between them, which is reverse-biased, is as high as about 20 to 30 V and can be used as a high withstand voltage transistor.

In this embodiment, the N-type diffusion layer 16 having a low impurity concentration is formed by ion implantation of the impurities 31 using the resist film 28, the polycrystalline Si film 14 and the sidewall spacers 26 as a mask and the subsequent heat treatment. However, the side wall spacer 32 may be formed of a SiO ₂ film containing 10 to 20% by weight of P ₂ O ₅ , and the diffusion layer 16 may be formed by solid phase diffusion of phosphorus from the side wall spacer 32. This way,
The step of forming the resist film 28 and the step of ion-implanting the impurities 31 are unnecessary.

[0033]

In the semiconductor device according to the first aspect of the invention, since the collector region is not in contact with the base electrode having a high impurity concentration, the breakdown voltage between the reverse biased base electrode and collector region is high.

In the method of manufacturing a semiconductor device according to a second aspect of the present invention, the impurity concentration of the first conductivity type diffusion layer is lower than that of the electrode, and the second conductivity type diffusion layer is on the side opposite to the electrode of the sidewall spacer. The semiconductor device according to the first aspect can be manufactured stably because it is formed in the region.

In the method of manufacturing a semiconductor device according to the third aspect of the present invention, the impurity concentration of the diffusion layer of the first conductivity type is lower than the impurity concentration of the electrode, and the diffusion layer of the second conductivity type is the electrode of the first sidewall spacer. Is formed in the region on the opposite side.
The semiconductor device can be stably manufactured.

[Brief description of drawings]

FIG. 1 is a side sectional view of an embodiment of the present invention.

FIG. 2 is a side sectional view showing a first step for manufacturing the example.

FIG. 3 is a side sectional view showing a step that follows FIG.

FIG. 4 is a side sectional view showing a step that follows FIG.

FIG. 5 is a side sectional view showing a first step for manufacturing a conventional example.

FIG. 6 is a side sectional view of a conventional example of the present invention.

[Explanation of symbols]

 11 Si Substrate 14 Polycrystalline Si Film 16 Diffusion Layer 17 Diffusion Layer 26 Sidewall Spacer 27 Diffusion Layer 32 Sidewall Spacer

Claims (3)

[Claims] 1. A first-conductivity-type electrode having a relatively high impurity concentration is formed on a first-conductivity-type semiconductor substrate, and a sidewall spacer made of an insulating film is formed on at least one of the electrodes. A diffusion layer of a first conductivity type having a relatively low impurity concentration is formed in a region of the semiconductor substrate in contact with the electrode and the sidewall spacer, and the diffusion layer of the sidewall spacer of the semiconductor substrate is formed. A semiconductor device in which a diffusion layer of the second conductivity type is formed in a region opposite to the electrode. 2. A step of forming an electrode of the first conductivity type on a semiconductor substrate of the first conductivity type, and a step of forming a sidewall spacer made of an insulating film and containing impurities of the first conductivity type on at least one of the electrodes. A step of diffusing first conductivity type impurities from the electrodes and the sidewall spacers into the semiconductor substrate to form a first conductivity type diffusion layer; and using the electrodes and the sidewall spacers as a mask, the semiconductor And a step of forming a diffusion layer of the second conductivity type on the substrate. 3. A step of forming an electrode of the first conductivity type on a semiconductor substrate of the first conductivity type, and a first sidewall spacer made of an insulating film and containing impurities of the first conductivity type on at least one of the electrodes. A step of forming, a step of forming a second sidewall spacer made of an insulating film and containing impurities of the second conductivity type, on a side of the first sidewall spacer opposite to the electrode, the electrode and the first sidewall A first conductivity type impurity is diffused from the spacer to the semiconductor substrate to form a first conductivity type diffusion layer, and a second conductivity type impurity is diffused from the second sidewall spacer to the semiconductor substrate. And a step of forming a diffusion layer of two conductivity type.