JPH05218095A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To improve the productivity of semiconductor devices having T-shaped gate electrodes. A lower layer mask 48 is etched through a resist 52 to form a gate electrode forming window 48a in the lower layer mask 48. Next, another resist 54 is formed on the lower layer mask 48, and the resist 54 is exposed using the above-mentioned exposure mask. After that, the resist 54 is developed and another window for forming a gate electrode is formed in the resist 54. Even if the common exposure mask is used, the exposure amount of the resist 54 is made smaller than that of the resist 52, so that another window for forming the gate electrode is formed as the window 48.
It can be formed wider than a. Therefore, the narrow window 48a for forming the gate electrode and another wide window can be formed by controlling the exposure amount by the reduced projection exposure method without using the EB direct writing method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an electrode having a T-shaped cross section.

[0002]

2. Description of the Related Art MESFETs used in microwave circuits,
In FETs such as HEMTs, it is desired to shorten the gate length in order to reduce noise. However, the gate resistance increases as the gate length decreases. An increase in gate resistance hinders noise reduction. Therefore, a T-shaped gate electrode that can reduce the gate resistance as well as the gate length has been proposed. As a method of forming the T-shaped gate electrode, for example, Document 1: Technical Report of the Institute of Electronics, Information and Communication Engineers ED90-92, pp3
7-43.

FIG. 10 (A)-(B) and FIG. 11 (A)-
FIG. 3B is a cross-sectional view for explaining a conventional process for forming a T-shaped electrode disclosed in the above document.

In the conventional forming method, first, as shown in FIG.
As shown in (A), a low-sensitivity and high-resolution lower-layer resist 12 and a high-sensitivity upper-layer resist 14 are sequentially laminated on the GaAs substrate 10.

Next, as shown in FIG. 10B, the upper layer resist 14 and the lower layer resist 12 are exposed using an electron beam direct writing apparatus, and then the upper layer resist 14 and the lower layer resist 12 are developed. , These resists 14 and 1
2, a window 16 exposing the GaAs substrate 10 is formed. Even if the upper layer resist 14 and the lower layer resist 12 are exposed with the same amount of exposure, the upper layer resist 14 has a larger portion that is soluble in the developing solution than the lower layer resist 12, so that the window 16 having a T-shaped cross section can be formed.

Next, as shown in FIG. 11A, the substrate 1 in which the material layer 18 for forming the gate electrode is exposed through the window 16
It is laminated on the 0 surface and the lower layer resist 12.

Next, as shown in FIG. 11B, the lower layer resist 12 and the upper layer resist 14 are removed to obtain a gate electrode 20 having a T-shaped cross section. The gate length can be effectively shortened by narrowing the width of the base of the gate electrode 20, and the resistance of the gate electrode 20 can be reduced by widening the width of the head of the gate electrode 20.

[0008]

However, when the resist is exposed by using the electron beam direct writing apparatus, the resist is exposed so that the gate electrode shape is drawn by the electron beam, so that the writing takes time, and therefore the productivity is improved. Will be lower.

An object of the present invention is to solve the above-mentioned conventional problems, and to a method of manufacturing a semiconductor device capable of forming a T-shaped electrode, particularly a gate electrode, by a projection exposure method.

[0010]

To achieve this object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a lower layer mask for forming an electrode on a base material, and a negative type mask on the lower layer mask. A step of applying a first resist, a step of exposing the first resist using an exposure mask having a phase shifter, and forming a fine line-shaped first unexposed portion corresponding to the edge of the phase shifter on the first resist , A step of developing the first resist to remove the first unexposed portion and forming a first resist pattern, and etching the lower layer mask through the first resist pattern to expose the base material to the lower layer mask. The step of forming the window, the step of removing the first resist pattern, the step of applying the negative second resist on the lower layer mask having the window formed thereon, and the exposure amount less than the exposure amount of the first resist using the exposure mask. Exposing the second resist in an amount, and forming a second unexposed portion of a fine line which is arranged on the window and wider than the window, and developing the second resist to remove the second unexposed portion. Then, a step of forming a second resist pattern as an upper layer mask for electrode formation, and a step of laminating an electrode material on the base material through the lower layer and the upper layer mask and then removing the lower layer and the upper layer mask It is characterized by

[0011]

According to such a manufacturing method, the phase shifter of the exposure mask shifts the phase of light by approximately 180 °, so that the phase of light transmitted through the exposure mask and the phase shifter of the exposure mask are changed. The phase of light transmitted without passing through is shifted by about 180 °. When a negative resist is exposed by a projection exposure method using this exposure mask, the intensity of the light irradiated to the portion corresponding to the phase shifter edge of the negative resist (hereinafter referred to as the edge corresponding portion) depends on the light interference. become weak.

Therefore, the edge-corresponding portion can be exposed to the extent that the property of dissolving it in the developing solution is not lost, so that an unexposed portion that is not substantially exposed can be formed in the edge-corresponding portion. Moreover, a very narrow thin line-shaped unexposed portion can be formed at this edge-corresponding portion. Although the numerical value is not limited to this, it is possible to form an unexposed portion having a width of 0.25 μm or less, for example. The width (or area) of the unexposed portion formed in the edge corresponding portion can be controlled by the exposure amount. The width of the unexposed portion decreases as the exposure amount increases, and the width of the unexposed portion increases as the exposure amount decreases. Therefore, even if a common exposure mask is used for exposing the first and second resists, an unexposed portion having a wider width than the unexposed portion of the first resist is formed in the second resist by controlling the exposure amount. it can.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, an example in which a T-shaped gate electrode and a gate electrode pad are formed in parallel will be described as an example.

In this embodiment, in order to form the planar shape of the T-shaped gate electrode into a desired electrode pattern shape, in addition to the exposure mask having a phase shifter (hereinafter referred to as the first exposure mask), the phase Another exposure mask (hereinafter referred to as the second exposure mask) that includes a light-shielding portion at a position corresponding to the electrode pattern portion at the edge of the shifter and a light-transmitting portion at a position corresponding to the non-electrode pattern portion at the edge of the phase shifter. ) Is used.

FIG. 1A is a plan view schematically showing the structure of the first exposure mask used in this embodiment, and FIG. 1B.
2 is a cross-sectional view taken along the line IB-IB in FIG. As shown in FIG. 1, the first exposure mask 22 of this embodiment has a first light shielding portion 24 used to form a gate electrode pad and a phase shifter 26 used to form a T-shaped gate electrode. Are provided in the light transmitting portion 28 of the first light transmitting substrate, and the edge 26a of the phase shifter 28 extends from the first light shielding portion 24 to a region of the light transmitting portion 28 where the first light shielding portion 24 is not provided. Let me place it.

The planar shape of the first light shielding portion 24 is rectangular. The length of the first side of the light shielding portion 24 extending in the Y direction is W1, and the length of the second side orthogonal to the first side and extending in the X direction is, for example, W2 + 2WX. W1 is a value obtained by multiplying the design size of the side extending in the X direction of the gate electrode pad by the reciprocal of the reduction ratio t of the projection exposure apparatus, and W2
Indicates a value obtained by multiplying the designed actual size of the side extending in the Y direction of the gate electrode pad by the reciprocal of the reduction ratio t of the projection exposure apparatus.

Further, WX is an estimated amount of positional deviation in the X direction between the first exposure mask 22 and the second exposure mask 30 which will be described later. In the X direction of FIG. Is set at a position separated by WX from the position corresponding to the left end of the gate electrode pad on the first exposure mask 22, and the right end position of the first light shielding portion 24 is exposed in the X direction of FIG. The position is separated from the position corresponding to the right end of the gate electrode pad on the first mask 22 by WX.

FIG. 2A is a plan view schematically showing the structure of the second exposure mask used in this embodiment, and FIG. 2B.
FIG. 3 is a sectional view taken along line IIB-IIB in FIG. As shown in FIG. 2, the second mask 30 for exposure of this embodiment has a second light-shielding portion 32 used for forming a gate electrode pad and a third light-shielding portion used for forming a T-shaped gate electrode. And the portion 34 are provided on the light transmitting portion 36 of the second light transmitting substrate. The second light-shielding portion 32 is arranged at a position corresponding to the first light-shielding portion 24 of the first exposure mask 22, and the third light-shielding portion 34 is aligned with the gate electrode pattern portion of the edge 26a of the first exposure mask 22. They are arranged corresponding to each other, and the light shielding parts 32 and 34 are combined and provided. The second light-shielding portion 32 and the third light-shielding portion 34 are provided at positions corresponding to the non-gate electrode pattern portion of the edge 26a of the first exposure mask 22.
A region of only the light transmitting portion 36 where no is provided is provided.

The planar shape of the second light shielding portion 32 is rectangular. The length of the second side of the light shielding portion 32 extending in the X direction is W2, and the length of the first side orthogonal to the second side and extending in the Y direction is W1 + 2WY. WY is a predicted amount of positional deviation in the Y direction between the first exposure mask 22 and the second exposure mask 30, and the upper end position of the second light shielding portion 32 is exposed in the Y direction of FIG. The position on the second mask 30 for use, which is separated from the position corresponding to the upper end of the gate electrode pad by WY, and further, Y in FIG.
In the direction, the lower end position of the second light shielding portion 32 is a position separated by WY from the position corresponding to the lower end of the gate electrode pad on the second exposure mask 30.

Next, an unexposed portion (latent image) formed on the resist by two exposures using the above-described first exposure mask 22 and second exposure mask 30 will be described.

The resist is exposed using the first exposure mask 22 (first exposure), and then the second exposure mask 3 is used.
Consider a case where 0 is used for exposure (second exposure).
FIGS. 3A and 3B are plan views showing the state of the unexposed portion of the resist formed by the first and second exposures.

As shown in FIG. 3A, in the first exposure, an unexposed portion 40 for pad formation is formed in the portion of the resist 38 corresponding to the first light shielding portion 24, and an edge of the phase shifter 26 of the resist 38. An unexposed portion 42 for forming a gate electrode is formed on the corresponding portion.

After the first exposure, the second exposure mask 30 is aligned and the second exposure is performed. At this time, as shown in FIG. 3A, the left side of the second light shielding portion 32 of the second exposure mask 30 is the first exposure mask 2
It is assumed that the mask alignment is performed in a state of being displaced in the X direction so as to overlap with the left side of the second light-shielding portion 24. In this case, a light shielding region formed on the resist 38 by the second light shielding portion 32 and the third light shielding portion 34 of the second exposure mask 30 is indicated by reference numeral 44 in FIG. 3A. ..
Even in this case, the widths of the second light-shielding portion 32 and the third light-shielding portion 34 included in the second exposure mask 30 in the X-direction take into account the amount of misregistration expected during mask alignment. As shown, in the second exposure, the non-gate electrode pattern portion can be exposed while the gate electrode pattern portion of the unexposed portion 42 for forming the gate electrode is not exposed. Moreover, the length of the side of the unexposed portion for forming the pad in the X and Y directions is set to a predetermined design dimension W1 x
t and W2 xt. Even if two exposures are performed using the second exposure mask 30 and the first exposure mask 22 in this order, the unexposed portions 40 and 42 having the same pattern shape as shown in FIG. 3B. Can be formed. In this embodiment, the gate electrode having a planar shape equivalent to, for example, the unexposed portions 40 and 42 shown in FIG. 3B is obtained by performing two exposures using the first exposure mask 22 and the second exposure mask 30. A pad and a gate electrode are formed.

Here, only an example in which the positions of the first exposure mask 22 and the second exposure mask 30 are displaced in the X direction by the mask alignment of the exposure first mask 22 and the exposure second mask 30 has been described and shown. Even if the position of is shifted in the X and / or Y direction, it is possible to form an unexposed portion for pad formation having the same area and shape as the unexposed portion 40 shown in FIG.

Next, a process of forming a T-shaped gate electrode and a gate electrode pad using the above-described first exposure mask 22 and second exposure mask 30 will be described. Figure 4-
FIG. 6 is an explanatory view of this embodiment, and is a process drawing showing the formation of the T-shaped gate electrode. These figures are shown in FIG.
The cross section corresponding to the cross section taken along the III-III line of (A) is shown.

First, as shown in FIG. 4A, a base material 46 on which a T-shaped electrode is to be formed is prepared. In this embodiment, since the gate electrode is formed as the T-shaped electrode, the substrate 4
6 includes an active layer (not shown) of a field effect transistor. Further, although not shown, the base material 46 includes a field oxide film used for element isolation of the field effect transistor, and a source electrode (ohmic electrode) and a drain electrode (ohmic electrode) provided on the active layer.

Next, as shown in FIG. 4B, the base material 46
A lower layer mask 48 for forming electrodes is formed thereon. In this embodiment, the lower mask 48 is a SiN film having a film thickness of about 1000 Å (angstrom). For example, PCVD (pla
sma chemical vapor deposit
ion) method to form a SiN film.

The lower layer mask 48 may be other than the SiN film as long as the lower layer mask 48 can be removed by etching so as not to substantially damage the base material and / or the electrodes. For example, as the lower layer mask 48, a SiO ₂ film, Si
It may be an ON film and other inorganic insulating films, a resist that is immiscible with the negative resist and thus does not deteriorate the negative resist, polyimide and other organic insulating films, a polysilicon film and other conductive films.

Next, as shown in FIG. 4C, a negative first resist 50 is applied on the lower layer mask 48. In this embodiment, FSMR is used as the negative first resist 50.
(Manufactured by Fuji Chemical Industry Co., Ltd.) using the first resist 50
Is applied to a film thickness of about 0.7 μm.

Next, as shown also in FIG. 4D, the first resist 50 is exposed by using the first exposure mask 22 having the phase shifter 26, and a fine line shape corresponding to the edge 26a of the phase shifter 26 is exposed. The first unexposed portion 50b is applied to the first resist 5
Form 0. In this embodiment, an i-ray projection exposure apparatus RA101VLII (manufactured by Hitachi, Ltd.) is used as a stepper.
And the exposure amount of the first resist 50 is 250 mJ · cm.
^-2 .

The first resist 50 has, for example, FIG.
Similarly to the unexposed portions 40 and 42 shown in FIG. 3, an unexposed portion (not shown) for forming a pad and an unexposed portion 50b for forming a gate electrode are formed. Further, for example, by controlling the film thickness of the phase shifter 26, the exposure first mask 2
The phase of the exposure light passing through 2 through the phase shifter 26 and the phase of the exposure light passing through the first exposure mask 22 without passing through the phase shifter 26 are shifted by 180 °. As a result, the exposure amount of the portion corresponding to the edge of the phase shifter 26 of the first resist 50 is reduced to such an extent that the dissolution characteristic of the edge corresponding portion with respect to the developing solution is not changed. The portion 50b can be formed at this edge corresponding portion.

Next, in this embodiment, the first resist 50 is exposed by using the second exposure mask 30, and an unexposed portion (not shown) for forming a pad having a predetermined pattern is formed on the first resist 50. Unexposed part 5 for gate electrode formation
0b is formed. In this embodiment, for example, similarly to the unexposed portions 40 and 42 shown in FIG. 3B, the first resist 50 has an unexposed portion for forming a pad having a predetermined shape and a gate electrode for forming a predetermined shape. Unexposed part 50
and b.

Next, as shown in FIG. 5A, the first resist 50 is developed to remove the unexposed portion 50b, and a first resist pattern 52 is formed. In this embodiment, the first resist 50 is developed to remove the unexposed portion for pad formation and the unexposed portion 50b for gate electrode formation, and the first resist 50 has a pad formation window (not shown) and A window 52a for forming a gate electrode is formed, and a first resist pattern 52 having these windows is obtained. First resist pattern 5
The lower layer mask 48 is partially exposed through the windows for pad formation and gate electrode formation.

When the exposure amount when exposing the first resist 50 using the first exposure mask 22 is about 250 mJ · cm ⁻² , the opening length H1 of the window 52a in the gate electrode length direction is 0.15 μm. It can be a degree. Here, the gate electrode length direction is a direction orthogonal to the edge of the phase shifter 26.

Next, as shown in FIG. 5B, the lower layer mask 48 is etched through the first resist pattern 52 to expose the base material 46 to the lower layer mask 48 in the fine line window 4.
8a is formed. In this embodiment, the lower layer mask 48 is etched by anisotropic etching such as reactive ion etching to form a window (not shown) for forming a pad and a window 48a for forming a gate electrode in the lower layer mask 48.

Next, as shown in FIG. 5C, the first resist pattern 52 is removed, and a negative second resist 54 is applied on the lower layer mask 48 having the window 48a. In this embodiment, FSM is used as the negative second resist 54.
Second resist 5 using R (manufactured by Fuji Chemical Industry Co., Ltd.)
4 is applied to a film thickness of about 0.7 μm.

Next, as shown in FIG. 5D, the second resist 54 is exposed by using the exposure first mask 22 with an exposure amount smaller than that of the first resist 50, and the lower mask window 48a is exposed. A second unexposed portion 54b, which is arranged above and has a width wider than the window 48a, is formed on the second resist 54.
In this embodiment, the stepper used for exposing the first resist 50 is used, and the second resist 5 is exposed at an exposure amount smaller than that of the first resist 50, for example, about 100 mJ · cm ^−2.
4 is exposed to form an unexposed portion (not shown) for forming a pad and an unexposed portion 54b for forming a gate electrode on the second resist 54. Unexposed portions of the second resist 54 for pad formation and unexposed portions 5 for gate electrode formation
4b is formed so as to overlap the window for pad formation of the lower layer mask 48 and the window 48a for gate electrode formation when seen in a plan view. When the exposure amount of the second resist 54 is smaller than that of the first resist 50, the second resist 54
And the planar shape of the unexposed portion for pad formation corresponding to the first light shielding portion 24 of the first resist 50 is almost the same,
Phase shifter 2 of second resist 54 and first resist 50
The planar shape of the unexposed portion for forming the gate electrode corresponding to 6 is wider in the second resist 54.

Therefore, in this case, the unexposed portion 54b for forming the gate electrode is removed by the development, and the second resist 54 is formed.
The opening length H2 of the window formed in the first electrode 50 in the gate electrode length direction is larger than the opening length H1 of the gate electrode forming window 52a formed in the first resist 50. When the exposure amount of the second resist 54 is about 100 mJ · cm ⁻² , the opening length H2 of the second resist 54 can be about 0.35 μm. This point will be described with reference to FIG. 7.

FIG. 7 shows the relationship between the exposure amount (dose amount) of the resist and the width of the window formed in the portion corresponding to the phase shifter edge of the resist when the resist is exposed using the first exposure mask having the phase shifter. FIG. The vertical axis of FIG. 7 represents the opening length H2 (μm) of the window corresponding to the phase shifter edge in the direction orthogonal to the phase shifter edge (gate electrode length direction in this embodiment), and the horizontal axis represents the resist exposure amount ( mJ · cm ⁻² ).
For the details of the relationship between the width of these unexposed portions and the amount of exposure, refer to: 1990 IEDM Technical.
See Digest tp 33.3.1-33.3.4.

As can be understood from FIG. 7, when the resist is exposed using the first exposure mask 22, the opening length H2 of the window of the resist formed in the portion corresponding to the phase shifter edge by development is the exposure amount of this resist. Increases with decreasing.

Therefore, even if the first resist 50 and the second resist 54 are exposed by using the common first exposure mask 22, the exposure amount of the second resist 54 should be smaller than that of the first resist 50. Thus, the opening length H2 of the second resist 54 can be made wider than the opening length H1 of the first resist 50. The opening length H3 in the gate electrode length direction of the gate electrode forming window of the lower mask 48 is the opening length H.
Since it is equal to 1, the opening length H2 of the second resist 54 is wider than the opening length H3 of the lower layer mask 48.

Next, in this embodiment, the second resist 54 is exposed by using the second exposure mask 30, and the second resist 54 has an unexposed portion (not shown) for forming pads having a predetermined pattern shape. Unexposed part 5 for gate electrode formation
0b is formed. In this embodiment, for example, similarly to the unexposed portions 40 and 42 shown in FIG. 3B, an unexposed portion for forming pads having a predetermined shape on the second resist 54 and a portion for forming a gate electrode having a predetermined shape are formed. Unexposed portion 54b
To form.

Next, as shown in FIG. 6A, the second resist 54 is developed to remove the second unexposed portion 54b, and the second resist pattern 5 as an upper mask for electrode formation is formed.
6 is formed. In this embodiment, the second resist 54 is developed to remove the unexposed portion (not shown) for pad formation and the unexposed portion 54b for gate electrode formation, and the second resist 54 is provided with a window for pad formation ( (Not shown) and a window 56a for forming a gate electrode are formed, and a second resist pattern 56 having these windows is obtained. Window for forming pad and gate electrode of second resist pattern 56 and lower mask 4
The base material 46 is partially exposed through the pad forming window and the gate electrode forming window 8. Hereinafter, the second resist pattern 56 is referred to as the upper layer mask 56.

Next, in this embodiment, a recess 57 is formed in the portion of the base material 46 exposed through the upper mask 56 and the lower mask 48. For example, the recess 57 having a depth of about 1000 Å is formed by wet etching.

Next, as shown in FIGS. 6B to 6D,
After the electrode material 58 is laminated on the base material 48 through the lower layer mask 48 and the upper layer mask 56, the masks 48 and 5 are formed.
Remove 6. In this embodiment, the electrode material 58 is the substrate 4
It is a film having a two-layer structure composed of a Ti film and an Al film sequentially provided from the 6 side, and an electrode material 58 having a two-layer structure is used as an electrode material for forming a gate electrode and a pad. Then, a Ti film having a film thickness of about 200 Å and a film thickness of 500 are formed by the electron beam evaporation method.
An Al film of about 0Å is sequentially laminated as the electrode material 58 (FIG. 6 (B)). Next, the electrode material 58 is lifted off by removing the upper mask 56 using an organic solvent. The electrode material 48 remaining on the base material 46 is the gate electrode 6
0 and pads (not shown) are formed (FIG. 6C).
Although the pad forming windows provided in the upper layer mask 56 and the lower layer mask 48 have substantially the same planar shape, the cross-sectional shape of the pad has a substantially rectangular shape, but the upper layer mask 56 and the lower layer mask 48 have the same shape.
The plane shape of the gate electrode forming window provided in the upper layer mask 5 is
Since 6 is wider, the gate electrode 60 has a substantially T-shaped cross section. Next, the lower layer mask 48 is removed from the substrate 48 by, for example, plasma etching (see FIG.
(D)), formation of the gate electrode 60 and the pad is completed. The gate length of the gate electrode 60 is equal to the opening length H3 (= H1) of the window 48a provided in the lower mask 48, and is about 0.15 μm, for example.

Next, DCFL of applying the semiconductor device manufacturing method of the present invention (D irect C oupled F E
For T L ogic) of the manufacturing process will be described with reference to FIGS.

First, a GaAs substrate 71 having an element isolation region 70 formed therein is prepared by O ⁺ ion implantation. Although not shown, an active layer is formed on the GaAs substrate 71 by an epitaxial growth method. (Fig. 8
(See (A))

Next, the ohmic electrodes 72 to be the source / drain electrodes are formed by the lift-off method. Here, the interval between the ohmic electrodes 72 is 3 μm. (Fig. 8
(See (B))

Next, to cover the GaAs substrate 71 surface and the ohmic electrode 72 Plasma CVD (C hemica
by using the l V apour D eposition),
The SiN film 73 is deposited to 1000 Å. (See FIG. 8C)

Next, after coating a resist on the entire surface, the resist is patterned, RIE (R eactive the resist 74 thus patterned as a mask
By I on E tching), E- FET region 75
The SiN film 73 on the ohmic electrode 72 inside is removed.
(See FIG. 8D)

Next, after removing the resist 74, a resist for forming a gate pattern for the E-FET region 75 and the D-FET region 76 is applied on the entire surface, this resist is patterned, and this patterned resist 77 is formed. Form. Here, the resist 77 is a negative resist. The resist 77 is FSMR (manufactured by Fuji Chemical Industry Co., Ltd.)
The resist thickness was 0.7 μm. The exposure of the resist 77 using an i-line stepper, which is one of the phase shift method PEL (P hase-shifter E
carried out by dge L ine) method. As the exposure condition, the focus condition is set so that the resist pattern in the E-FET region 75 is exposed with the best focus. The purpose is to make the opening inversely tapered. The exposure dose is 200 mJ · cm ^-2 . At this time, S is formed on the ohmic electrode 72 in the D-FET region 76.
Since the iN film 73 is provided, the light intensity distribution of the portion where the pattern is formed is different from that of the E-FET region 75, and the resist cross-sectional shape of the E-FET region 75 is inversely tapered, whereas the D-FET region 76 is. Has a forward tapered shape, and the resist lower portion is narrower than the resist 77 upper portion. (See FIG. 8E) The SiN film 73 is etched by RIE using the gate pattern resist 77 as a mask. Here, the opening width of the SiN film 73 is equal to the E-FET region 7
5 is wider than the D-FET region 76, and E-FE
The thickness is 0.2 μm on the T side and 0.15 μm on the D-FET side. (See FIG. 9 (A))

Next, after removing the resist 75, a pattern for gate lift-off is formed by the resist 78. Here, FSMR is used as the resist 78, and the resist thickness is 0.7 μm. Also, E-FET region 75 and D
The reason why the shape of the opening of the resist 78 in the -FET region 76 is an inverse taper is that the opening width is set to be wide, so that the focus margin is wide and the influence of the base shape is less likely to occur. (See FIG. 9B)

Further, using the resist 78 as a mask, Ga
The surface of the As substrate 71 is recess-etched to a depth of 1000Å. (See FIG. 9C)

Next, the E-FET region 75 and the D-FET
To form each gate metal 79 in the region 76, Ti /
Al = 200Å / 5000Å is deposited by the electron beam evaporation method. (See FIG. 9D)

Next, after the gate metal 79 is vapor-deposited, the lift-off method, that is, the resist 78 is removed, so that each gate electrode 80 in the E-FET region 75 and the D-FET region 76 is formed. Further, the SiN film 73 is removed to complete the E-FET and D-FET. Where E
The gate length of the −FET is 0.2 μm, and the gate length of the D-FET is 0.15 μm. As described above, according to this manufacturing process, since the FETs can be formed on the same substrate by changing the gate length, the E-FET and the D-FET can be formed by the short channel effect even though the recess etching is the same. It becomes possible to divide.

The present invention is not limited to the above-described embodiments, and therefore, the constitution, shape, forming material, forming method, numerical conditions, disposition position and the like of each constituent can be arbitrarily changed. The semiconductor device manufacturing method of the present invention can form T-shaped electrodes of various electric circuit elements. For example, the T-shaped electrode forming method of the present invention can be used to form MESFETs, HEMTs, MOSFETs, diodes or bipolar transistors. The control electrode has a fine width T
It may be formed as a V-shaped electrode. Further, the method of forming the gate electrode and the pad is not limited to that of the above-mentioned embodiment. Therefore, the recess may not be formed, or the gate electrode and the pad may be formed in separate forming steps without forming the gate electrode and the pad in parallel, and the first exposure mask used for forming the gate electrode may be formed. The gate electrode may be formed by removing the light-shielding portion for forming the pad from the first and second masks, or the gate electrode of the base material may be formed by forming the gate electrode and the pad in separate steps. You may make it form a recess in a formation area. Further, a T-shaped electrode other than the gate electrode may be formed, and thus the T-shaped electrode may be formed using only the first exposure mask without using the second exposure mask.

[0057]

As is apparent from the above description, according to the method of manufacturing a semiconductor device of the present invention, the phase of light transmitted through the exposure mask through the phase shifter and the exposure mask does not pass through the phase shifter. The phase of the light transmitted by is almost 1
Since it shifts by 80 °, when a negative resist is exposed by a projection exposure method using this exposure mask, the portion corresponding to the phase shifter edge of the negative resist (edge corresponding portion)
The intensity of the light radiated on the object becomes weak due to the interference of the light. Therefore, the edge-corresponding portion can be exposed to the extent that the property of dissolving it in the developing solution is not lost, so that the edge-corresponding portion can be formed as an unexposed portion that is not substantially exposed. Moreover, a very narrow thin line-shaped unexposed portion can be formed at this edge-corresponding portion.

Furthermore, since the width (or area) of the unexposed portion formed in the edge corresponding portion can be controlled by the exposure amount, the exposure amount can be controlled even if a common exposure mask is used for exposing the first and second resists. By controlling, the unexposed portion having a width wider than the unexposed portion of the first resist can be formed in the second resist. Therefore, since the T-shaped electrode can be formed by the projection exposure method, particularly the reduced projection exposure method, instead of using the EB direct writing method, the productivity can be improved. Further, even if the same exposure mask is used, the width of the unexposed portion of the first resist can be changed to a desired width by controlling the exposure amount. Therefore, T-shaped electrodes having various widths are referred to as exposure amount control. It can be formed by a simple method.

[Brief description of drawings]

1A and 1B are a plan view and a sectional view schematically showing the structure of a first exposure mask used in an embodiment of the present invention.

2A and 2B are a plan view and a cross-sectional view schematically showing the configuration of a second exposure mask used in an embodiment of the present invention.

3 (A) and 3 (B) are plan views for explaining an unexposed portion formed on a resist by two exposures using the first and second exposure masks.

4 (A) to 4 (D) are cross-sectional views schematically showing a step of forming a T-shaped gate electrode formed in the embodiment of the present invention.

5A to 5D are cross-sectional views schematically showing a step of forming a T-shaped gate electrode formed in the embodiment of the present invention.

6A to 6D are cross-sectional views schematically showing a step of forming a T-shaped gate electrode formed in the embodiment of the present invention.

FIG. 7 is a diagram showing a relationship between an opening length of a window formed in the resist and an exposure amount of the resist when the resist is exposed using the first exposure mask.

8A to 8E are cross-sectional views schematically showing manufacturing steps of a semiconductor device to which the invention is applied.

9A to 9E are cross-sectional views schematically showing manufacturing steps of a semiconductor device to which the invention is applied.

10A and 10B are cross-sectional views schematically showing a conventional process for forming a T-shaped gate electrode.

11A and 11B are cross-sectional views schematically showing a conventional process for forming a T-shaped gate electrode.

[Explanation of symbols]

22 first exposure mask (exposure mask provided with a phase shifter) 24 first light-shielding portion 26 phase shifter 26a edge of phase shifter 28,36 light transmitting portion 30 second exposure mask (other exposure mask) 32 second Light-shielding portion 34 Third light-shielding portion 46 Base material 48 Lower layer mask 50 First resist 50b First unexposed portion 52 First resist pattern 52a Window 54 Second resist 54a Second unexposed portion 56 Second resist pattern (upper layer resist)

Claims (2)

[Claims] 1. A step of forming a lower layer mask for electrode formation on a substrate, a step of applying a negative first resist on the lower layer mask, and a step of using the exposure mask having a phase shifter to perform the first step. Exposing one resist, forming a thin line-shaped first unexposed portion corresponding to the edge of the phase shifter on the first resist; and developing the first resist to remove the first unexposed portion,
A step of forming a first resist pattern, a step of etching the lower layer mask through the first resist pattern to form a thin line window exposing the base material in the lower layer mask, and removing the first resist pattern Then, a step of applying a negative type second resist on the lower layer mask having the window formed thereon, and exposing the second resist with an exposure amount smaller than that of the first resist using the exposure mask, Forming a second fine line-shaped second unexposed portion on the second resist which is arranged on the window and is wider than the window; and developing the second resist to remove the second non-exposed portion,
A step of forming a second resist pattern as an upper layer mask for electrode formation, and a step of laminating an electrode material on the base material through the lower layer and the upper layer mask, and then removing the lower layer and the upper layer mask. A method for manufacturing a semiconductor device, comprising: 2. Aside from the exposure using the exposure mask, a light-shielding portion is provided at a position corresponding to an electrode pattern portion of an edge of the phase shifter, and a position corresponding to a non-electrode pattern portion of an edge of the phase shifter is provided. The method for manufacturing a semiconductor device according to claim 1, wherein the first and second resists are exposed using another exposure mask having a light transmitting portion.