JPH05218098A - Heterojunction field-effect transistor and its manufacture - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to provide a heterojunction field effect transistor in which the source / drain series resistance is reduced. [Structure] An n-type GaAs operating layer 3 is formed on a semi-insulating GaAs substrate 1 with an i-type GaAs buffer layer 2 interposed therebetween, and a gate electrode 5 is formed with an i-type AlGaAs layer 4 interposed therebetween. The n-type AlGaAs layer 4 is provided only immediately below the gate electrode 5, and n ⁺ formed on the n-type GaAs operating layer 3 is formed in the source and drain regions close to the gate region. The type GaAs layer 6 and the n ⁺⁺ type GaAs layer 7 which is formed on the type GaAs layer 6 and is formed slightly apart from the gate region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction field effect transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A field effect transistor having a heterojunction such as GaAs / AlGaAs is a conventional GaAsME.
It has various advantages that SFET does not have, and is attracting attention as a high-speed device. As a typical example of this kind of heterojunction field effect transistor, a HEMT (High Electron M) is used.
mobility Transistor) and DMT (Doped-channel MI)
S-like gate Transistor).

FIG. 7 is a sectional view of a conventional DMT. This DMT comprises an n-type G on a semi-insulating GaAs substrate 11 via an undoped (i-type) GaAs buffer layer 12.
The aAs operating layer 13 and the i-type AlGaAs layer 14 are formed using a wafer in which epitaxial growth is sequentially performed. A gate electrode 15 made of a heat-resistant metal such as WSi is formed on the AlGaAs layer 14, and Si is ion-implanted using the gate electrode as a mask to form high-concentration n-type layers 16 ₁ and 16 ₂ in the source and drain regions. There is.
For example, AuGe / N is formed on the high concentration n-type layers 16 ₁ and 16 _2.
Ohmic electrodes 17 ₁ and 17 ₂ made of i are formed.

The advantage of such a conventional DMT is that a layer having an electron affinity lower than that of the operating layer exists between the n-type GaAs operating layer 13 and the gate electrode 15 in which electrons travel.
This is to improve the forward breakdown voltage of the gate. Normal ME
In the SFET, when the gate length is shortened to improve the performance, it is necessary to make the operating layer shallow and have a high concentration in order to suppress the two-dimensional effect of the electric field in the operating layer. Then, since the Schottky gate electrode is directly formed in the operating layer, the tunnel current through the Schottky barrier increases, the so-called ideal factor (n value) deteriorates, and the barrier height decreases. The problem arises. In particular, the decrease in barrier height causes a decrease in logic amplitude and a decrease in operation margin when a logic circuit such as DCFL is configured. This is because the forward current flows at a low gate voltage. On the other hand, the DMT can maintain a high forward voltage even when the gate length is shortened, and is therefore superior to the MESFET as a basic element forming a logic circuit.

However, in the conventional DMT, a layer having an electron affinity lower than that of the operating layer which maintains a high forward voltage causes an increase in series resistance of the source and drain. That is, the layer with a small electron affinity is
It acts as a potential barrier against the gate forward characteristic, and functions to prevent electron injection from the gate electrode to the operating layer. However, since this layer also exists in the source and drain regions, the source electrode to the operating layer, or This is because it also serves as a barrier for electron injection from the operating layer to the drain electrode.

In the DMT of FIG. 7, a high concentration n-type layer is formed in the source and drain regions by ion implantation,
The drain series resistance is reduced. However, AlGa
The As layer generally has a lower activation rate of implanted ions than the GaAs layer, so that the AlGaAs layer cannot have sufficiently low resistance, and the potential barrier of the GaAs / AlGaAs heterojunction cannot be sufficiently low.

[0007]

As described above, the conventional heterojunction field effect transistor has a problem in that although a high gate forward breakdown voltage can be obtained, the series resistance of the source and drain cannot be sufficiently reduced.

The present invention has been made in consideration of such circumstances, and an object thereof is to provide a heterojunction field effect transistor in which the source / drain series resistance is reduced.

[0009]

According to the present invention, a first semiconductor layer serving as an operating layer and an electron affinity and a band gap larger than those of a first semiconductor layer formed on the first semiconductor layer are provided. A heterojunction field effect transistor having a second semiconductor layer, a gate electrode formed on the second semiconductor layer, and a source / drain region formed so as to sandwich the gate electrode, (a) wherein The second semiconductor layer is provided only under the gate electrode, and

(B) The source and drain regions include a third semiconductor layer formed on the first semiconductor layer and made of the same material as the second semiconductor layer and in the vicinity of the gate electrode. Formed on the third semiconductor layer with the same material as the gate electrode at a predetermined distance from the gate electrode;
It is characterized in that it has a stacked structure with a fourth semiconductor layer which is heavily doped with impurities.

The present invention is also a method for manufacturing such a heterojunction field effect transistor, which comprises a first semiconductor layer, which serves as an operating layer, and an electron affinity smaller than that of the first semiconductor layer and a bandgap on the semiconductor substrate. A large second semiconductor layer is sequentially grown, a gate electrode is formed on the second semiconductor layer, and then the second semiconductor layer is etched by using the gate electrode as a mask to expose the first semiconductor layer, and the exposed A third semiconductor layer made of the same semiconductor material on the first semiconductor layer
Selectively grows the semiconductor layer of the
An insulating film is formed on the side wall of the semiconductor layer, and using the gate electrode and the insulating film as a mask, the fourth semiconductor layer, which is made of the same semiconductor material and is highly doped with impurities, is formed on the third semiconductor layer. Is characterized by selective growth.

[0012]

In the present invention, the semiconductor layer having a small electron affinity and a large band gap exists only directly under the gate electrode, and the source and drain regions are composed of the same semiconductor layer capable of being doped with the same high-concentration impurities as the operating layer. .. Therefore, there is no potential barrier in the portion where electrons flow from the source electrode to the operating layer and from the operating layer to the drain electrode. As a result, the series resistance of the source and drain can be greatly reduced while maintaining the high forward breakdown voltage of the gate electrode portion, and a high-performance heterojunction field effect transistor can be obtained.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional structure of a DMT according to an embodiment of the present invention. This DMT is composed of a semi-insulating GaAs substrate 1, an n-type GaAs buffer layer 2 and an n-type GaA.
The s-operation layer 3 (first semiconductor layer) is epitaxially grown. On the n-type GaAs operating layer 3, a material having a smaller electron affinity and a larger bandgap is used.
A type AlGaAs layer 4 (second semiconductor layer) is epitaxially grown, and a gate electrode 5 made of WSi which is a heat resistant metal is formed on the epitaxial AlGaAs layer 4. The AlGaAs layer 4 is provided only below the gate electrode 5.

N-type GaAs is used for the source and drain regions.
On the operating layer 3, in contact with the i-type AlGaAs layer 4 or slightly apart, a relatively high concentration of n ⁺ Type GaAs layer 6
(6 ₁ , 6 ₂ ) (third semiconductor layer) is formed, and a sufficiently high concentration n ^{+ +} type GaAs layer 7 (7 ₁ , 7, ₂ ) is further formed on the (6 ₁ , 6 ₂ ) with a predetermined distance from the gate electrode 5. (Fourth semiconductor layer) is formed. On the n ⁺⁺ type GaAs layer 7, A
Source / drain electrodes 8 (8 ₁ , 8) made of uGe alloy
₂ ) has been formed.

To give concrete numerical examples of the concentration and thickness of each part, the i-type GaAs buffer layer has a thickness of 500 nm and an n-type Ga.
The As operating layer 3 has an impurity concentration of 2 × 10 ¹⁸ / cm ³ , Thickness about 6
nm. The i-type AlGaAs layer 4 has a thickness of about 20 nm and is n ⁺ Type GaAs layer 6 has an impurity concentration of 3 × 10 ¹⁸ / c
m ³ , Thinner than the i-type AlGaAs layer 4, about 15 nm
And The n ⁺⁺ type GaAs layer 7 is formed from the gate electrodes 5 to 0.
Formed at a distance of 2 μm with an impurity concentration of 5 × 10 ¹⁸ / c
m ³ And have a thickness of 300 nm.

In the DMT of this embodiment, the i-type AlGaAs layer 4 is present between the gate electrode 5 and the n-type GaAs operating layer 3, and therefore, the performance that the forward breakdown voltage of the gate is high is maintained. On the other hand, the source and drain regions are
Since the electron flow paths between the source and drain electrodes and the n-type GaAs operating layer are all the same GaAs layer as the operating layer, there is no potential barrier for electrons in these paths. Therefore, the series resistance of the source and drain is greatly reduced.

Further, in the structure of this embodiment, n ^{+ of the} source and drain regions are Type GaAs layer 6 is i type AlGaAs layer 4
Are formed in contact with or slightly separated from each other. That is, in the n-type GaAs operation layer 3, except for the region controlled by the gate electrode 5 (that is, the region immediately below the i-type AlGaAs layer 4), the n ⁺ It is covered with a type GaAs layer 6. Therefore, it is possible to avoid the influence of the surface level that the surface depletion layer extends in the n-type GaAs operating layer 3 to increase the resistance thereof.

Further, in this embodiment, the high concentration layer (n ^{+) for} reducing the resistance of the source / drain regions is used. Type GaAs layer 6 and n ⁺⁺ type GaAs layer 7) are formed above the n type GaAs operating layer 3. Therefore, the two-dimensional effect of the electric field on the n-type operating layer through the i-type GaAs buffer layer 2 is alleviated as compared with the conventional one in which the high-concentration source and drain layers are formed deeper than the operating layer, and the short channel The effect is less likely to occur. As a result, the gate can be further shortened as compared with the conventional structure, and the gate capacitance Cgs can be reduced and the current driving force gm can be improved.

Further, in this embodiment, n ^{+ of the} source and drain regions are Type GaAs layer 6 is i type AlG under the gate electrode 5.
It is thinner than the aAs layer 4. This is important for reducing the capacitance between the gate electrode and the source / drain regions. From the viewpoint of series resistance reduction, this n ⁺ The type GaAs layer 6 is also preferably thick to some extent, but if the type GaAs layer 6 is thicker than the i-type AlGaAs layer 4 and is too close to the gate electrode 5, the capacitance sharply increases.
This capacitance acts as a so-called fringing capacitance that is independent of the intrinsic capacitance of the FET, that is, the capacitance between the gate electrode and the operating layer, and is not reduced even if the gate length is shortened. This fringing capacitance appears to be relatively large as the gate length is shortened to reduce the intrinsic capacitance, which is a major factor in hindering high-speed operation of the device. In this embodiment, n ^{+ which} is thinner than the i-type AlGaAs layer 4 in the portion close to the gate Type G
As the aAs layer 6, an n ⁺⁺ type GaAs layer 7 for achieving a sufficiently low resistance is laminated on the aAs layer 6 at a predetermined distance from the gate to prevent the fringing capacitance from increasing,
The source and drain series resistance can be reduced.

Next, an embodiment of the DMT manufacturing method according to the present invention will be described with reference to FIGS. First, on the semi-insulating GaAs substrate 1, the molecular beam epitaxy method (MBE
Method) or a vapor phase growth method (MOC) using an organic metal gas.
VD method), i-type GaAs buffer layer 2, n-type Ga
The As operating layer 3 and the i-type AlGaAs layer 4 are sequentially epitaxially grown with a thickness of 500 nm, 6 nm and 200 nm, respectively. The AlGaAs layer 4 has an Al molar ratio of 0.3, for example. Then, a gate electrode material such as tungsten silicide (WSi) or tungsten nitride (WN), which is a heat-resistant metal, is deposited on the epitaxial wafer to a thickness of 150 to 500 nm, and then processed by ordinary lithography and dry etching. Thus, the gate electrode 5 is formed (FIG. 2 (a)).

Next, the i-type AlGaAs layer 4 is selectively removed by etching using the gate electrode 5 as an etching resistant mask (FIG. 2 (b)). At this time, as the etching liquid, for example, a mixed liquid of HCl (hydrochloric acid) and H ₂ O ₂ (hydrogen peroxide solution) is used. This etching solution is GaAs
Since AlGaAs can be etched with a selection ratio of 50 times or more, the n-type GaAs operating layer 3
The i-type AlGaAs layer 4 can be selectively removed without damaging the.

Then, using the gate electrode 5 as a mask for selective growth, n ⁺ is formed only on the n-type GaAs operating layer 3 by MOCVD. The type GaAs layer 6 is epitaxially grown to a thickness of about 15 nm (FIG. 2 (c)). This MOCVD is
For example, trimethylgallium (Ga (CH
₃ ) ₃ ) and arsine (AsH ₃ ) are used, and silane (SiH ₄ ) is used as a doping gas.

After that, an insulating film 9 such as a CVD silicon oxide film is deposited on the entire surface and is etched by anisotropic etching to leave only on the side walls of the gate electrode 5 and the i-type AlGaAs layer 4 (FIG. 3 (a)). ). Side wall insulating film 9 (9 ₁ , 9
The width of ₂ ) is about 0.2 μm.

Further, using the gate electrode 5 and the side wall insulating film 9 as a mask, the n ^{+ is} again formed by the MOCVD method. Type GaAs layer 5
An n ⁺⁺ type GaAs layer 7 is selectively grown on the upper surface to a thickness of about 500 nm. Finally, an AuGe alloy is vapor-deposited, lift-off processed, and alloyed at 400 ° C. to form the source / drain electrodes 8 (FIG. 3 (b)).

An embodiment of another manufacturing method of the present invention will be described with reference to FIG. I-type Ga on the semi-insulating GaAs substrate 1
As buffer layer 2, n-type GaAs operating layer 3, i-type AlG
After the epitaxial growth of the aAs layer 4 to form the gate electrode 5, the i-type Al is formed using the gate electrode 5 as a mask.
The process up to the selective etching of the GaAs layer 4 is the same as in the previous embodiment. After that, the first insulating film 10 is deposited and etched back by anisotropic etching to leave it on the side wall (FIG. 4 (a)). Here, the first sidewall insulating film 10 (10
₁ , 10 ₂ ) are thin with a width of about 0.05 μm.

After that, using the gate electrode 5 and the first sidewall insulating film 10 as a mask, n ⁺ The type GaAs layer 6 is selectively grown (FIG. 4 (b)). At this time, the gate electrode 5 and the i-type AlG
Since the side wall of the aAs layer 4 is not exposed, the gate electrode 5
And n ⁺ The risk of contact of the type GaAs layer 6 is completely eliminated.
After that, a second sidewall insulating film 9 is formed, and n ⁺⁺ type GaAs is formed.
A layer 7 is selectively grown, and a source / drain electrode 8 is formed on the layer 7.
Are formed (FIG. 4 (c)).

In this embodiment, the first side wall insulating film 1
The reason why 0 is formed is firstly to prevent the influence of the surface depletion layer. An n ⁺ layer formed in the next step on the n-type GaAs operating layer 3 except in the region directly below the gate electrode 5 Type G
If there is a portion where the aAs layer 6 does not exist, the resistance of the n-type GaAs operating layer 3 is increased due to the influence of the surface depletion layer. By providing the first sidewall insulating film 10, it is possible to reduce the distance in which the high resistance region due to the influence of the surface depletion layer enters the region immediately below the gate.

The second reason is that n ⁺ formed next is formed. Type Ga
This is to more reliably prevent the contact between the As layer 6 and the gate electrode 5. In the previous embodiment, n ⁺ Type GaAs layer 6
The selective selectivity for the gate electrode 5 can be secured relatively easily during the selective growth of i.
The selectivity for the type AlGaAs layer 4 cannot be secured. In that case, the side wall of the i-type AlGaAs layer 4 also has n
⁺ The type GaAs layer 6 grows and comes into contact with the gate electrode 5. This causes inconveniences such as a decrease in gate forward breakdown voltage, an increase in leak current, and an increase in gate capacitance. According to this embodiment, the gate electrode 5 and n ⁺ The contact of the type GaAs layer 6 is surely prevented. Also n ⁺ As a result of widening the conditions for ensuring the growth selectivity of the type GaAs layer 6, a large process margin can be obtained.

FIG. 5 shows another embodiment of the manufacturing method of the present invention.
And it demonstrates using FIG. In the examples so far,
While an i-type AlGaAs single layer was used as the second semiconductor layer, in this embodiment, as the second semiconductor layer,
A laminated structure of AlGaAs / GaAs / AlGaAs is used. MBE method or M method on the semi-insulating GaAs substrate 1
I-type GaAs buffer layer 2, n-type G by OCVD method
aAs operation layer 3, i-type AlGaAs layer 4 _1, i-type GaA
The s layer 4 ₂ and the i-type AlGaAs layer 4 ₃ are sequentially epitaxially grown. That is, the i-type AlGa in each of the above embodiments
AlGaA with GaAs sandwiched in the middle of the As layer 4
The s layer 4 ₁ / GaAs layer 4 ₂ / AlGaAs layer 4 _{3 has} a laminated structure. The thickness of each layer, for example, 5 nm 5 nm the AlGaAs layer 4 _1, the GaAs layer 4 _2, AlGaAs layer 4
_{3 is set} to 15 nm. After that, the gate electrode 5 made of WSi, WN or the like is formed (FIG. 5 (a)).

Next, using the gate electrode 5 as a mask, the i-type AlGaAs layer 43 is selectively etched using a mixed solution of HCl and H ₂ O ₂ , and then the intermediate i-type GaAs layer 4 is etched.
₂ is selectively etched by reactive ion etching (RIE) using CCl ₂ F ₂ gas (FIG. 5 (b)). RIE using this gas can etch the GaAs with a large selection ratio with respect to the AlGaAs layer, thereby a thin i-type state AlGaAs layer 4 ₁ was left obtained.

After that, the first sidewall insulating film 10 is formed for the same purpose as in the previous embodiment (FIG. 5 (c)). Then, using the gate electrode 5 and the sidewall insulating film 10 as a mask, the i-type A
The ₁ GaAs layer 4 ₁ is selectively etched using a mixed solution of HCl and H ₂ O ₂ to expose the n-type GaAs operating layer 3,
n ⁺ The type GaAs layer 6 is selectively grown (FIG. 6 (a)). Further, the second sidewall insulating film 10 is formed, the n ⁺⁺ type GaAs layer 7 is selectively grown, and the source and drain electrodes 8 are formed thereon (FIG. 6 (b)).

According to this embodiment, the first side wall insulating film 1
When etching back to form 0, the underlying layer is n
I-type AlGaAs layer 4 ₁ instead of i-type GaAs operating layer 3
Therefore, the n-type GaAs operating layer 3 is prevented from being damaged by RIE. When conducting the epitaxial growth on the layer that received the RIE damage, or caused defects in the growth layer, abnormal growth or cause, in this embodiment, i-type AlGaAs layer 4 ₁ Damaged n ⁺ Since it is removed before the selective growth of the type GaAs layer 6, such inconvenience does not occur. The n-type GaAs operating layer 3 is RI
The situation that resistance is increased due to E damage is also prevented. As described above, according to this embodiment, the high performance DMT
Can be obtained with a high yield.

Next, concrete data for comparing the performance of the DMT of the embodiment of the present invention (FIG. 1) with that of the conventional example (FIG. 7) will be described. Both gate lengths were 0.3 μm. In the source and drain regions of the conventional example, Si ions are accelerated with a gate electrode as a mask at an acceleration voltage of 50 keV and a dose of 1 × 1.
0 ¹⁴ / cm ² Was formed under the conditions of, and was subjected to rapid thermal annealing at 900 ° C. for 5 minutes.

First, regarding the short channel effect, when the threshold value in the case of a gate length of 4 μm is used as a reference and the fluctuation of the threshold value is examined, it is as large as 250 mV in the conventional example, and the drain conductance (δ
Id / δVd) was 30 mS / mm, which did not show good pinch-off characteristics. On the other hand, in this embodiment,
The amount of threshold fluctuation was small at 150 mV (60% reduction), and the drain conductance was 15 mS / mm, indicating good pinch-off characteristics. These differences are caused by n ^{+ of the} source and drain in the conventional example. While the mold layer is formed deeper than the operating layer, n ⁺ is used in this embodiment. The result is that the mold layer is formed above the operating layer and the two-dimensional effect of the electric field on the channel is suppressed.

Next, current drive capacity (mutual conductance)
The source series resistance that influences gm was 0.5 Ω · mm in the conventional example, whereas it was 0.
It was reduced to about 1/2 at 25 Ω · mm. This is because in the conventional example, an AlGaAs layer having a small electron affinity exists between the source electrode and the operating layer, and a potential barrier of about 0.3 eV exists, whereas in this example, such a barrier exists. This is because it does not. As a result, the current drivability gm was 650 mS / mm in the conventional example, whereas it was 830 mS / mm in this example, an improvement of about 30%. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention, such as using other semiconductor material systems.

[0037]

As described above, according to the present invention, the potential barrier between the source / drain electrodes and the operation layer is eliminated while maintaining the advantage of the conventional DMT that the gate forward breakdown voltage is high. To provide a heterojunction field effect transistor which realizes a high current driving force by reducing series resistance of a source and a drain, and suppresses a two-dimensional effect of an electric field on an operating layer to enable further shortening of a gate. You can

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a DMT according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process (first half) of the same embodiment.

FIG. 3 is a view showing a manufacturing process (second half) of the same embodiment.

FIG. 4 is a view showing a manufacturing process of another embodiment.

FIG. 5 is a view showing a manufacturing process (first half) of still another embodiment.

FIG. 6 is a view showing a manufacturing process (second half) of the same embodiment.

FIG. 7 is a diagram showing a cross-sectional structure of a conventional DMT.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate, 2 ... i-type GaAs buffer layer, 3 ... n-type GaAs operating layer (first semiconductor layer), 4 ... i-type AlGaAs layer (second semiconductor layer), 5 ... gate electrode, 6 (6 ₁ , 6 ₂ ) ... n ⁺ -Type GaAs layer (third semiconductor layer), 7 (7 _1, 7 ₂₎ ... n ⁺⁺ type GaAs layer (fourth semiconductor layer), 8 (8 _1, 8 ₂₎ ... source, drain electrode, 9 ( 9 ₁ , 9 ₂ ), 10 (10 ₁ , 10 ₂ ) ... Sidewall insulating film.

Front page continuation (72) Inventor Kazuya Nishibori 1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research Institute, Inc. (72) Inventor Mayumi Moritsuka 1st Komukai-shiba-cho, Saiwai-ku, Kawasaki, Kanagawa (72) Inventor, Tokuhiko Matsunaga, No. 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Stock Company, Toshiba Research Institute

Claims (3)

[Claims] 1. A first semiconductor layer serving as an operation layer, and the first semiconductor layer.
A second semiconductor layer having a smaller electron affinity and a larger band gap than the first semiconductor layer formed on the second semiconductor layer, and a gate electrode formed on the second semiconductor layer,
In a heterojunction field effect transistor having a source / drain region formed by sandwiching the gate electrode, the second semiconductor layer is provided only directly under the gate electrode, and the source / drain region is A third semiconductor layer formed on the first semiconductor layer by the same material as the second semiconductor layer and in proximity to the gate electrode;
Heterojunction, characterized in that it has a laminated structure with a fourth semiconductor layer doped with a high concentration of impurities and formed on the semiconductor layer of the same material at a predetermined distance from the gate electrode. Type field effect transistor. 2. A step of sequentially growing, on a semiconductor substrate, a first semiconductor layer to be an operating layer and a second semiconductor layer having a smaller electron affinity and a larger band gap than the first semiconductor layer, and the second semiconductor layer is formed on the second semiconductor layer. Forming a gate electrode on the first semiconductor layer, exposing the first semiconductor layer by etching the second semiconductor layer using the gate electrode as a mask, and using the gate electrode as a mask, the first semiconductor layer A step of selectively growing a third semiconductor layer made of the same semiconductor material as above, a step of forming an insulating film on sidewalls of the gate electrode and the second semiconductor layer, and a mask of the gate electrode and the insulating film. And a step of selectively growing on the third semiconductor layer a high concentration impurity-doped fourth semiconductor layer made of the same semiconductor material as the third semiconductor layer. Method of manufacturing a heterojunction field effect transistor that. 3. A step of sequentially growing, on a semiconductor substrate, a first semiconductor layer to be an operation layer and a second semiconductor layer having a smaller electron affinity and a larger band gap than the first semiconductor layer, and the second semiconductor layer is formed on the second semiconductor layer. A step of forming a gate electrode on the gate electrode, a step of etching the second semiconductor layer with the gate electrode as a mask leaving a predetermined thickness, and a first insulating layer on the sidewall of the gate electrode and the second semiconductor layer thereunder. A step of forming a film; a step of etching the remaining second semiconductor layer to expose the first semiconductor layer by using the gate electrode and the first insulating film as a mask; Using the first insulating film as a mask, selectively growing a third semiconductor layer made of the same semiconductor material on the first semiconductor layer; and forming a second insulating film on the side wall of the first insulating film. And a fourth semiconductor layer made of the same material as the third semiconductor layer and doped with a high concentration of impurities, using the gate electrode and the first and second insulating films as a mask. And a step of selectively growing the heterojunction field effect transistor.