JPH05218331A - Contact hole formation method - Google Patents

Abstract

(57) [Abstract] [Purpose] To form a contact hole in a semiconductor device in a self-aligned manner without performing a high temperature heat treatment such as a BPSG flow. [Structure] At least two gate electrode patterns 29 are formed on a silicon substrate 21 via a LOCOS oxide film 28, and an oxide film 34, a nitride film 35 and ozone TEOS are formed on the entire surface.
The films 36 are sequentially formed, and a part of the ozone TEOS film 36 is removed by etching back to planarize the ozone TEOS film.
A contact hole resist pattern 37 is formed on the film 36, and the TEOS film 36, the nitride film 35, and the oxide film 34 are etched using the resist pattern 37 as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole, and more particularly to a silicon semiconductor DRAM (Dynamic
The present invention relates to a method for forming a bit line contact of a Randam Access Memory) in a self-aligned manner.

[0002]

2. Description of the Related Art A high density memory such as 16M DRAM is formed by a stacked capacitor cell having two self-aligned contacts as shown in FIG.

According to FIG. 3, 1 is a silicon (Si) substrate,
Reference numeral 2 is a word line, 3 is a bit line contact, 4 is a storage node, 5 is a storage node contact, and 6 is a cell plate. That is, the bit line contact 3 is formed in a self-aligned manner in the memory shown in FIG.

4 and 5 are sectional views showing a process of forming the bit line contact shown in FIG. 3 by self-alignment.

First, as shown in FIG. 4A, after a LOCOS oxide film 8 is formed on a silicon (Si) substrate 1, a gate polysilicon (poly-Si) layer 9, a SiO ₂ film 10 and a SiO ₂ sidewall are formed. After forming 11 by the CVD method, a diffusion layer 12 is formed by ion implantation and annealing. An HTO (High T
An emperature oxide (SiO ₂ ) film 14 is formed, and a Si ₃ N ₄ film 15 and a BPSG film 16 are further formed.

Next, after applying a photoresist on the entire surface, bit contact patterning of the photoresist is performed to form a resist pattern, and as shown in FIG. 4B, the resist pattern 17 is used as a mask to form the BPSG film 16.
Is wet-etched with an HF-based solution.

Next, as shown in FIG. 5A, the Si ₃ N ₄ film 15 and H in the contact hole are anisotropically etched.
The TO film 14 is removed to expose the Si substrate 1. Then, after removing the resist pattern 17, a BPSG flow is performed to further flatten the polysilicon film 18 and the tungsten silicide (WSix) film 19 which are the second layer wiring.
Are sequentially formed (FIG. 5B).

In this way, the contact hole can be formed in a self-aligned manner.

[0009]

In fine processing (lithography technique), a negative resist may be used for a contact hole opening. The negative resist often has a reverse taper shape because the portion where the light is irradiated (absorbs the light) remains as a pattern. In such a case, processing control is usually performed by the upper surface regulation. This upper surface regulation processing is possible only by using anisotropic (vertically downward) dry etching, and in wet etching, the etching proceeds isotropically.
If the inverse taper becomes tight, it is not possible to perform etching at a predetermined location with high precision.

If the step on the upper surface of the BPSG film 16 is steeper as shown in FIG.
A film of ly-Si or the like is formed, and p on the side surface of the steep step is formed.
When it was necessary to remove poly-Si, some poly-Si remained in the lower part of the side surface.

The BPSG flow of the above process is 900
Although heat treatment is required at a temperature of about ° C, heat treatment at a high temperature other than drive-in is not desirable from the viewpoint of realizing a shallow PN junction required for a highly integrated device.

Therefore, an object of the present invention is to form a contact hole in a self-aligned manner without performing a high temperature heat treatment such as a BPSG flow.

[0013]

According to the present invention, the above-mentioned object is to form at least two gate electrode patterns having an oxide film on the upper and sidewalls of a silicon substrate through a LOCOS oxide film. An oxide film, a nitride film, and ozone tetraethoxysilane (TEO) are used as an interlayer insulating film.
S) a step of sequentially forming a film, a step of removing a part of the ozone TEOS film by etching back to planarize it, and then a resist pattern on the ozone TEOS film to form a contact between the gate electrode patterns. And a step of sequentially removing the ozone TEOS film, the nitride film and the oxide film by etching using the resist pattern as a mask.

[0014]

According to the present invention, an oxide film 34 of SiO ₂ or the like, a nitride film 35 of Si ₃ N ₄ or the like and an ozone TEOS film 36 are sequentially formed thereon as an interlayer insulating film on the gate electrode pattern. This ozone TEOS film 36 is 350-400.
Stable CVD growth can be performed even at a temperature as low as about 0 ° C. without forming voids even on a step, and since resist patterning is performed after planarization, a good vertical resist pattern can be formed.

Moreover, since the resist pattern 37 is formed on the ozone TEOS film 36 in order to form the contact between the gate electrode patterns 29, the contact hole regulated by the gate electrode even if the pattern is misaligned. Can be formed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 are process sectional views showing an embodiment of the present invention.

First, as shown in FIG. 1A, a LOCOS oxide film 28 is formed on the surface of a silicon (Si) substrate 21 in the same manner as in the conventional method, and then a 200 nm thick n ⁺ gate p is formed.
An oli-Si layer (gate electrode pattern) 29, and a SiO ₂ film 30 having a thickness of 150 nm are formed thereon by depositing by a CVD method and patterning by a lithography technique. In the figure, two gate electrode patterns 29 are shown. Further, after depositing SiO ₂ with a thickness of 250 nm by the CVD method, etch back is performed by anisotropic etching by RIE to form SiO ₂ sidewalls 31 on the side surfaces of the gate portion. Thus, a gate electrode pattern having an oxide film on the upper and side walls was formed.

Further, a dose amount of 5 × 10
Arsenic (As) ions are ion-implanted into the Si substrate 21 at ¹⁵ / cm ² and an annealing treatment is performed at a temperature of 900 ° C. for 30 minutes to form the n ⁺ diffusion layer 22. After that, thickness 30 on the entire surface
A TEOS oxide film (SiO ₂ ) 34 having a thickness of nm is deposited and formed. Next, after forming a Si ₃ N ₄ film 35 having a thickness of 20 nm by a low pressure (LP) CVD method, ozone tetraethoxysilane (O ₃ -TEOS) is deposited at a temperature of about 380 ° C. to a thickness of 500 nm, and the whole surface is deposited. 350 nm thickness by etch back
In this state, an ozone TEOS film 36 is formed to fill the groove between the gate polysilicon layers (gate electrodes) 29 and to perform planarization.

Next, a resist pattern 3 patterned on the ozone TEOS film 36 corresponding to the contact holes.
After forming 7, a buffer hydrofluoric acid solution is etched for 2 minutes. In this etching, the Si ₃ N ₄ film 35 remains because it is insoluble in hydrofluoric acid.

As a variation in the case where the contact holes are wet-etched after being planarized with ozone TEOS, the ozone TEOS is densified by annealing at 800 ° C. for 30 minutes after planarization, and the contact holes are patterned to form P, As, Si. There is a case where the ozone TEOS in the contact hole is damaged by ion implantation of the above, and the wet etching rate is locally increased. By this method, lateral erosion due to wet etching can be suppressed.

Next, as shown in FIG. 2A, CF ₄ / O ₂
Residual Si ₃ N ₄ film 35 and TEOS thereunder by plasma etching (anisotropic dry etching) using gas
By removing the oxide film 34 and then removing the resist pattern 37 as shown in FIG. 2B, the contact hole 40 can be formed in a self-aligned manner.

[0023]

As described above, according to the present invention, the BP
High temperature such as SG (phosphorus-boron glass) flow (about 9
Low temperature heat treatment (about 350-40)
Since the interlayer insulating film can be flattened at 0 ° C., a stable self-aligned contact hole can be formed.

[Brief description of drawings]

FIG. 1 is a first-half process sectional view of an embodiment of the present invention.

FIG. 2 is a sectional view of a second half process of the embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a multilayer capacitor cell having two self-aligned contacts.

FIG. 4 is a sectional view of a first half process of a conventional example.

FIG. 5 is a cross-sectional view of the second half process of a conventional example.

[Explanation of symbols]

1, 21 Silicon (Si) substrate 2 Word line 3 Bit line contact 4 Storage node 5 Storage node contact 6 Cell plate 8, 28 LOCOS oxide film 9, 29 Gate poly-Si layer (gate electrode pattern) 10, 30 SiO ₂ film 11, 31 SiO ₂ film sidewalls 12, 22 diffusion layer 14 HTO (SiO ₂ ) film 15, 35 Si ₃ N ₄ film 16 BPSG film 17, 37 resist pattern 36 ozone TEOS film

Claims (2)

[Claims] 1. A step of forming at least two gate electrode patterns on a silicon substrate with an oxide film on the upper and side walls through a LOCOS oxide film, an oxide film, a nitride film and ozone tetraethoxy as an interlayer insulating film on the entire surface. A step of sequentially forming a silane film, a step of removing a part of the ozone tetraethoxysilane film by etching back to planarize, and a step of forming a contact between the gate electrode patterns on the ozone tetraethoxysilane film. And a step of sequentially removing the ozone tetraethoxysilane film, the nitride film, and the oxide film by using the resist pattern as a mask. 2. The method of forming a contact hole according to claim 1, wherein the ozone tetraethoxysilane film is wet-etched, and the nitride film and the oxide film are anisotropically dry-etched.