JPH05218403A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the operating characteristics of semiconductor devices. [Structure] On the boundary region between the active region and the inactive region, MI
The gate length of the gate electrode 9 of the SFET is increased. [Effect] The distance between the source and drain regions 10 becomes large in the boundary region between the active region and the non-active region. As a result, the length of the leak path due to the crystal defect becomes long. In addition, it becomes difficult to form the inversion layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to a semiconductor device having a MISFET.

[0002]

2. Description of the Related Art A semiconductor device having a MOS is used. This semiconductor device is mainly composed of a semiconductor substrate. This semiconductor substrate is composed of a semiconductor substrate made of single crystal silicon and a single crystal silicon layer formed on the semiconductor substrate by an epitaxial growth method.

The MOS is provided on the main surface of the active region or the main surface of the well region of the semiconductor substrate.
The well region is provided on the main surface portion of the semiconductor substrate. The MOS is surrounded by an element isolation insulating film. The element isolation insulating film is provided on the main surface portion of the inactive region of the semiconductor substrate. The element isolation insulating film is formed by selectively thermally oxidizing the main surface of the semiconductor substrate or the well region using the silicon nitride film as an oxidation resistant mask. In addition, in the same step as the step of forming the element isolation insulating film, a semiconductor region forming a channel stopper region is formed below the element isolation insulating film in order to reduce the ON operation of the parasitic MOS. .. The semiconductor region forming the channel stopper region is of the same conductivity type as the semiconductor substrate or the well region.

The MOS is mainly composed of a gate insulating film, a gate electrode, and a pair of semiconductor regions forming a source region and a drain region, respectively. The gate insulating film is composed of a silicon oxide film. This silicon oxide film is
It is formed by thermally oxidizing the main surface of the active region or the main surface of the well region of the semiconductor substrate. The gate electrode is provided on the gate insulating film. In the gate width direction, both ends of this gate electrode are provided so as to extend from above the gate insulating film in the active region to above the element isolation insulating film in the inactive region. A wiring is connected to the gate electrode in the region on the element isolation insulating film. Further, in the region on the element isolation insulating film, the gate length (wiring width) of the gate electrode is larger than the gate length (wiring width) of the gate electrode on the active region in order to reduce the resistance value of the gate electrode.
Is large in size.

[0005]

However, as a result of examining the above-mentioned prior art, the present inventor has found the following problems.

In the thermal oxidation step of forming the element isolation insulating film, thermal stress causes crystal defects at the end portion of the element isolation insulating film, that is, in the boundary region between the active region and the non-region. When there is a crystal defect, a leak path is formed. Therefore, in the boundary region between the active region and the inactive region, a leak path due to a crystal defect is formed between the source region and the drain region, which causes a leak current between the source region and the drain region. ..

Further, since the semiconductor region forming the channel stopper region is mainly formed so as to cover the bottom of the element isolation insulating film, it is non-conductive with the end of the element isolation insulating film, that is, the active region. The boundary region with the region has a lower impurity concentration than the other regions. Further, in the step of forming the element isolation insulating film, the impurity concentration in the main surface portion of the semiconductor substrate or the well region is lowered in the boundary region between the active region and the inactive region. As a result, the impurity concentration in the boundary region between the active region and the non-active region is lower than that in the other regions, so that the inversion layer is easily formed. On the other hand, since the MOS gate electrode extends over this boundary region, this boundary region forms a part of the MOS channel region. Therefore, the impurity concentration of a part of the channel region of the MOS is lowered, so that the inversion layer is easily formed.
There is a problem that the threshold voltage of is low.

An object of the present invention is to provide a technique capable of improving operating characteristics in a semiconductor device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

The gate electrode is provided on the main surface of the active region whose periphery is defined by the non-active region of the main surface of the semiconductor substrate, and at least one end of the gate electrode extends from the active region to the inactive region. In a semiconductor device having a MISFET whose region is provided in self-alignment with the gate electrode, the gate length of the gate electrode on the boundary region between the active region and the non-active region is smaller than the gate length of the gate electrode of the active region. Enlarge.

[0012]

According to the above-mentioned means, the distance between the source region and the drain region is increased by making the gate length of the gate electrode larger than that of the active region on the boundary region between the active region and the inactive region. Therefore, the length of the leak path due to the crystal defect becomes long. Therefore, the leak current through the leak path is reduced. Further, since the distance between the source region and the drain region becomes large, it becomes difficult to form the inversion layer between the source region and the drain region, and M
The fluctuation of the threshold voltage of the OS can be reduced. These can improve the operating characteristics of the semiconductor device.

[0013]

Embodiments of the present invention will be specifically described below with reference to the drawings. In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

The structure of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1 (plan view of the main part) and FIG. 2 (perspective view of the main part taken along the line AA of FIG. 1).

As shown in FIGS. 1 and 2, the semiconductor device is mainly composed of a semiconductor substrate 1. The semiconductor substrate 1 is composed of, for example, a semiconductor substrate made of single crystal silicon and an n − type single crystal silicon layer formed on the semiconductor substrate by an epitaxial growth method. In FIG. 1, only the n − -type single crystal silicon layer portion is shown.

A p-type well region 2 is provided on the main surface of the semiconductor substrate 1. An element isolation insulating film (field insulating film) 6 is provided on the main surface portions of the p-type well region 2 and the inactive region of the semiconductor substrate 1. The element isolation insulating film 6 is made of, for example, a silicon oxide film. This silicon oxide film is formed by selectively thermally oxidizing the main surface portions of the inactive region of the semiconductor substrate 1 and the p-type well region 2 using a silicon nitride film as an oxidation resistant mask. Below the element isolation insulating film 6, a p + type semiconductor region 5 forming a channel stopper region is provided. The p + type semiconductor region 5 is formed simultaneously in the step of forming the element isolation insulating film 6.

As shown in FIGS. 1 and 2, an n-channel MISFETQ is formed on the main surface of the active region of the p-type well region 2 in the region defined by the element isolation insulating film 6. It is provided.

The n-channel MISFETQ is mainly composed of
The gate insulating film 8, the gate electrode 9, and the pair of n-type semiconductor regions 10 forming the source region and the drain region, respectively. The gate insulating film 8 is composed of, for example, a silicon oxide film. This silicon oxide film is formed by thermally oxidizing the main surface of the p-type well region 2. The gate electrode 9 is provided on the gate insulating film 8. The gate electrode 9 is composed of, for example, a polycrystalline silicon film. The pair of n-type semiconductor regions 10 forming the source region and the drain region are provided in the main surface portion of the p-type well region 2 in a self-aligned manner with the side portions of the gate electrode 9. Although the n-type semiconductor region 10 cannot be seen when cut along the line AA in FIG. 1, the n-type semiconductor region 10 is shown by a dotted line in FIG. 2 for easy understanding.

As shown in FIGS. 1 and 2, in the end portion of the inter-element isolation insulating film 6, that is, in the boundary region between the active region and the inactive region (region B surrounded by the chain double-dashed line in FIG. 2), The gate length of the gate electrode 9 is larger than that of the gate electrode 9 on the active region. This area B
Then, as described above, the impurity concentrations of the p + type semiconductor region 5 and the p type well region 2 forming the channel stopper region are lowered. Further, due to thermal stress for forming the element isolation insulating film 6, crystal defects are present. On the other hand, according to the configuration of the present embodiment, the distance between the n-type semiconductor regions 10 is increased by increasing the gate length of the gate electrode 9 on the boundary region between the active region and the inactive region. Therefore, the length of the leak path due to the crystal defect becomes long. Therefore, the leak current through the leak path is reduced. Further, since the distance between the n-type semiconductor regions 10 becomes large, it becomes difficult to form an inversion layer between these n-type semiconductor regions 8, and the fluctuation of the threshold voltage of the MISFET Q can be reduced. These can improve the operating characteristics of the semiconductor device.

Next, voltage-current characteristics when the gate length of the gate electrode 9 in the active region of the n-channel MISFET is variously changed are shown in FIGS. 3 to 6 (voltage-current characteristics). 3 to 6, the horizontal axis represents the gate voltage (Vg) and the vertical axis represents the drain current (Id). In addition, FIGS.
In, the curve indicated by C has a source-drain voltage of 0.
The case of V is shown, and the curve shown by D shows the case where the source-drain voltage is 5V. 3 shows a gate length of 2 μm, FIG. 3 shows a gate length of 3 μm, FIG. 4 shows a gate length of 4 μm, and FIG.
Shows the case where the gate length is 6 μm. The gate width is 1 each
The case of 8 μm is shown.

As shown in FIG. 6, when the gate length is 6 μm, there is no characteristic deterioration due to leakage current in the low current region (especially, -1E-8 or less). However, in FIG.
As shown in FIG. 5, when the gate length is 2 to 4 μm, characteristic deterioration due to leak current occurs in the low current region. Therefore, for example, when the gate length in the active region is 2 to 4 μm, the gate length in the boundary region between the active region and the non-active region is about 1.5 to 2 times, for example, about 5 to 6 μm. MISFET
It is possible to reduce or prevent the deterioration of characteristics.

Next, FIG. 7 (a diagram showing the relationship between the gate length and the leakage current) shows the relationship between the gate length and the leakage current between the source / drain regions. In FIG. 7, E is the characteristic of the conventional MISFET, and F is the MISFET of this embodiment.
Shows the characteristics of.

As indicated by E in FIG. 7, as the gate length becomes shorter, the leak current increases. On the other hand, according to the configuration of the present embodiment, as shown by F in FIG. 7, by increasing the gate length of the gate electrode in the boundary region between the inactive region and the active region, the active region With the same gate length, leakage current can be reduced. That is, the characteristics of the MISFET can be improved.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. ..

For example, in the above embodiment, the n-channel MI is used.
Although shown as an SFET, the present invention is not limited to p-channel MISFE.
It can also be applied to T.

Further, in the above-mentioned embodiment, the example in which the element isolation insulating film is provided on the main surface portion of the inactive region of the semiconductor substrate has been shown. However, the present invention has a groove on the main surface portion of the inactive region of the semiconductor substrate. It is also possible to apply the present invention to a semiconductor device in which an element is isolated by this groove or an element is isolated by an insulating film embedded in the groove and the groove.

[0027]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

In the semiconductor device, the operating characteristics can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a perspective view of an essential part taken along the line AA of FIG.

FIG. 3 is a diagram showing a relationship between a gate voltage and a drain current with respect to a gate length.

FIG. 4 is a diagram showing a relationship between a gate voltage and a drain current with respect to a gate length.

FIG. 5 is a diagram showing a relationship between a gate voltage and a drain current with respect to a gate length.

FIG. 6 is a diagram showing a relationship between a gate voltage and a drain current with respect to a gate length.

FIG. 7 is a diagram showing a relationship between a gate length and a leak current.

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... P-type well region, 5 ... Channel stopper region, 6 ... Inter-element isolation insulating film, 8 ... Gate insulating film, 9 ... Gate electrode, 10 ... Source region, drain region.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideki Yasuoka 111 No. Nishiyote-cho, Takasaki-shi Gunma Hitachi Takasaki factory (72) Inventor Toyomasa Koda 111 Nishi-Yokote-cho, Takasaki Gunma Hitachi Co., Ltd. Takasaki Factory

Claims (1)

[Claims] 1. A source region, wherein at least one end of a gate electrode is provided on a main surface of an active region whose periphery is defined by a non-active region of the main surface of a semiconductor substrate and extends from above the active region to above the inactive region. In a semiconductor device having a MISFET in which a drain region and a drain region are provided in self-alignment with the gate electrode, the gate length of the gate electrode on the boundary region between the active region and the inactive region is determined by A semiconductor device characterized by being made larger than the length.