JPH05219403A - Synchronization converter - Google Patents

Abstract

PURPOSE:To prevent discontinuity of an output signal and deterioration in the picture quality from being caused by reading new and old data from a digital memory and not converting a field or a frame even in an uncertain region. CONSTITUTION:An analog television video signal inputted from a video signal input terminal (a) is digitized by an A/D converter circuit 2 and stored in a digital memory circuit 3 based on a write address (c). An in-phase read address (d) and a lead phase read address (e) are generated based on a reference synchronizing signal inputted from a reference signal input terminal (b). A timing detection circuit 11 detects whether or not the relation between the write address (c) and the in-phase read address (d) is resident in a new/old data read uncertain region of the digital memory circuit 3, and when the relation is in existence, the data are read from the lead phase read address (e) and the read data are delayed by a delay changeover circuit 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous converter for correcting a time axis of an input video signal by using a digital memory called a frame synchronizer capable of storing a video signal of several fields or more.・ Read / write in the old / new data indeterminate area of memory
The present invention relates to a circuit for preventing reading of a video signal containing old and new data which is generated by access.

[0002]

2. Description of the Related Art Conventionally, this type of synchronous conversion device detects whether or not read / write access to a digital memory is performed in the old and new data uncertain areas, and executes in the old and new data uncertain areas. Digital if
The read access is changed to a field in which old and new data of the memory are not mixed and read, and the field or frame is converted by data interpolation of the read data or color signal data polarity inversion processing.

[0003]

In the above-described conventional television video signal synchronization conversion apparatus, since the fields or frames are exchanged, the discontinuity of the television video signal and the deterioration of the image quality occur at the output of the apparatus. There is a drawback.

[0004]

The synchronous converter of the present invention is an A / D conversion circuit for converting an input analog video signal from an analog amount to a digital amount, and a digitized signal by this A / D conversion circuit. A digital memory circuit for recording and reading out a video signal in a plurality of fields, a D / A conversion circuit for converting the digital video signal read out from the digital memory circuit from a digital amount to an analog amount, and the inputted analog video signal A write address generation circuit for generating a write address to the digital memory circuit; and a common mode read address generation circuit for generating a common mode read address to the digital memory circuit from an input reference synchronization signal, the input The input analog video signal is time-axis corrected and synchronized with the input reference sync signal. In the synchronous conversion device, a phase read address generating circuit for generating a phase read address advanced from the input synchronous reference address from the synchronous read address, and an address of the write address and the common mode read address. A timing detection circuit for detecting read / write access in the old / new data read indeterminate area of the digital memory circuit from the value, and the common mode read address and the phase advance controlled by a detection signal from the timing detection circuit. A read address switching circuit that switches the read address and sends the read address to the digital memory circuit, and a delay switching circuit that adjusts the deviation of the device delay in the digital memory circuit reading based on the phase read address. Contains.

[0005]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a television video signal synchronization conversion apparatus according to an embodiment of the present invention.

The analog television video signal input from the video signal input terminal a is sent to the clamp circuit 1 and the write system sync separation circuit 6.

In order to stabilize the digital conversion of the analog television video signal, the pedestal level is made constant by the clamp circuit 1 and sent to the A / D conversion circuit 2 to become a digital television video signal.

On the other hand, the write-system synchronization separation circuit 6 generates vertical, horizontal, and hue timing pulses and sampling clocks synchronized with the input analog television video signal, and the write address generation circuit 7 is generated based on these timing pulses. A write address c is created at. The write address c is sent to the digital memory circuit 3 and the timing detection circuit 11.

The digital memory circuit 3 has a capacity for storing television video signals of several fields or more,
The digital television video signal sent from the / D conversion circuit 2 is stored based on the write address c.

The reference sync signal input from the reference signal input terminal b generates vertical / horizontal / hue timing pulses and sampling clocks synchronized with the reference sync signal in the read-out system sync separation circuit 8, These are sent to the in-phase read address generation circuit 9 and the phase read address generation circuit 10.

The in-phase read address generation circuit 9 produces the in-phase read address d, and the advanced read address generation circuit 10 produces the advanced read address e.
The in-phase read address d is sent to the timing detection circuit 11 and the read address switching circuit 12, and the phase read address e is sent to the read address switching circuit 12.

The timing detection circuit 11 detects whether or not the relationship between the write address c and the in-phase read address d is within the old and new data read indefinite areas of the digital memory circuit 3 based on both address values. A read address switching signal f is generated based on the detection result and sent to the read address switching circuit 12 and the delay switching circuit 4.

In the read address switching circuit 12,
Based on the read address switching signal f, digital
If the read / write access of the memory circuit 3 is performed within the old / new data reading uncertain area, the leading phase read address e is read, and if it is performed in the old / new data reading fixed area, the in-phase read address d is read. It is sent to the digital memory circuit 3 as the address g.

In the digital memory circuit 3, the stored digital television video signal is read based on the read address g and sent to the delay switching circuit 4.

The delay switching circuit 4 does not delay the digital television image signal read from the digital memory circuit 3 when the in-phase read address d is used, and does not delay when the in-phase read address e is used. The read address d is switched by the read address switching signal f to delay the read address d by the amount of a phase advance, and is sent to the D / A conversion circuit 5 as a digital television video signal with a constant delay amount.

The D / A conversion circuit 5 converts the sent digital television video signal into an analog television video signal and sends it to the video signal output terminal h.

As described above, an analog television video signal synchronized with the reference sync signal and having the same phase is output to the video signal output terminal h.

[0019]

As described above, according to the present invention, in the old and new data reading uncertain areas of the digital memory,
Since the delay circuit switching control is performed without performing field or frame conversion of the television image signal, stable operation is possible without causing discontinuity of the television image signal or image quality deterioration at the device output. ..

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 Clamp circuit 2 A / D conversion circuit 3 Digital memory circuit 4 Delay switching circuit 5 D / A conversion circuit 6 Write system sync separation circuit 7 Write address generation circuit 8 Read system sync separation circuit 9 In-phase read address generation circuit 10 Advance read address generation circuit 11 Timing detection circuit 12 Read address switching circuit

Claims (1)

[Claims] 1. An A / D conversion circuit for converting an input analog video signal from an analog amount to a digital amount, and the A / D conversion circuit.
A digital memory circuit for recording and reading a plurality of fields of a video signal digitized by a D / A conversion circuit, and a D / A conversion circuit for converting the digital video signal read from the digital memory circuit from a digital amount to an analog amount A write address generation circuit that generates a write address from the input analog video signal to the digital memory circuit, and a common mode read address that generates a common mode read address from the input reference synchronization signal to the digital memory circuit In a synchronous converter having a generating circuit and synchronizing the input analog video signal with the input reference sync signal by time-axis correction, the synchronous read address from the input reference sync signal is read. Advanced phase read address to generate advanced phase read address And a timing detection circuit for detecting a read / write access in the old / new data read indeterminate area of the digital memory circuit from the address value of the write address and the in-phase read address, and the timing detection circuit A read address switching circuit that sends the read address to the digital memory circuit by switching between the in-phase read address and the advanced read address controlled by a detection signal, and the digital memory circuit based on the advanced read address. A synchronous conversion device, comprising: a delay switching circuit for adjusting a deviation of device delay in reading.