JPH05219413A - Digital filter - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to provide a digital filter capable of obtaining an appropriate filter output at an image end without increasing the hardware scale. [Structure] Each multiplier 103, 106, 109, 112,
Selectors 104, 107, 110, 113, 11 for selecting respective tap coefficients 115, 118, 120
When 6, 11, 119 and 121 are connected and a filtering process is performed on a video signal, when a signal other than the video signal is input to each multiplication circuit, the tap coefficient of the multiplication circuit to which this signal is input is changed to 0. Along with changing at least one tap coefficient of other multiplication circuits,
Optimize the filter output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter used for video signal processing.

[0002]

2. Description of the Related Art The configuration of a conventional digital filter for filtering video signals is shown in FIG. 3 by taking a 7-tap vertical filter as an example.

In the figure, reference numeral 301 designates an input terminal. The signals input from the input terminal 301 are connected to the six 1H delay units 302 and 30 connected in series.
3, 304, 305, 306, and 307 are sequentially input. Input signal and six 1H delays 302, 303,
The seven signals in total of the output signals of 304, 305, 306, 307 are respectively multipliers 308, 309, 310, 3
11, 312, 313, 314, and after being multiplied by tap coefficients A _-3 , A _-2 , A ₀ , A ₁ , A ₂ , and A ₃ ,
Is output. Each multiplier 308, 309, 310, 31
The outputs of 1, 312, 313, and 314 are all adders 31.
5, the sum of all multiplication results input here is obtained. The output of the adder 315 is the output terminal 3
16 and is the output of the filter.

Now, assume that a signal as shown in FIG. 4A is input to the filter. In the figure, L ₁ to L ₅
Is a signal of the non-image portion, and L ₆ to L ₁₄ are video signals corresponding to the image portion. Here, as shown in FIG. 4B, when the center tap (the signal input to the multiplier 311 located in the center) is L ₁₀ , the filter output is A ₋₃ L ₇ + A _−2.
L ₈ + A _-1 L ₉ + A ₀ L ₁₀ + A ₁ L ₁₁ + A ₂ L ₁₂ + A ₃
It becomes L ₁₃ . Thus, if all of the signals to be multiplied by the tap coefficient are video signals, correct filtering is performed.

On the other hand, as shown in FIG. 4C, when the center tap is L ₆ , the filter output is A _-3 L ₃ + A _-2 L ₄ + A _-1 L ₅ + A ₀ L ₆ + A ₁ L ₇ +
It becomes A ₂ L ₈ + A ₃ L ₉ . However, since L ₃ , L ₄ , and L ₅ are non-image parts, for example, if the value is 0, the filter output is A ₀ L ₆ + A ₁ L ₇ + A ₂ L ₈ + A ₃ L ₉ , which is correct. No filter output is obtained. Also L ₇ ,
The same applies to the filter output of L ₈ .

As for the actual signal waveform, if the filter is a low-pass filter, a change point from the non-image portion to the image portion, that is, a sharp rise between the signal L ₅ and the signal L ₆ may occur. is there. When this steep rise occurs, unnecessary linking occurs in the filter output.

As described above, at the edge of the image, the signal to which the tap coefficient is multiplied includes a signal other than the video signal, so that an appropriate filter output cannot be obtained.

Therefore, a method of optimizing the filter output is generally used by extending the video signal at the end of the image by several lines.

FIG. 5 is a block diagram showing the structure of the extension processing section. The extension processing unit performs extension processing of signals for three lines if the digital filter is to perform filter processing of 7 taps.

As shown in the figure, the extension processing section comprises an input terminal 501, a selector 502, a one-line memory 503, a three-line delay unit 504 and an output terminal 505. In the extension processing unit, the signals input to the input terminal 501 are output to the selectors 502, 1
It is input to the line memory 503 and the 3-line delay unit 504 at the same time. The outputs of the 1-line memory 503 and the 3-line delay device 504 are input to the selector 502. The output of the selector 502 is output to the filter through the output terminal 505.

Next, the operation of this extension processing will be described with reference to FIG.

When the signal L _{6 of the first} line of the image portion is input to the input terminal 501, the selector 502 selects the input signal to the input terminal 501 and outputs it to the output terminal 505. At the same time, the input signal is written as data in the 1-line memory 503 and input to the 3-line delay unit 504.

The selector 502 outputs the signal L of the first line.
After outputting ₆ , ₆ lines of data written in the 1-line memory 503 are continuously selected and output. This gives L
₆ signals are output continuously for 3 lines. After that, the selector 502 selects the output of the 3-line delay device 504,
The signals of ₆ or less are sequentially output while being delayed by 3 lines.

Then, the signal L ₁₅ of the last line of the image portion is set to 1
After being written as data in the line memory 503 and the signal L ₁₅ of the last line is output through the 3-line delay unit 504, the selector 502 selects and outputs the data written in the 1-line memory 503 for 3 lines in succession.
In this way, the signals for three lines are extended even at the lower end of the image portion.

However, by performing such a stretching process, the signal input of the non-image portion is eliminated in the filtering process of the video signal, and an appropriate filter output can be obtained at each end of the image.

However, in order to realize this extension processing, a total of four lines of memory capacity of the one-line memory 503 and the three-line delay unit 504 are required, which leads to an increase in hardware scale. Moreover,
In the above example, a 7-tap filter is explained, but in order to obtain a filter with sufficient characteristics, a filter with a larger number of taps is required, and a larger number of extension lines and memory capacity are required.

[0017]

As described above, in the conventional digital filter, by performing the signal stretching process before the filtering process, it becomes possible to obtain an appropriate filter output even at the end of the image. However, there is a problem that the scale of hardware is increased by providing the extension processing unit.

The present invention has been made to cope with such a situation, and an object of the present invention is to obtain an appropriate filter output at the end of an image with almost no increase in the scale of hardware. The purpose is to provide a digital filter that can.

[0019]

In order to achieve the above-mentioned object, the digital filter of the present invention includes a plurality of delay circuits which are connected in series and delay and output an input signal at an equal time. The sum of the multiplication results of each of the multiplying circuits and each of the multiplying circuits for multiplying a plurality of input signals to each delay circuit and / or the plurality of output signals from each of the delay circuits by a predetermined tap coefficient and outputting the product When a signal other than a video signal is input to at least one of the multiplication circuits in the case of performing a filtering process on the addition circuit and the video signal, the tap coefficient of the multiplication circuit to which the signal is input is changed to 0 and , And means for changing at least one tap coefficient of the other multiplication circuits.

[0020]

According to the digital filter of the present invention, when a video signal is filtered, at least one of the multiplication circuits receives a signal other than the video signal, for example, a signal of a non-image portion, so that the filter output is properly adjusted. In order to realize the above, the tap coefficient of the multiplication circuit to which the signal is input is changed to 0, and at least one tap coefficient of another multiplication circuit is changed. As a result, with a simple configuration, it is possible to obtain the same effect as in the case of performing the known signal extension processing, that is, an appropriate filter output for the video signal at the image end.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a digital filter according to an embodiment of the present invention.

The digital filter shown in the figure has a plurality of 1's each delaying a signal input from the input terminal 101 by 1H.
H delay devices 102, 105, 108, 111, 114, 1
17 and the input signal from the input terminal 101 and the individual 1
H delay devices 102, 105, 108, 111, 114, 1
Multiple multipliers 1 for multiplying 17 output signals by tap coefficients
03, 106, 109, 112, 115, 118, 12
0 and each multiplier 103, 106, 109, 112, 11
A plurality of selectors 104, 107, 110, 113, 116, 11 for selecting tap coefficients of 5, 118, 120
9, 121 and each multiplier 103, 106, 109, 11
An adder 122 that adds the multiplication results of 2, 115, 118, and 120, and an output terminal 1 that outputs the result of the filtering process.
And 23.

In the digital filter having such a configuration, the signal input from the input terminal 101 is first input to the first 1H delay device 102 and the first multiplier 103. The first multiplier 103 receives the input signal and the first
The multiplier 104 performs multiplication with the tap coefficient selected by the selector 104, and outputs the result to the adder 122. At this time the first
Selector 104 selects and outputs either A ₃ or 0 as the tap coefficient. On the other hand, the first 1H delay unit 102 delays the input signal by 1H and outputs it.

The output of the first 1H delay device 102 is input to the second 1H delay device 105 and the second multiplier 106. The second multiplier 106 multiplies the input signal by the tap coefficient output from the second selector 107,
The result is output to the adder 122. At this time, the second selector 107 selects and outputs one of the three types of tap coefficients A ₂ , A ₂ + A ₃ , and 0. On the other hand, the second 1H delay unit 105 delays the input signal by 1H and outputs it.

The output of the second 1H delay unit 105 is input to the third 1H delay unit 108 and the third multiplier 109, and similarly, the multiplication with the tap coefficient and the delay of 1H are performed respectively. At this time, the third selector 11
For 0, one is selected from three types of tap coefficients of A ₁ , A ₁ + A ₂ + A ₃ , and 0, and is output.

The output of the third 1H delay unit 108 is input to the fourth 1H delay unit 111 and the fourth multiplier 112, and similarly, the multiplication with the tap coefficient and the delay of 1H are performed respectively. At this time, the fourth selector 11
3 is A ₀ , A ₀ + A ₁ + A ₂ + A ₃ , A _-3 + A _-2 + A
One of the three tap coefficients of _-1 + A ₀ is selected and output.

The output of the fourth 1H delay unit 111 is input to the fifth 1H delay unit 114 and the fifth multiplier 115, and similarly, the multiplication with the tap coefficient and the delay of 1H are performed respectively. At this time, the fifth selector 11
6 selects and outputs one of the three types of tap coefficients of A _-1 , A _-3 + A _-2 + A _-1 , and 0.

The output of the fifth 1H delay unit 114 is input to the sixth 1H delay unit 117 and the sixth multiplier 118, and similarly, the multiplication with the tap coefficient and the delay of 1H are performed respectively. At this time, the sixth selector 11
9 selects and outputs the tap coefficient from among A _-2 , A _-3 + A _-2 , and 0.

The output of the sixth 1H delay unit 117 is input to the seventh multiplier 120, where it is multiplied with the tap coefficient. At this time, the seventh selector 121 selects and outputs either A _-3 or 0 as the tap coefficient.

Then, each of the multipliers 103, 106, 109,
All the multiplication results of 112, 115, 118, 120 are input to the adder 122, and the adder 122 calculates the sum of all the multiplication results. The addition result of the adder 122 is output from the output terminal 123 as the result of the filtering process.

Next, referring to FIG. 2, selector 104, 107, 110, 113, 11 will be used to describe the operation of filtering the video signal with this digital filter.
The operations of Nos. 6, 119 and 121 will be mainly described. In this operation, the signal input to the intermediate multiplier, that is, the fourth multiplier 112 is referred to as the center tap. For the sake of simplicity, consider a signal of 20 lines here. Here, L ₆ to L ₁₅ are video signals corresponding to the image portion, and L ₁ to L ₅ and L ₁₆ to L ₂₀ are signals for the non-image portion. The start point of the filtering process for the video signal is when the center tap reaches the tip of the image portion, that is, when the center tap reaches L ₆ .

In this case, that is, when the center tap is L ₆ , the first to third selectors 104, 107 and 110 select the tap coefficients of A ₃ , A ₂ and A ₁ , respectively, and the fourth selector 113. Selects A _-3 + A _-2 + A _-1 + A ₀ , and the fifth to seventh selectors 116, 119 and 121 select all 0 tap coefficients. Therefore, the filter output in this case is A _-3 L ₆ + A _-2 L ₆ + A _-1 L ₆ + A ₀ L ₆ + A ₁ L ₇ +
A ₂ L ₈ + A ₃ L ₉ = (A _-3 + A _-2 + A _-1 + A ₀ ) L ₆ + A ₁ L ₇ + A ₂ L
It becomes ₈ + A ₃ L ₉ . The output of this filter is the same as when the signal of L ₆ is extended by three lines by the extension processing.

When L ₇ is a center tap, the first to fourth selectors 104, 107, 110 and 113 select A ₃ , A ₂ , A ₁ and A ₀ , respectively, and the fifth selector 116 is For A _-3 + A _-2 + A _-1 , the sixth and seventh selectors 119 and 121 select the tap coefficient of 0 respectively. Therefore, in this case, the filter output is (A _-3 + A _-2 + A _-1 ) L ₆ + A ₀ L ₇ + A ₁ L ₈ + A ₂
It becomes L ₉ + A ₃ L ₁₀ .

Further, when L ₈ is a center tap, the first to fifth selectors 104, 107, 110, 113, 1
16 selects A ₃ , A ₂ , A ₁ , A ₀ , and A _-1 , respectively, the sixth selector 119 selects A _-3 + A _-2 , and the seventh selector 121 selects 0. As a result, the filter output is (A _-3 + A _-2 ) L ₆ + A _-1 L ₇ + A ₀ L ₈ + A ₁ L ₉ +
It becomes A ₂ L ₁₀ + A ₃ L ₁₁ .

When the center tap is L ₉ , that is, when the signals to be multiplied by the tap coefficient are all video signals corresponding to the image portion, the selectors 104, 107, 110, 113, 1
16, 119 and 121 respectively select A ₃ , A ₂ , A ₁ , A ₀ , A _-1 , A _-2 and A _-3 as tap coefficients. Therefore, the filter output is: A _-3 L ₆ + A _-2 L ₇ + A _-1 L ₈ + A ₀ L ₉ + A ₁ L ₁₀ +
It becomes A ₂ L ₁₁ + A ₃ L ₁₂ .

Similarly, when L ₁₀ to L ₁₂ are center taps, the selectors 104, 107, 110 and 11 are similarly selected.
₃ , 116, 119, and 121 select A ₃ , A ₂ , A ₁ , A ₀ , A _-1 , A _-2 , and A _-3 as tap coefficients, respectively.

When L ₁₃ is a center tap, the first selector 104 selects 0 and the second selector 107 selects A ₂ +.
Select A ₃ . Furthermore, the third to seventh selectors 11
0, 113, 116, 119 and 121 are A ₁ and
Select A ₀ , A _-1 , A _-2 , A _-3 . As a result, the output of the filter is A _-3 L ₁₀ + A _-2 L ₁₁ + A _-1 L ₁₂ + A ₀ L ₁₃ + A ₁ L ₁₄ +
(A ₂ + A ₃ ) L ₁₅ .

When L ₁₄ is the center tap, both the first and second selectors 104 and 107 select 0, the third selector 110 selects A ₁ + A ₂ + A ₃ , and the fourth to seventh selectors 113. , 116, 119, and 121 are A, respectively.
Select ₀ , A _-1 , A _-2 , A _-3 . Therefore, the output of the filter is: A _-3 L ₁₁ + A _-2 L ₁₂ + A _-1 L ₁₃ + A ₀ L ₁₄ + (A ₁ + A
₂ + A ₃ ) L ₁₅ .

When L ₁₅ is a center tap, the first to third selectors 104, 107 and 110 all select 0, and the fourth selector 113 is A ₀ + A ₁ + A _2.
+ A ₃ to the fifth to seventh selectors 116, 119, 1
21 selects A _-1 , A _-2 and A _-3 respectively. As a result, the filter output is A _-3 L ₁₁ + A _-2 L ₁₂ + A _-1 L ₁₃ + (A ₀ + A ₁ + A ₂ +
The A ₃₎ L _15. That is, this filter output has a value equal to that when the signal of L ₁₅ is extended by three lines by the extension processing.

Thus, according to the digital filter of this embodiment, when filtering the video signal, the multiplication circuits 103, 106, 109, 112, 115 and 1 are used.
When the signal of the non-image portion is input to either 18 or 120, all the tap coefficients of the multiplication circuit to which the signal of the non-image portion is input are changed to 0, and one of the tap coefficients of other multiplication circuits is input. The filter output can be optimized by changing the. Therefore, it is possible to perform the same filtering process as in the case where the stretching process is performed without providing the stretching process unit, and it is possible to perform the appropriate filtering process for the video signal at the image end portion. It should be noted that the change of the tap coefficient referred to here means each of the multiplication circuits 103, 106, 109, 112, 115, and 11.
This indicates a change from the tap coefficient when all the signals input to 8 and 120 are video signals corresponding to the image portion. Further, according to the present embodiment, the hardware scale can be suppressed to be much smaller than the case where the extension processing unit is provided.

Although the present embodiment has a configuration equivalent to the one in which the signal at the end of the video signal is simply stretched and then the filtering process is performed, the non-image portion is selected depending on how the tap coefficient is selected by the selector. It is also possible to extend the video signal of (4) with an appropriate function.

Further, although the case of the vertical filter has been described here, it goes without saying that the present invention can be applied to a horizontal filter, a two-dimensional filter and the like.

[0044]

As described above, according to the digital filter of the present invention, proper filter processing can be performed even at the end portion of the video signal without increasing the hardware scale, and unnecessary ringing or the like can be performed. Can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital filter according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a change in tap coefficient of each multiplier in the digital filter of FIG.

FIG. 3 is a block diagram showing a configuration of a conventional digital filter.

FIG. 4 is a diagram for explaining signal processing of an image end portion in a conventional digital filter.

FIG. 5 is a block diagram showing a configuration of a stretch processing unit in a conventional digital filter.

FIG. 6 is a diagram for explaining signal extension processing by the extension processing unit in FIG. 5;

[Explanation of symbols]

101 ... Input terminals 102, 105, 108, 111, 114, 117 ... 1
H delay device 103, 106, 109, 112, 115, 118, 1
20 ... Multipliers 104, 107, 110, 113, 116, 119, 1
21 ... Selector 122 ... Adder 123 ... Output terminal

Claims (1)

[Claims] 1. A plurality of delay circuits connected in series, each of which delays an input signal with an equal time and outputs the delayed signal, and a plurality of input signals to each of the delay circuits and / or a plurality of delay circuits from each of the delay circuits. A plurality of multiplication circuits that respectively output a predetermined tap coefficient to the output signal of, and an addition circuit that obtains the sum of the multiplication results of the respective multiplication circuits; When a signal other than a video signal is input to at least one of them, the tap coefficient of the multiplication circuit to which the signal is input is changed to 0, and at least one tap coefficient of another multiplication circuit is changed. A digital filter characterized in that