JPH0522263A - Delayed insertion / removal device - Google Patents

Abstract

PURPOSE:To prevent occurrence of a data error based on phase fluctuation between the input and output by providing an intermediate phase control circuit generating an intermediate read instruction signal and a write instruction signal from/to a phase control elastic storage based on a phase comparison signal. CONSTITUTION:A phase controlling elastic storage 5 reads an input signal written synchronously with a write instruction signal with an intermediate read instruct signal selected based on a comparison signal from a phase comparator circuit 4 among different intermediate read instruction signals generated from an intermediate read instruction generating circuit 7 and sends it to an elastic storage 3. The write to the storage 3 is similarly implemented by using an intermediate write instruction signal selected by a phase comparison signal generated from an intermediate write instruction generating circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay insertion / removal device used for digital transmission.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional delaying and inserting device. In the figure, 1 is a delay circuit that gives a preset delay to an input signal and a write command signal synchronized with the input signal, and 2 is delayed by the delay circuit 1 with the input signal and the write command signal. The selection circuit selects either the input signal or the write command signal.

An input signal 3 selected by the selection circuit 2 is stored by a write command signal selected by the selection circuit 2, and an output signal 3 is synchronized with the read command signal according to the read command signal. It is an elastic store that converts the phase and speed between input and output data by reading as.

Reference numeral 4 detects a phase difference between the write command signal selected by the selection circuit 2 and the read command signal directly input to the elastic store 3, generates a phase comparison signal, and outputs it to the selection circuit 2. It is a phase comparison circuit that does.

Next, the operation will be described. The input signal and the write command signal synchronized with this input signal are directly input to the selection circuit 2 and also delayed by a predetermined time in the delay circuit 1 and input to the selection circuit 2. The selection circuit 2 selects one of the input signal and the write command signal and the input signal and the write command signal delayed by the delay circuit 1 and sends it to the elastic store 3.

The phase comparison circuit 4 compares the phases of the write command signal selected by the selection circuit 2 and the read command signal provided to the elastic store 3, and generates a phase comparison signal based on the phase difference to generate a selection circuit. Send to 2. This phase comparison signal controls the selection circuit 2 so as to select the input signal and the write command signal having a phase that does not cause a data error when writing and reading the elastic store 3.

When the elastic store 3 receives the input signal and the write command signal thus selected by the selection circuit 2, the input signal is written in accordance with the write command signal and the stored input signal is stored. The read command signal is read according to the given read command signal and output as an output signal synchronized with the read command signal at the phase and speed required by the output side.

As a document describing a technique related to such a conventional delay insertion / removal device, for example, Japanese Patent Laid-Open No.
No. 226929 is available.

[0009]

Since the conventional delay inserting / removing device is constructed as described above, the phase difference between the input side and the output side causes a data error due to jitter, wander, or the like. However, when it is necessary to change the phase difference by switching the selection circuit 2, a data error occurs for a moment during the switching.

The present invention has been made to solve the above problems, and an object thereof is to obtain a delay insertion / removal device in which no data error occurs.

[0011]

According to a first aspect of the present invention, there is provided a delay insertion / removal device in which a delay circuit and a selection circuit are replaced by a phase control elastic store, and a phase comparison signal from the phase comparison circuit is used. Based on the intermediate phase, an intermediate read command signal for giving the timing for reading the intermediate output signal to the elastic store for phase control and an intermediate write command signal for giving the timing for writing the intermediate output signal to the elastic store are generated. A control circuit is provided.

According to a second aspect of the present invention, there is provided a delay insertion / removal device which uses the intermediate phase control circuit according to the first aspect of the present invention to output a plurality of different intermediate read command signals for giving a read timing to the elastic store for phase control. An intermediate read command generation circuit that generates, an intermediate write command generation circuit that generates a plurality of different intermediate write command signals that give write timing to the elastic store, and the intermediate signal based on the phase difference comparison signal output from the phase comparison circuit. An intermediate read instruction selection circuit that selects one of the read instruction signals and supplies it to the elastic store for phase control, and selects one of the intermediate write instruction signals based on the phase difference comparison signal, This is an alternative to the intermediate write instruction selection circuit supplied to the stick store.

[0013]

According to the elastic store for phase control in the invention described in claim 1, the intermediate phase control circuit receives the input signal written in synchronization with the write command signal, based on the phase comparison signal from the phase comparison circuit. By reading according to the generated intermediate read command signal, sending it to the elastic store as an intermediate output signal, and causing the intermediate phase control circuit to write according to the intermediate write command signal generated based on the phase comparison signal, a data error is generated. A delay insertion / removal device that does not occur is realized.

According to the elastic store for phase control in the invention described in claim 2, the intermediate read command selection circuit receives the input signal written in synchronization with the write command signal and the phase comparison signal from the phase comparison circuit. Selected according to one of the plurality of different intermediate read command signals generated by the intermediate read command generation circuit, and sends it to the elastic store as an intermediate output signal. By implementing writing according to one of a plurality of different intermediate write command signals generated by the intermediate write command generation circuit, which is selected based on the comparison signal, a delay insertion / removal device in which no data error occurs can be realized. .

[0015]

EXAMPLES Example 1. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention described in claim 1. In the figure, 3 is an elastic store, and 4 is a phase comparison circuit, which is the same as or equivalent to those of the conventional one denoted by the same reference numeral in FIG.

An input signal 5 is written according to a write command signal synchronized with the input signal, and is read according to an intermediate read control signal from an intermediate phase control circuit described later to the elastic store 3 as an intermediate output signal. It is an elastic store for phase control.

Reference numeral 6 denotes a phase control elastic store 5 based on the phase comparison signal output from the phase comparison circuit 4.
Is an intermediate phase control circuit for generating an intermediate read command signal for giving a read timing to the memory, and for generating an intermediate write command signal for giving a write timing to the elastic store 3 based on the phase comparison signal.

Next, the operation will be described. The input signal is
It is sent to the elastic store 5 for phase control together with the write command signal synchronized with the input signal, and is stored in the elastic store 5 for phase control according to the write command signal.

The phase comparison circuit 4 compares the phase of the write command signal given to the elastic store 5 for phase control with the phase of the read command signal given to the elastic store 3, and a phase comparison signal based on the phase difference. Is generated and sent to the intermediate phase control circuit 6.

In the intermediate phase control circuit 6, a data error occurs between the input signal input to the elastic store 5 for phase control and the output signal read from the elastic store 3 based on the phase comparison signal. The intermediate read command signal and the intermediate write command signal are generated in such a phase that they do not operate, and the intermediate read command signal is sent to the phase control elastic store 5 and the intermediate write command signal is sent to the elastic store 3.

The elastic store 5 for phase control reads the input signal stored according to the intermediate read command signal received from the intermediate phase control circuit 6, sends it to the elastic store 3 as an intermediate output signal, and the elastic store 3 Stores its intermediate output signal in accordance with the intermediate write command signal from intermediate phase control circuit 6.

Then, when the elastic store 3 is supplied with the read command signal, the elastic store 3 reads the intermediate output signal stored in accordance with the read command signal, and outputs the intermediate output signal in synchronization with the read command signal as a phase requested by the output side. , Output at speed.

Example 2. 2 is a block diagram showing an embodiment of the invention described in claim 2, and the same parts as those in FIG.

In the figure, reference numeral 7 is an intermediate read command generation circuit for generating a plurality of different intermediate read command signals for giving the read timing to the phase controlling elastic store 5, and 8 is the write timing to the elastic store 3. Is an intermediate write command generating circuit for generating a plurality of different intermediate write command signals for applying the signal.

Further, reference numeral 9 selects one of the plurality of intermediate read command signals output from the intermediate read command generation circuit 7 based on the phase difference comparison signal output from the phase comparison circuit 4, and the phase control elastic is selected. An intermediate read instruction selection circuit to be supplied to the store 5, 10 is based on the phase difference comparison signal,
This is an intermediate write instruction selection circuit that selects one of a plurality of intermediate write instruction signals generated by the intermediate write instruction generation circuit 8 and supplies it to the elastic store 3.

As described above, in this embodiment, the intermediate phase control circuit 6 of the embodiment shown in FIG. 1 is replaced by the intermediate read instruction generating circuit 7, the intermediate write instruction generating circuit 8, the intermediate read instruction selecting circuit 9, And the intermediate write instruction selection circuit 10 is used instead.

Next, the operation will be described. Here, since the basic operation is the same as that of the embodiment shown in FIG. 1, only different parts will be described below.

In the phase control elastic store 5, the intermediate read instruction selecting circuit 9 outputs a plurality of different intermediate read instructions generated by the intermediate read instruction generating circuit 7 from the input signal written in synchronization with the write instruction signal. The signal is read out according to the intermediate read command signal selected based on the phase comparison signal from the phase comparison circuit 4, and it is sent to the elastic store 3 as an intermediate output signal.

The elastic store 3 outputs the intermediate output signal sent from the phase controlling elastic store 5 to the plurality of different intermediate write signals generated by the intermediate write command generation circuit 8 by the intermediate write command selection circuit 10. From the included command signal,
It writes according to the intermediate write command signal selected based on the phase difference comparison signal, and reads it as an output signal according to the given read command signal.

[0030]

As described above, according to the invention described in claim 1, the conventional delay circuit and the selection circuit are replaced by the elastic store for phase control, and the elastic phase control circuit is replaced by the intermediate phase control circuit. Since the intermediate read command signal to the stick store and the intermediate write command signal to the elastic store are generated based on the phase comparison signal from the phase comparison circuit, the phase of the input signal can be selected without selection / switching. There is an effect that a delay insertion / removal device can be obtained that is capable of controlling the delay time and preventing the occurrence of a momentary data error when the phase changes between input and output.

According to a second aspect of the present invention, the intermediate phase control circuit of the first aspect of the invention is provided with an intermediate read instruction generating circuit, an intermediate write instruction generating circuit, an intermediate read instruction selecting circuit, and an intermediate read instruction selecting circuit. Since the write command selection circuit is used as an alternative, the phase of the input signal can be controlled without selection / switching, and the occurrence of momentary data errors when the phase changes between input and output are prevented. There is an effect that a delay insertion / removal device capable of

[Brief description of drawings]

FIG. 1 is a block diagram showing a delay insertion / removal device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of the invention described in claim 2.

FIG. 3 is a block diagram showing a conventional delay insertion / removal device.

[Explanation of symbols]

3 Elastic Store 4 Phase comparison circuit 5 Elastic store for phase control 6 Intermediate phase control circuit 7 Intermediate read instruction generation circuit 8 Intermediate write instruction generation circuit 9 Intermediate read instruction selection circuit 10 Intermediate write instruction selection circuit

Claims (2)

[Claims] 1. A phase control elastic store in which an input signal is written by a write command signal synchronized with the input signal, and an intermediate output signal read from the phase control elastic store is written in and a read command is issued. An elastic store that is read out as an output signal in synchronization with the signal, a phase comparison circuit that detects a phase difference between the write command signal and the read command signal and generates a phase comparison signal, and a phase that the phase comparison circuit outputs. And an intermediate phase control circuit for generating an intermediate read command signal for giving a read timing to the phase controlling elastic store and an intermediate write command signal for giving a write timing to the elastic store based on a comparison signal. Delayed insertion and removal device. 2. A phase control elastic store in which an input signal is written by a write command signal synchronized with this input signal, and an intermediate output signal read from the phase control elastic store is written in and a read command is issued. An elastic store that is read out as an output signal in synchronization with a signal, a phase comparison circuit that detects a phase difference between the write command signal and the read command signal and generates a phase comparison signal, and the elastic store for phase control. Intermediate read command generating circuit for generating a plurality of different intermediate read command signals for giving a read timing, and intermediate write command generating for generating a plurality of different intermediate write command signals for giving a write timing to the elastic store Circuit and the output of the intermediate read command generation circuit based on the phase comparison signal output from the phase comparison circuit. The intermediate write command is generated based on the intermediate read command selection circuit which selects one of the generated intermediate read command signals and supplies it to the phase control elastic store, and the phase comparison signal output from the phase comparison circuit. A delay insertion / removal device comprising an intermediate write instruction selection circuit for selecting one of the intermediate write instruction signals generated by the circuit and supplying the selected one to the elastic store.