JPH0522423B2 - - Google Patents

Info

Publication number
JPH0522423B2
JPH0522423B2 JP58222648A JP22264883A JPH0522423B2 JP H0522423 B2 JPH0522423 B2 JP H0522423B2 JP 58222648 A JP58222648 A JP 58222648A JP 22264883 A JP22264883 A JP 22264883A JP H0522423 B2 JPH0522423 B2 JP H0522423B2
Authority
JP
Japan
Prior art keywords
data
signal
pulse
high frequency
call
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58222648A
Other languages
Japanese (ja)
Other versions
JPS60113552A (en
Inventor
Susumu Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58222648A priority Critical patent/JPS60113552A/en
Publication of JPS60113552A publication Critical patent/JPS60113552A/en
Publication of JPH0522423B2 publication Critical patent/JPH0522423B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/02Details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、複数のデータ端末装置間で相互に
データを交換するデータ交換システムにおいて、
発呼・切断信号を伝送するための発呼・切断信号
伝送装置に関するものである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a data exchange system for mutually exchanging data between a plurality of data terminal devices.
The present invention relates to a call/disconnection signal transmission device for transmitting a call/disconnection signal.

〔従来技術〕[Prior art]

従来の発呼・切断信号は第1図に示す方法によ
つて伝送された。第1図aは元のデータ(ビツト
直列の形)を表し、同図bは発呼・切断信号を含
めて伝送されるデータを表する。元のデータは、
第1図aのD11〜D61,D12〜D62,D13〜D63に示
すように各連続する6ビツトを1単位にして区切
り、これを伝送する場合はこの6ビツト1単位の
前にFビツト(同期ビツト)を付し、この6ビツ
ト1単位の後にSビツト(制御用ビツト)を付
し、FビツトとSビツトでデータを包むようにし
て伝送する。FビツトからSビツトまでの8ビツ
トを1エンベロープ(envelope)と称し、この
ような方式をエンベロープ方式という。
Conventional call/disconnection signals were transmitted by the method shown in FIG. FIG. 1a represents the original data (in bit series form), and FIG. 1b represents the transmitted data including call/disconnect signals. The original data is
As shown in D 11 to D 61 , D 12 to D 62 , and D 13 to D 63 in FIG. An F bit (synchronization bit) is placed in front of the data, and an S bit (control bit) is placed after each 6-bit unit, and the data is transmitted so as to be wrapped in the F bit and S bit. The 8 bits from the F bit to the S bit are called one envelope, and this method is called the envelope method.

制御用ビツトであるSビツトが発呼・切断の信
号として用いられており、発呼によりSビツトの
論理は“0”→“1”と変化し、切断により
“1”→“0”と変化する。またFビツトはエン
ベロープ同期のために用いられ、1エンベロープ
ごとに“1”,“0”の論理を繰返しており、デー
タビツト及びSビツトにはこのようなビツトパタ
ーンの繰返しをするものが発生しないので、この
繰返しのビツトパターンを検出してFビツトの位
置を検出し、ビツト周期が既知であるから、エン
ベロープ中の他のビツトの位置を決定することが
できる。
The S bit, which is a control bit, is used as a call/disconnection signal; when a call is made, the logic of the S bit changes from "0" to "1", and when a call is disconnected, the logic of the S bit changes from "1" to "0". do. In addition, the F bit is used for envelope synchronization, and repeats the logic of "1" and "0" for each envelope, so that such repeating bit patterns do not occur in the data bits and S bits. Therefore, by detecting this repeated bit pattern, the position of the F bit can be detected, and since the bit period is known, the positions of other bits in the envelope can be determined.

従来は上述のような方法で発呼・切断の信号を
送出しているので、6ビツトのデータを伝送する
のにFビツト及びSビツトを付加して合計8ビツ
トを伝送することになり、伝送路上の伝送速度を
8/6倍とすることが必要で、その間の速度変換や、
Fビツトの検出などのために回路構成が複雑にな
るという欠点があつた。
Conventionally, call origination and disconnection signals were sent using the method described above, so when transmitting 6 bits of data, the F bit and S bit were added, resulting in a total of 8 bits being transmitted. It is necessary to increase the transmission speed on the road by 8/6 times, and speed conversion in between,
The disadvantage is that the circuit configuration becomes complicated due to the detection of the F bit.

〔発明の概要〕[Summary of the invention]

この発明は上記のような従来のものの欠点を除
去するためになされたもので、この発明では、デ
ータ信号のビツトタイミング信号よりも高い繰返
し周波数を有する高周波パルスを発呼・切断信号
とし、切断状態においては上記高周波パルスを送
出し、発呼状態においてはこの高周波パルスの送
出を停止してデータを送出し、受信側では受信信
号の論理変化点間の間隔を計測することによつ
て、上記高周波パルスの存在の有無を検知するよ
うにして、従来のエンベロープ方式におけるよう
なデータ速度と伝送速度間の速度変換を不要にし
たものである。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above. In this invention, a high frequency pulse having a repetition frequency higher than the bit timing signal of the data signal is used as a calling/disconnecting signal, and when the disconnection state is On the receiving side, the above-mentioned high-frequency pulse is transmitted, and in the calling state, the transmission of this high-frequency pulse is stopped and data is transmitted.The receiving side measures the interval between the logic change points of the received signal. This method detects the presence or absence of a pulse, thereby eliminating the need for speed conversion between data speed and transmission speed as in the conventional envelope method.

〔発明の実施例〕[Embodiments of the invention]

以下この発明の実施例を図面について説明す
る。第2図はこの発明の信号構成を説明するため
のタイムチヤートであり、第2図aは伝送すべき
送信データ、同図bは伝送すべき送信データのビ
ツトタイミングパルス、同図cは送信データのビ
ツトタイミングパルスよりも高い繰返し周波数を
有する高周波パルスの発呼・切断信号、同図dは
送信データと発呼・切断信号の合成、同図eは発
呼・切断信号の検出をそれぞれ示している。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a time chart for explaining the signal configuration of the present invention, in which FIG. 2a shows the transmission data to be transmitted, FIG. The figure d shows the combination of the transmitted data and the call/disconnect signal, and the figure e shows the detection of the call/disconnect signal. There is.

第3図はこの発明の一実施例を示すブロツク図
で、図において1はデータ端末装置、2はデータ
交換機、3は加入者線であるが、データ端末装置
1、データ交換機2とも加入者線3側の部分だけ
を示す。11は送信データ入力端子、12はアン
ドゲート、13はラインドライバ、14はナンド
ゲート、15は高周波パルス発生器、16は発
呼・切断スイツチ、21はラインレシーバ、22
は受信データ出力端子、23は信号検知回路、2
4は微分回路、25はDフリツプフロツプ、26
はパルス消滅監視回路、27はオアゲートであ
る。
FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a data terminal device, 2 is a data exchange, and 3 is a subscriber line. Both the data terminal device 1 and the data exchange 2 are subscriber lines. Only the third side is shown. 11 is a transmission data input terminal, 12 is an AND gate, 13 is a line driver, 14 is a NAND gate, 15 is a high frequency pulse generator, 16 is a call/disconnect switch, 21 is a line receiver, 22
is a received data output terminal, 23 is a signal detection circuit, 2
4 is a differential circuit, 25 is a D flip-flop, 26
2 is a pulse extinction monitoring circuit, and 27 is an OR gate.

以下、第3図の装置の動作を説明する。データ
端末装置1の送信データ(第2図a)は第2図b
のビツトタイミングで端子11からアンドゲート
12の一方の入力端子に入力する。アンドゲート
12の他方の端子にはナンドゲート14の出力が
接続されているが、発呼時にはスイツチ16がア
ース側(論理“0”)に接続されているので、ナ
ンドゲート14の出力は“1”となり、送信デー
タ入力はそのままの形でラインドライバ13を介
して加入者線3に出力される。
The operation of the apparatus shown in FIG. 3 will be explained below. The transmission data of the data terminal device 1 (Fig. 2 a) is shown in Fig. 2 b.
The signal is input from terminal 11 to one input terminal of AND gate 12 at the bit timing of . The output of the NAND gate 14 is connected to the other terminal of the AND gate 12, but when a call is made, the switch 16 is connected to the ground side (logic "0"), so the output of the NAND gate 14 becomes "1". , the transmission data input is output to the subscriber line 3 via the line driver 13 as is.

データ交換機2では加入者線3上の信号をライ
ンレシーバ21で受信し、受信データ出力端子2
2に出力する。送信データ入力の存在しない時、
端子11の信号論理は“1”に保たれる。信号検
知回路23はその端子Tから入力される信号の、
たとえば立上り点を計数するカウンタから構成さ
れ、このカウンタの計数値が所定値以上になると
Dフリツプフロツプ25のD端子に論理“1”の
信号を入力するように構成されている。微分回路
24は送信データのビツトタイミングパルス(第
2図b)に等しい周波数の伝送速度タイミングパ
ルスを入力して、たとえばその立上り点のパルス
で信号検知回路23を構成するカウンタをリセツ
トするが、送信データ信号の立上り点の間隔の方
が、伝送速度タイミングパルスの間隔よりも大き
いので信号検知回路23は常にリセツトされた状
態にある。
In the data exchange 2, the signal on the subscriber line 3 is received by the line receiver 21, and the received data output terminal 2
Output to 2. When there is no transmit data input,
The signal logic of terminal 11 is kept at "1". The signal detection circuit 23 detects the signal input from its terminal T.
For example, it is composed of a counter that counts rising points, and is configured to input a logic "1" signal to the D terminal of the D flip-flop 25 when the counted value of this counter exceeds a predetermined value. The differentiating circuit 24 inputs a transmission speed timing pulse having a frequency equal to the bit timing pulse (FIG. 2b) of the transmission data, and resets the counter constituting the signal detection circuit 23 with the pulse at its rising point, for example. Since the interval between the rising points of the data signal is greater than the interval between the transmission rate timing pulses, the signal detection circuit 23 is always in a reset state.

スイツチ16を+5V側(論理“1”側)に接
続すると、高周波パルス発生器15の出力がナン
ドゲート14を通過し、端子11の信号論理が
“1”である間はアンドゲート12を通過し、ラ
インドライバ13、加入者線3、ラインレシーバ
21を経て端子22に出力されると同時に、信号
検知回路23に入力される。高周波パルスは伝送
速度タイミングパルスより高い周波数を有し、伝
送速度タイミングパルスによつて信号検知回路2
3がリセツトされる間にその出力点の論理が
「1」になる計数が行われるように設計されてい
るのでDフリツプフロツプ25の出力が切断状態
を示す論理になる。スイツチ16をアース側に接
続すると高周波パルスは送出されなくなり、次の
伝送速度タイミングパルスの立上り点で信号検知
回路23がリセツトされDフリツプフロツプ25
の出力は発呼状態を示す論理になる。このよう
に、フリツプフロツプ25の出力により発呼、切
断状態が検出でき、かつビツトタイミングパルス
に等しい周波数の伝送速度タイミングパルスによ
り信号検知回路23をリセツトしているので、従
来のエンベロープ方式のように同期ビツト、及び
制御用ビツトを必要としない伝送が可能になる。
When the switch 16 is connected to the +5V side (logic "1" side), the output of the high frequency pulse generator 15 passes through the NAND gate 14, and while the signal logic at the terminal 11 is "1", it passes through the AND gate 12. The signal is output to the terminal 22 via the line driver 13, the subscriber line 3, and the line receiver 21, and at the same time is input to the signal detection circuit 23. The high frequency pulse has a higher frequency than the transmission speed timing pulse, and the transmission speed timing pulse causes the signal detection circuit 2 to
3 is reset, the output point of the D flip-flop 25 becomes a logic indicating a disconnected state because it is designed so that the logic at its output point becomes "1". When the switch 16 is connected to the ground side, the high frequency pulse is no longer sent out, and the signal detection circuit 23 is reset at the rising point of the next transmission speed timing pulse, and the D flip-flop 25 is reset.
The output of is a logic indicating the calling status. In this way, the call origination and disconnection states can be detected by the output of the flip-flop 25, and the signal detection circuit 23 is reset by the transmission speed timing pulse with the same frequency as the bit timing pulse, so that synchronization is not performed as in the conventional envelope method. Transmission that does not require bits or control bits becomes possible.

Dフリツプフロツプ25のブロツク内の記号S
はセツト入力端子でパルス消滅監視回路26の出
力及び電源リセツト時の信号によりオアゲートを
経てDフリツプフロツプ25を切断状態を表す論
理にセツトして、Dフリツプフロツプ25の初期
化を行う。パルス消滅監視回路26は所定時間の
間送信データの入力も高周波パルスの入力も存在
しないときDフリツプフロツプ25をセツトする
信号を出力する。
Symbol S in the block of D flip-flop 25
At the set input terminal, the D flip-flop 25 is initialized by setting the D flip-flop 25 to the logic representing the disconnected state via an OR gate using the output of the pulse extinction monitoring circuit 26 and a signal at the time of power supply reset. The pulse disappearance monitoring circuit 26 outputs a signal to set the D flip-flop 25 when there is no input of transmission data or high frequency pulse for a predetermined period of time.

なお、上記実施例では、発呼・切断信号がデー
タ端末装置1側からデータ交換機2側に送出され
る場合について説明したが、逆にデータ交換機側
から切断信号が送出される場合についても適用で
きることは明らかである。また、この発明の装置
では加入者線には常時送信データ信号が高周波パ
ルスのいずれかが送出されているのでパルス消滅
監視回路により容易に線路異常をも検出すること
ができる。
In the above embodiment, the case where the call origination/disconnection signal is sent from the data terminal device 1 side to the data exchange 2 side has been described, but it can also be applied to the case where the disconnection signal is sent from the data exchange side. is clear. Further, in the apparatus of the present invention, since either the transmission data signal or the high frequency pulse is constantly sent to the subscriber line, line abnormalities can be easily detected by the pulse extinction monitoring circuit.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、データの伝送
速度より十分に高い繰返し周波数のパルス波を発
呼・切断信号に用いたので、データ速度と伝送速
度間の速度変換が不要であり、また、同期ビツ
ト、制御用ビツトの付加が不要となる効果があ
る。
As described above, according to the present invention, a pulse wave with a repetition frequency sufficiently higher than the data transmission rate is used for the call/disconnection signal, so there is no need for speed conversion between the data rate and the transmission rate. This has the effect of eliminating the need to add synchronization bits and control bits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の方法を示すフオーマツト図、第
2図はこの発明の信号構成を説明するためのタイ
ムチヤート、第3図はこの発明の一実施例を示す
ブロツク図である。 1……データ端末装置、2……データ交換器、
3……加入者線、15……高周波パルス発生器、
16……発呼・切断スイツチ、23……信号検出
回路。尚、各図中同一符号は同一又は相当部分を
示す。
FIG. 1 is a format diagram showing a conventional method, FIG. 2 is a time chart for explaining the signal structure of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. 1...Data terminal device, 2...Data exchanger,
3...Subscriber line, 15...High frequency pulse generator,
16...Call/disconnect switch, 23...Signal detection circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 1 デイジタル符号の形のデータを交換する場合
に、データ端末装置とデータ交換機間で加入者線
を介して発呼・切断信号を伝送するための発呼・
切断信号の伝送装置において、上記データの送信
側に設けられ、データ信号のビツトタイミングパ
ルスよりも高い繰返し周波数の高周波パルス発生
器と、上記送信側に設けられ、切断状態時上記高
周波パルスを受信側へ送出し、発呼信号時上記高
周波パルスの送出を停止する発呼・切断スイツチ
と、上記データの受信側に設けられ、上記ビツト
タイミングパルス周期でリセツトされ、かつ上記
加入者線から入力するパルスを上記ビツトタイミ
ングパルス周期に応じた期間計数し、計数値が所
定値以上のとき出力を発生する信号検知回路と、
この信号検知回路の出力に有無により、発呼状
態、又は切断状態を示す論理出力を発生するフリ
ツプフロツプと、所定時間、上記受信側で上記デ
ータ信号及び上記高周波パルスを受信しないと
き、上記フリツプフロツプを切断状態の論理出力
とするパルス消滅監視回路とを備えたことを特徴
とする発呼・切断信号の伝送装置。
1 Call origination/disconnection signals for transmitting call origination/disconnection signals via subscriber lines between data terminal equipment and data exchange equipment when exchanging data in the form of digital codes.
The disconnect signal transmission device includes a high frequency pulse generator provided on the data transmitting side and having a higher repetition frequency than the bit timing pulse of the data signal, and a high frequency pulse generator provided on the transmitting side that generates the high frequency pulse in the disconnected state. a call originating/disconnecting switch that stops sending out the high frequency pulse when a calling signal is sent to the subscriber line; and a pulse that is provided on the data receiving side and is reset at the bit timing pulse period and is input from the subscriber line. a signal detection circuit that counts the period of time according to the bit timing pulse cycle and generates an output when the counted value is greater than or equal to a predetermined value;
A flip-flop generates a logic output indicating a calling state or a disconnected state depending on the presence or absence of the output of this signal detection circuit, and the flip-flop is disconnected when the receiving side does not receive the data signal and the high frequency pulse for a predetermined period of time. A transmission device for a call/disconnection signal, comprising a pulse extinction monitoring circuit that outputs a logic state.
JP58222648A 1983-11-24 1983-11-24 Transmitter of calling and cutting signals Granted JPS60113552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58222648A JPS60113552A (en) 1983-11-24 1983-11-24 Transmitter of calling and cutting signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58222648A JPS60113552A (en) 1983-11-24 1983-11-24 Transmitter of calling and cutting signals

Publications (2)

Publication Number Publication Date
JPS60113552A JPS60113552A (en) 1985-06-20
JPH0522423B2 true JPH0522423B2 (en) 1993-03-29

Family

ID=16785741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58222648A Granted JPS60113552A (en) 1983-11-24 1983-11-24 Transmitter of calling and cutting signals

Country Status (1)

Country Link
JP (1) JPS60113552A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5732539B2 (en) * 1974-09-20 1982-07-12

Also Published As

Publication number Publication date
JPS60113552A (en) 1985-06-20

Similar Documents

Publication Publication Date Title
JPS5845866B2 (en) Variable speed data transmission method
JPH0228939B2 (en)
US4225752A (en) High speed, low noise digital data communication system
GB1278861A (en) Transmit-receive devices
JP3201666B2 (en) Interface conversion circuit for half-duplex serial transmission
JPH0522423B2 (en)
CA1279729C (en) Method and apparatus for transferring data between two data processing equipments each driven by an independent clock
US4271510A (en) Shift-register transmitter for use in a high speed, low noise digital data communication system
US3516073A (en) Data and control character discrimination scheme for digital computer system
JPS649781B2 (en)
US5003582A (en) Method of adjusting the end of transmission in a modem
US3300578A (en) Data transmission
JP2888004B2 (en) Transmission line interface circuit
SU1159164A1 (en) Serial code-to-parallel code translator
JPS5495105A (en) Data transfer system
US3790699A (en) Simplex radiotelegraph system
US4229621A (en) Transmitting means for use in a high speed, low noise digital data communication system
SU1762307A1 (en) Device for information transfer
US5268931A (en) Data communication system
JPH1168720A (en) Duplex communication system for transmission line
JPS60121850A (en) Transmitter for call and disconnection signal
SU1142898A1 (en) Start-stop transmitting device
CA1189928A (en) Full-duplex transmission of bit streams serially and in bit-synchronism on a bus between two terminals
JPH02306735A (en) Data transmission/reception system
GB1597835A (en) Error detection arrangements for line transmission systems