JPH05226465A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05226465A JPH05226465A JP2981692A JP2981692A JPH05226465A JP H05226465 A JPH05226465 A JP H05226465A JP 2981692 A JP2981692 A JP 2981692A JP 2981692 A JP2981692 A JP 2981692A JP H05226465 A JPH05226465 A JP H05226465A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- isolation
- selective oxidation
- shaped
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 238000002955 isolation Methods 0.000 abstract description 17
- 230000003647 oxidation Effects 0.000 abstract description 11
- 238000007254 oxidation reaction Methods 0.000 abstract description 11
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 238000005452 bending Methods 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の関し、特に
超高速デジタル回路用のバイポーラトランジスタの素子
間分離に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to element isolation of bipolar transistors for ultra high speed digital circuits.
【０００２】[0002]
【従来の技術】近年、超高速動作するバイポーラトラン
ジスタを用いたＥＣＬ回路と、超高密度または低消費電
力のＣＭＯＳ回路、特にメモリ回路とが同一チップに形
成された半導体集積回路の開発が進められている。2. Description of the Related Art In recent years, development of a semiconductor integrated circuit in which an ECL circuit using a bipolar transistor operating at an extremely high speed and a CMOS circuit having an extremely high density or low power consumption, particularly a memory circuit, are formed on the same chip has been advanced. ing.
【０００３】一般にＣＭＯＳ部には従来のＬＯＣＯＳ選
択酸化法による素子間分離（絶縁分離）を用い、バイポ
ーラ部にはトレンチアイソレーションおよびＬＯＣＯＳ
選択酸化法を併用した素子間分離が用いられている。Generally, element isolation (insulation isolation) by a conventional LOCOS selective oxidation method is used for the CMOS portion, and trench isolation and LOCOS are used for the bipolar portion.
Isolation between elements using a selective oxidation method is used.
【０００４】つぎに従来のトレンチアイソレーションお
よびＬＯＣＯＳ選択酸化法を併用した素子間分離につい
て、図３（ａ）〜（ｃ）を参照して説明する。Next, element isolation using conventional trench isolation and LOCOS selective oxidation will be described with reference to FIGS. 3 (a) to 3 (c).
【０００５】はじめに図３（ａ）に示すように、Ｎ+ 型
埋込層２およびＮ- 型エピタキシャル層３が形成された
Ｐ型シリコン基板１に窒化シリコン膜（図示せず）をマ
スクとしてエッチングを行なってトレンチ（溝）を形成
する。つぎにトレンチ内壁に酸化シリコン膜４を形成し
てからポリシリコン５を堆積したのち、エッチバックし
てＮ- 型エピタキシャル層３表面を露出させる。First, as shown in FIG. 3A, a P-type silicon substrate 1 on which an N + type buried layer 2 and an N − type epitaxial layer 3 are formed is etched using a silicon nitride film (not shown) as a mask. Is performed to form a trench. Next, a silicon oxide film 4 is formed on the inner wall of the trench and then polysilicon 5 is deposited and then etched back to expose the surface of the N − type epitaxial layer 3.
【０００６】つぎに図３（ｂ）に示すように、熱酸化に
よりＮ- 型エピタキシャル層３表面に厚さ３０〜５０ｎ
ｍの酸化シリコン膜（図示せず）を形成したのち、厚さ
５０〜１００ｎｍのポリシリコン６を成長してから厚さ
２００〜３００ｎｍの窒化シリコン膜７を成長する。つ
ぎにトレンチ近傍の窒化シリコン膜７を除去する。Next, as shown in FIG. 3B, a thickness of 30 to 50 n is formed on the surface of the N − type epitaxial layer 3 by thermal oxidation.
m silicon oxide film (not shown) is formed, a polysilicon 6 having a thickness of 50 to 100 nm is grown, and then a silicon nitride film 7 having a thickness of 200 to 300 nm is grown. Next, the silicon nitride film 7 near the trench is removed.
【０００７】つぎに図３（ｃ）に示すように、窒化シリ
コン膜７開口のポリシリコン５，６およびＮ- 型エピタ
キシャル層３表面を熱酸化して、厚さ８００ｎｍのフィ
ールド酸化膜８を形成して素子間分離が完成する。Next, as shown in FIG. 3C, the surfaces of the polysilicon 5 and 6 in the opening of the silicon nitride film 7 and the surface of the N − type epitaxial layer 3 are thermally oxidized to form a field oxide film 8 having a thickness of 800 nm. Then, isolation between elements is completed.
【０００８】このとき図２（ａ）および（ｂ）の平面図
に示すように、トレンチ９はトランジスタ１０を囲むと
ともに、Ｌ字型のコーナーをもっている。At this time, as shown in the plan views of FIGS. 2A and 2B, the trench 9 surrounds the transistor 10 and has an L-shaped corner.
【０００９】[0009]
【発明が解決しようとする課題】従来の半導体装置で
は、トレンチからフィールド酸化膜が１．５μｍ以上張
り出している場合は問題なかった。ところが素子寸法の
縮小とともに、張り出しが１０μｍ以下になると、フィ
ールド酸化膜端部の応力と、トレンチ内壁の酸化シリコ
ン膜のＮ- 型エピタキシャル層表面近傍の応力とが相乗
的に作用する。そのため転位などの結晶欠陥を発生さ
せ、基板リーク電流の増加、耐圧不良、ショートなどに
より歩留りが大幅に低下する。In the conventional semiconductor device, there was no problem when the field oxide film overhangs the trench by 1.5 μm or more. However, when the overhang becomes 10 μm or less as the element size decreases, the stress at the end of the field oxide film and the stress near the surface of the N − type epitaxial layer of the silicon oxide film on the inner wall of the trench act synergistically. Therefore, crystal defects such as dislocations are generated, and the yield is significantly reduced due to an increase in substrate leak current, a poor breakdown voltage, a short circuit, and the like.
【００１０】特にトレンチがＬ字型に折れ曲るコーナー
の外周の角度は図２（ａ）に示すように約２７０°と大
きい。表面近傍のトレンチ内壁の酸化シリコン膜の応力
が大きく、図４に示すようにトレンチ９のコーナーの外
側で多くの結晶欠陥１１が発生している。In particular, the angle of the outer circumference of the corner at which the trench is bent into an L-shape is large, as shown in FIG. The stress of the silicon oxide film on the inner wall of the trench near the surface is large, and many crystal defects 11 are generated outside the corner of the trench 9 as shown in FIG.
【００１１】このトレンチの折れ曲りを緩やかにするに
は、トランジスタの面積を拡大しなければならないう
え、トランジスタ特性が低下する。In order to moderate the bending of the trench, the area of the transistor must be increased and the transistor characteristics are deteriorated.
【００１２】[0012]
【課題を解決するための手段】本発明の半導体装置は、
直線、丁字および十字の組み合わせからなる平面パター
ンのトレンチが形成されたものである。The semiconductor device of the present invention comprises:
A trench having a plane pattern composed of a combination of straight lines, T-shapes and crosses is formed.
【００１３】さらにトレンチの丁字または十字の平面パ
ターンの交差部から末端までの距離は、前記トレンチの
幅と同等以上となっている。Furthermore, the distance from the intersection of the T-shaped or cross-shaped plane pattern of the trench to the end is equal to or greater than the width of the trench.
【００１４】[0014]
【実施例】本発明の一実施例について、図１（ａ）〜
（ｅ）を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to (e).
【００１５】はじめに図１（ａ）では、孤立したトラン
ジスタ１０を囲んで丁字型のトレンチ９を形成する。図
１（ｃ）では十字型のトレンチ９を形成する。First, in FIG. 1A, a T-shaped trench 9 is formed surrounding an isolated transistor 10. In FIG. 1C, the cross-shaped trench 9 is formed.
【００１６】このとき丁字型または十字型の交差部から
末端までの距離は、トレンチ９の幅と同等以上になって
いる。At this time, the distance from the T-shaped or cross-shaped intersection to the end is equal to or more than the width of the trench 9.
【００１７】つぎに直線上に複数個のトンランジスタを
並べるときは、図１（ｄ）に示すように、隣り合ったト
レンチ９を連結させて丁字型のコーナーを形成する。こ
の連結されたトランジスタ１０の配列においても、トレ
ンチ９の末端を丁字型に形成している。Next, when arranging a plurality of tunnel transistors on a straight line, adjacent trenches 9 are connected to form a letter-shaped corner, as shown in FIG. 1 (d). Also in the array of the connected transistors 10, the end of the trench 9 is formed in a T-shape.
【００１８】図１（ｄ）の丁字型の代りに図１（ｅ）で
は、トレンチ９の総てのコーナーを十字型に形成してい
る。In FIG. 1 (e), all the corners of the trench 9 are formed in a cross shape instead of the T-shape of FIG. 1 (d).
【００１９】さらに図１（ｃ）では、４個のトランジス
タ１０が隣接するトレンチ９を共有しながら、トレンチ
９の末端を総て十字型に形成している。Further, in FIG. 1C, the four transistors 10 share the adjacent trenches 9, and all the ends of the trenches 9 are formed in a cross shape.
【００２０】以上に述べたように、トレンチがＬ字型に
折れ曲る個所で局所的に延長して総て丁字型または十字
型に改造することができる。その結果、転位などの結晶
欠陥を解消することができた。As described above, the trenches can be locally extended at the bent portions to form a T-shape or a cross shape. As a result, crystal defects such as dislocations could be eliminated.
【００２１】[0021]
【発明の効果】トレンチがＬ字型に折れ曲るコーナーを
延長して、丁字型または十字型に改造する。そうしてト
レンチの折れ曲りの角度を１８０°以下にすることによ
り、ＬＯＣＯＳ選択酸化のときトレンチのコーナーで発
生する応力を低減することができた。トランジスタの面
積を拡大したり、特性を低下させることなく、従来の結
晶欠陥に起因する歩留り低下の問題を解決することがで
きた。EFFECTS OF THE INVENTION The corner at which the trench is bent into an L shape is extended to be modified into a letter shape or a cross shape. By setting the bending angle of the trench to 180 ° or less, the stress generated at the corner of the trench during the LOCOS selective oxidation could be reduced. It has been possible to solve the conventional problem of reduced yield due to crystal defects without increasing the area of the transistor or deteriorating the characteristics.
【図１】本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.
【図２】従来のトレンチアイソレーションおよびＬＯＣ
ＯＳ選択酸化法を併用した素子間分離を示す平面図であ
る。FIG. 2 Conventional trench isolation and LOC
It is a top view which shows the isolation between elements which used the OS selective oxidation method together.
【図３】トレンチアイソレーションおよびＬＯＣＯＳ選
択酸化法を併用した素子間分離を工程順に示す断面図で
ある。FIG. 3 is a cross-sectional view showing, in the order of steps, element isolation using both trench isolation and LOCOS selective oxidation.
【図４】従来のトレンチアイソレーションおよびＬＯＣ
ＯＳ選択酸化法を併用した素子間分離の問題点を示す平
面図である。FIG. 4 Conventional trench isolation and LOC
FIG. 6 is a plan view showing a problem of element isolation using an OS selective oxidation method together.
１ Ｐ型シリコン基板 ２ Ｎ+ 型埋込層 ３ Ｎ- 型エピタキシャル層 ４ 酸化シリコン膜 ５，６ ポリシリコン ７ 窒化シリコン膜 ８ フィールド酸化膜 ９ トレンチ １０ トランジスタ １１ 結晶欠陥1 P-type silicon substrate 2 N + -type buried layer 3 N - -type epitaxial layer 4 of silicon oxide film 5, 6 polysilicon 7 silicon nitride film 8 field oxide film 9 trench 10 transistor 11 crystal defects
Claims (2)
なる平面パターンのトレンチが形成された半導体装置。1. A semiconductor device in which a trench having a plane pattern composed of a combination of straight lines, characters and crosses is formed.
ンの交差部から末端部までの距離が、前記トレンチの幅
と同等以上である請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the distance from the intersection of the T-shaped or cross-shaped plane patterns of the trench to the end is equal to or greater than the width of the trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4029816A JP2833323B2 (en) | 1992-02-18 | 1992-02-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4029816A JP2833323B2 (en) | 1992-02-18 | 1992-02-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05226465A true JPH05226465A (en) | 1993-09-03 |
| JP2833323B2 JP2833323B2 (en) | 1998-12-09 |
Family
ID=12286549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4029816A Expired - Lifetime JP2833323B2 (en) | 1992-02-18 | 1992-02-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2833323B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5854112A (en) * | 1993-03-30 | 1998-12-29 | Siemens Aktiengesellschaft | Transistor isolation process |
| US6777772B1 (en) * | 1998-05-22 | 2004-08-17 | Renesas Technology Corp. | Semiconductor device having improved trench structure |
| JP2009516364A (en) * | 2005-11-14 | 2009-04-16 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Rotational shear stress for charge carrier mobility correction |
| JP2021044433A (en) * | 2019-09-12 | 2021-03-18 | キオクシア株式会社 | Semiconductor storage device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62171139A (en) * | 1986-01-24 | 1987-07-28 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1992
- 1992-02-18 JP JP4029816A patent/JP2833323B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62171139A (en) * | 1986-01-24 | 1987-07-28 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5854112A (en) * | 1993-03-30 | 1998-12-29 | Siemens Aktiengesellschaft | Transistor isolation process |
| US6777772B1 (en) * | 1998-05-22 | 2004-08-17 | Renesas Technology Corp. | Semiconductor device having improved trench structure |
| JP2009516364A (en) * | 2005-11-14 | 2009-04-16 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Rotational shear stress for charge carrier mobility correction |
| JP2021044433A (en) * | 2019-09-12 | 2021-03-18 | キオクシア株式会社 | Semiconductor storage device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2833323B2 (en) | 1998-12-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980901 |