JPH05235331A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide the manufacturing, method in which a contact hole can be formed to the bottom of an oxide-film opening section for diffusing impurities with excellent dimensional accuracy even when the thickness of an oxide film is thickened for realizing high breakdown strength and high reliability. CONSTITUTION:A contact hole 7 is formed to the bottom of an oxide-film recessed section 4' shaped for diffusing impurities in the manufacture of a semiconductor device, a silicon nitride film 6a is deposited on the whole surface of an oxide film 2 including the oxide-film recessed section 4', and etched in an anisotropic manner so as to leave the silicon nitride film 6a only on the sidewalls of the oxide-film recessed section 4'. The oxide film 2 is etched in the anisotropic manner so that one conductivity type semiconductor region 5 is exposed to the bottom of the oxide-film recessed section 4' to bore a recessed-section oxide film 2a, and the silicon nitride films 6a on the sidewalls of the oxide-film recessed section are removed, thus forming a stepped contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact hole in an oxide film having a step.

[0002]

2. Description of the Related Art One of semiconductor devices is a static induction type semiconductor device. FIG. 4 is a cross-sectional view of a main part of such an electrostatic induction semiconductor device. In the electrostatic induction semiconductor device 31, a gate (P ⁺ ) region 33 and a cathode (N ⁺ ) region 34 are provided on one surface side of a semiconductor substrate 32. And an anode (P ⁺ ) region 35 on the other surface, and a high specific resistance (N ⁻ ) region 36 serving as a main current path between the gate / cathode regions 33 and 34 and the anode region 35. ing.

In the electrostatic induction type semiconductor device 31, the anode electrode 35 'and the cathode electrode 34' are controlled by controlling the voltage between the gate electrode 33 'and the cathode electrode 34'.
The main current between the two can be turned on and off. In recent years, the turning on and off speed (switching speed) has been greatly improved by structural improvement, electron beam and proton beam irradiation, and has attracted attention as a next-generation high-power semiconductor device. ing.

By the way, the gate region 33 of such an electrostatic induction type semiconductor device exists as far as the inside of the semiconductor substrate 32 as compared with the cathode region 34 (the diffusion length of the gate region 33 is deeper). Therefore, the gate region 33 and the cathode region 34 are generally formed in this order in manufacturing.

To form the gate region, as shown in FIG. 5A, after a resist 48 is applied to the oxide film 47 formed on the one surface side of the semiconductor substrate 42 to form a desired resist pattern. As shown in FIG. 5B, the oxide film 47 is etched using the resist 48 as a mask to expose the surface 49 of the semiconductor substrate 42.

Then, after removing the resist 48,
A P-type impurity is introduced and diffused through the diffusion oxide film opening (semiconductor substrate exposed portion 49) 50 to form a gate region 43 as shown in FIG. 5C. Since the cathode region is formed thereafter, the semiconductor substrate exposed portion 49 is covered with the oxide film 47 'during the impurity diffusion.

After forming the cathode region, a contact hole for connecting to the gate electrode must be finally formed in the gate region 43, and as shown in FIG.
The resist 48 'is applied again to form a desired contact hole resist pattern inside the diffusion oxide film opening 50. Then, the oxide films 47 and 47 'are etched by using the contact hole resist pattern as a mask.

Finally, after removing the resist 48 ', the contact hole shown in FIG. 6 can be formed.

Here, the contact hole resist pattern 48 'is formed inside the diffusion oxide film opening 50. The opening size is set in consideration of mask alignment accuracy. It is designed to be smaller than 50. Further, as shown in FIG. 6, by having a stepwise oxide film cross section S in the final cross-sectional structure, it is possible at the same time to realize good coverage of the electrode material when the electrode material is deposited thereafter. There is.

[0010]

However, in the above-mentioned conventional technique, there is a problem that the contact hole resist cannot be opened (processed) more accurately than the mask size when the oxide film becomes thicker. there were.

That is, recently, there has been a demand for higher power and higher breakdown voltage of the semiconductor device, and the electrostatic induction type semiconductor device is no exception. Therefore, especially aiming at high breakdown voltage, and
In order to improve the reliability of the device, a method of increasing the oxide film thickness is adopted. However, when the oxide film is thickened, no problem occurs in opening the oxide film for impurity diffusion, but as shown in FIG. 7, the contact hole forming resist 58 is formed in the oxide film opening 60 for impurity diffusion. If the oxide film 57 is thick when the resist is reapplied, the resist 58 inside the opening 60 also becomes thick, and the amount of resist 58 ′ to be removed for forming the contact hole increases.
Therefore, compared with processing the resist applied on the flat surface 61, both the exposure amount and the development time required for the processing (opening) are increased, and according to the increase rate of the exposure amount and the development time, The accuracy of the opening size after the resist opening with respect to the mask size is deteriorated, the resist cannot be processed within the target size, and in the worst case, the size exceeds the diffusion oxide film opening 60 size as shown in FIG. There was a problem.

The present invention has been made in view of the above problems, and an object of the present invention is to form an oxide film opening for impurity diffusion even if the oxide film is thickened to realize high breakdown voltage and high reliability. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a contact hole can be formed with high dimensional accuracy at the bottom of the portion.

[0013]

In order to solve the above-mentioned problems, the present invention is directed to the manufacture of a semiconductor device in which a contact hole is formed at the bottom of an oxide film recess formed for impurity diffusion. And then anisotropically etching so that the silicon nitride film is left only on the sidewalls of the oxide film recess, and subsequently, a semiconductor region of one conductivity type is exposed at the bottom of the oxide film recess. Is characterized in that the oxide film is anisotropically etched to open the recess oxide film, and thereafter, the stepwise contact hole is formed by removing the silicon nitride film on the sidewall of the oxide film recess. is there.

[0014]

1 and 2 are process sectional views showing an embodiment of the present invention, which will be described by taking an electrostatic induction type semiconductor device as an example of a semiconductor device.

First, in order to form a gate region of an electrostatic induction type semiconductor device, as shown in FIG. 1A, a resist 3 is applied to an oxide film 2 formed on one surface of a semiconductor substrate 1. The resist 3 is opened in the impurity diffusion pattern.

Next, as shown in FIG. 1B, the oxide film 2 is anisotropically etched using the resist 3 as a mask to expose the surface 1a of the semiconductor substrate 1, and impurity diffusion which becomes an oxide film concave portion in a later step is performed. The opening 4 is formed. At this time, even if the thickness of the oxide film 2 is increased, the etching time is lengthened and there is no processing problem.

Next, after removing the resist 3, a P-type impurity is introduced through the diffusion opening (exposed semiconductor substrate surface 1a) 4 and diffused to a desired depth, as shown in FIG. 1 (c). A gate region 5 is formed in the. Here, the semiconductor substrate surface 1a is covered with an oxide film 2a in consideration of forming a cathode region later, and the diffusion opening 4 becomes an oxide film recess 4 '.

After this, a cathode region is formed by the same method, but finally the gate region 5 must be connected to the electrode material. Therefore, after the cathode region is formed, contact holes for connecting the diffusion layer and the electrode material must be formed in both the gate region and the cathode region.

Next, the case of forming a contact hole in the gate region 5 will be described. As shown in FIG. 1D, after forming a gate region 5 and a cathode region (not shown), a silicon nitride film 6 is deposited on the entire surface of the surface oxide film 2, and the silicon nitride film 6 is anisotropically formed. Etching, Figure 2
As shown in (a), the silicon nitride film 6a is left only on the side wall of the oxide film recess 4'formed previously for impurity diffusion.

Next, as shown in FIG. 2B, the surface oxide films 2 and 2a are anisotropically etched while leaving the silicon nitride film 6a on the sidewalls of the oxide film recess 4 ', and the recess oxide film 2a is formed.
To expose the underlying semiconductor substrate surface 1a (gate region 5). That is, the silicon nitride film 6a remaining on the side wall of the oxide film recess 4 'serves as a mask material to etch the recess oxide film 2a. Of course, the oxide film 2 is also the recess oxide film 2
Although it is etched by the thickness of a, the thickness may be increased in the initial step in anticipation of it.

Finally, if the silicon nitride film 6a is removed, as shown in FIG. 2 (c), 7 contact holes can be formed from the side wall of the oxide film recess 4'to the inside with a dimension determined by the thickness of the silicon nitride film 6a. After that, the electrode material may be deposited in the contact hole and processed.

As described above, when the contact hole 7 is formed at the bottom of the oxide film recess 4 ', no resist is used as in the prior art, so that mask alignment is unnecessary and
Even if the oxide film 2 is thickened, a contact hole having a staircase shape that can improve the coverage of the electrode material can be formed as usual without deteriorating the processing dimensional accuracy. Needless to say, even if the oxide film 2 is thin, it can be formed by the same method as described above. Further, in the cathode region, a contact hole may be formed at the same time as in the gate region.

In the above embodiment, the contact hole forming portion is on the same plane as the surface of the semiconductor substrate, but the present invention is not limited to this.
As shown in FIG. 3, the present invention can also be applied to the case where a contact hole is formed at the bottom of a trench-shaped oxide film recess 4'formed by etching the semiconductor substrate 1. That is, the present invention is effective in forming a contact hole at the bottom of an oxide film recess existing on the surface of or inside a semiconductor substrate.

[0024]

As described above, according to the present invention, when the contact hole is formed at the bottom of the recess of the oxide film formed for impurity diffusion, the oxide film is etched using the silicon nitride film on the sidewall of the recess as a mask. Even if the oxide film is thickened to achieve high breakdown voltage and high reliability, the dimensional accuracy of processing the contact hole is not deteriorated. Further, since the contact hole can be formed in a stepped shape, the coverage of the electrode material can be improved as in the conventional case.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an embodiment of the present invention.

FIG. 2 is a process sectional view showing an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step of another embodiment of the present invention.

FIG. 4 is a cross-sectional view of a main part of a static induction semiconductor device according to a conventional example.

FIG. 5 is a process sectional view showing a conventional example.

FIG. 6 is a process sectional view showing a conventional example.

FIG. 7 is a process sectional view showing a different conventional example.

FIG. 8 is a process sectional view showing a different conventional example.

[Explanation of symbols]

 1 Semiconductor Substrate 1a Semiconductor Substrate Surface 2 Oxide Film 2a Recess Oxide Film 3 Resist 4 Impurity Diffusion Opening 4'Oxide Film Recess 5 Gate Area 6 Silicon Nitride Film 6a Silicon Nitride Film 7 Contact Hole

Claims (1)

[Claims] 1. In the manufacture of a semiconductor device in which a contact hole is formed at the bottom of an oxide film recess formed for impurity diffusion, a silicon nitride film is deposited on the entire surface including the oxide film recess, and then the oxide film recess is formed. Anisotropic etching is performed so as to leave the silicon nitride film only on the sidewalls, and then the oxide film is anisotropically etched until a semiconductor region of one conductivity type is exposed at the bottom of the oxide film recess, thereby forming a recess oxide film. Open the
After that, a step-like contact hole is formed by removing the silicon nitride film on the sidewall of the oxide film recess, and a method for manufacturing a semiconductor device.