JPH0523548B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a photoelectric conversion device, and in particular, a control electrode region made of a semiconductor of a first conductivity type and a second conductivity type different from the first conductivity type. first and second main electrode regions made of a semiconductor, and a plurality of transistors capable of accumulating carriers generated by receiving light energy in the control electrode region; and the first main electrode region. a first switch for selectively holding the transistor at a reference potential, and a second switch for selectively connecting the first main electrode region and a capacitive element for reading a signal from the transistor. The present invention relates to a photoelectric conversion device that includes: and performs an accumulation operation, a readout operation, and a refresh operation.

The present invention is applied to photoelectric conversion devices such as broadcast televisions and general video cameras.

[Prior art and its problems]

In recent years, research on photoelectric conversion devices, particularly solid-state imaging devices, has been actively conducted along with the progress of semiconductor technology, and some are beginning to be put into practical use.

These solid-state imaging devices can be broadly classified into
It is classified into two types: CCD type and MOS type. A CCD type imaging device forms a potential well under a MOS capacitor electrode, stores charges generated by incident light in this well, and during readout, these potential wells are sequentially moved by pulses applied to the electrode. The principle is that the accumulated charge is transferred to the output amplifier section and read out. Also
Some CCD imaging devices use a pn junction diode structure for the light receiving section and a CCD structure for the transfer section. On the other hand, in a MOS type imaging device, charges generated by incident light are accumulated in each photodiode made of a pn junction that constitutes the light receiving section, and when reading out, the MOS switching transistor connected to each photodiode is activated. It uses the principle that the accumulated charge is read out to the output amplifier section by sequentially turning on the transistors.

CCD type imaging device has a relatively simple structure,
In addition, considering the noise that can be generated, only the capacitance value of the charge detector consisting of the floating diffusion in the final stage contributes to random noise, so it is a relatively low-noise imaging device and is capable of low-light photography. be. However, due to process constraints in manufacturing CCD type imaging devices, MOS is used as the output amplifier.
Since the type amplifier is on-chip, 1/f noise, which is easily noticeable on images, is generated from the interface between silicon and SiO ₂ film. Therefore, although it is said to have low noise, there are limits to its performance. In addition, if the number of cells is increased to achieve higher density in order to achieve higher resolution, the area of one cell will become smaller and the maximum amount of charge that can be stored in one potential well will decrease, making it impossible to maintain a dynamic range. This will become a major problem as solid-state imaging devices become higher resolution in the future. Furthermore, since a CCD-type imaging device transfers accumulated charge by sequentially moving the potential wells, even if there is a defect in one of the cells, the charge transfer may stop there, or the charge may be lost. It also has the disadvantage that the quantity decreases and the manufacturing yield does not increase.

On the other hand, MOS type imaging devices are structurally
Although it is a little more complicated than a CCD type imaging device, especially a frame transfer type device, it has the advantage of being able to be configured to have a large storage capacity and having a wide dynamic range. Furthermore, even if one of the cells has a defect, because of the X-Y addressing method, the defect does not affect other cells, which is advantageous in terms of manufacturing yield. However, this
In MOS type imaging device, MOS transistor and
Since there is a large stray capacitance between the MOS amplifier and the MOS amplifier, an extremely large signal voltage drop occurs during readout, resulting in a drop in the output voltage.The wiring capacitance is large, which causes a large amount of random noise. In addition, fixed pattern noise is introduced due to variations in the parasitic capacitance of each photodiode and horizontal scanning MOS switching transistor, and it has disadvantages such as difficulty in low-light photography compared to CCD type imaging devices. There is.

Furthermore, in the future, as the resolution of imaging devices increases, the size of each cell will be reduced and the amount of accumulated charge will decrease. On the other hand, the wiring capacitance, which is determined by the chip size, does not decrease much even if the line width is made thinner. For this reason, the MOS type imaging device becomes increasingly disadvantageous in terms of S/N.

Although CCD type and MOS type imaging devices have the above-mentioned advantages and disadvantages, they are gradually approaching the level of practical use. However, it can be said that there are essentially major problems in promoting the higher resolution that will be required in the future.

Regarding those solid-state imaging devices,
A new method is proposed in JP-A No. 150878 "Semiconductor Imaging Device", JP-A-56-157073 "Semiconductor Imaging Device", and JP-A-56-165473 "Semiconductor Imaging Device". CCD type,
A MOS imaging device transfers the charge generated by incident light to the main electrode (for example, the source of a MOS transistor).
In contrast, the method proposed here stores the charge generated by incident light on the control electrode (e.g., the base of a bipolar transistor, the SIT
It is based on a new concept of controlling the flowing current using the charges accumulated in the gate of a (static induction transistor) or MOS transistor and generated by light. That is,
While the CCD type and MOS type read out the accumulated charge itself to the outside by light incidence, the method proposed here uses the amplification function of each cell to amplify the charge and then read out the accumulated charge. If you look at it from another perspective, it is read out as a low impedance output by impedance conversion. Therefore, the method proposed here has high output, wide dynamic range, and low noise, and because the carriers (charges) excited by the optical signal accumulate on the control electrode, non-destructive readout is possible. It has several advantages such as: Furthermore, it can be said that this method has the potential for higher resolution in the future.

FIG. 6 is a circuit diagram of a conventional photoelectric conversion device in which a plurality of photosensor cells of the type described above are stored in a control electrode are arranged.

In the figure, the optical sensor cells 101 are arranged in a line, and each output terminal is connected to a common output line 20 via MOS transistors 5 ₁ to 5 _o . The common output line 20 is connected to the output amplifier 2
1 to the output terminal 22, and
MOS transistor 24 for line refresh
is grounded through. Further, each gate electrode of the MOS transistors 5 ₁ to 5 _o is connected to the logic circuit 1
9 are connected to terminals 7 ₁ to 7 _o , respectively.

In such a conventional photoelectric conversion device, the optical information signal of each optical sensor cell 101 is serially read out via the common output line 20 and the output amplifier 20 by sequentially turning on the MOS transistors 5 ₁ to 5 _o . be done.

However, the time required for a read operation of a certain photosensor cell 101 is proportional to the stray capacitance that the common output line 20 has. Therefore, as the number n of optical sensor cells 101 increases, the overall time required for continuous output increases rapidly.

As described above, conventional devices have had the problem that if the number n of optical sensor cells is increased in an attempt to achieve high resolution, high-speed readout operations become difficult.

Furthermore, as described above, the optical sensor cell 101
Since this is a method in which charges due to photoexcitation are accumulated in the control electrode, it is necessary to refresh the accumulated charges after reading is completed.

Conventionally, this refresh operation was performed at once after the readout operation of all the optical sensor cells 101 was completed, so especially when the optical sensor cells 101 are arranged in a two-dimensional array, the readout operation of the optical sensor cells 101 was performed after the collective refresh operation was completed. The time required to start operation differs depending on each optical sensor cell 101, which is inconvenient for achieving high-speed operation and uniformizing photoelectric conversion characteristics.

[Summary of the invention]

A photoelectric conversion device according to the present invention is intended to solve the above conventional problems, and includes a control electrode region made of a semiconductor of a first conductivity type and a semiconductor of a second conductivity type different from the first conductivity type. a plurality of transistors having first and second main electrode regions, each having a plurality of transistors capable of accumulating carriers generated by receiving light energy in the control electrode region; a first switch for maintaining the reference potential at a reference potential, and a second switch for selectively connecting the first main electrode region and a capacitive element for reading a signal from the transistor. In a photoelectric conversion device that performs an accumulation operation, a readout operation, and a refresh operation, the second main electrode region is biased in a direction opposite to the control electrode region during the accumulation operation, the readout operation, and the refresh operation. scanning means for sequentially scanning the signals read out to the capacitor; and during the refresh operation, operating the first switch and the second switch to separate the first main electrode region from the first main electrode region; means for holding the capacitive element at the reference potential and biasing the junction between the control electrode region and the first main electrode region in a forward direction to reset the potential of the control electrode region and the capacitive element; It is characterized by having the following.

[Effect]

With this configuration, a high-speed readout operation can be achieved, and even when the optical sensor cells are arranged in a two-dimensional manner, the storage time of all the optical sensor cells can be made uniform.

Further, at the same time as resetting the potential of the capacitive element, the first main electrode region is set to the reference potential, and a forward bias is applied between the control electrode region and the first main electrode region, so that carriers accumulated in the control electrode region are removed. Disappear.
At this time, the second main electrode region is held at a reverse bias potential and the potential of the control electrode region is reset, making it difficult for noise caused by junction capacitance to occur.
The reset operation is also simplified.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view of a photosensor cell constituting a photoelectric conversion device according to the present invention, and FIG. 2 is an equivalent circuit of the photosensor cell. In addition, in the following, parts that are common to each part will be given the same number.

In FIG. 1, it is usually formed of a PSG film or the like on a silicon substrate 12 doped with impurities such as phosphorus (P), antimony (Sb), and arsenic (As) to make it n-type or n ⁺ type. Passivation film 1
3; Insulating oxide film 3 made of silicon oxide film (SiO ₂ ); Made of an insulating film made of SiO ₂ or Si ₃ N ₄ or a polysilicon film, etc. for electrically insulating between adjacent photosensor cells. element isolation region 4 formed by epitaxial technology; low impurity concentration n ^- region 5 formed by epitaxial technology; bipolar transistor doped with impurity such as boron (B) using impurity diffusion technology or ion implantation technology. p region 6, which becomes the base; n ⁺ region, which becomes the emitter of a bipolar transistor formed by impurity diffusion technology, ion implantation technology, etc.
Region 7; Wiring 8 made of a conductive material such as aluminum (Al), Al-Si, Al-Cu-Si, etc. for reading out signals to the outside; P region in a floating state through the insulating film 3; an electrode 9 for applying a pulse to the substrate 12; an n ⁺ region 10 with a high impurity concentration formed by impurity diffusion technology to establish an ohmic contact with the back surface of the substrate 12; an electrode 9 for applying a pulse to the substrate 12; An electrode 11 made of a conductive material such as aluminum for applying a collector potential.

The capacitor 2 in the equivalent circuit shown in FIG. n ⁺ region 7 as the base (becomes the control electrode region), p region 6 as the base (becomes the control electrode region), n ⁻ region 5 with low impurity concentration, and n or n ⁺ as the collector (becomes the second main electrode region). It is composed of each part of the area 12. As is clear from these drawings, p region 6 is made into a floating region.

The basic operation of the optical sensor cell will be explained below with reference to FIGS. 1 and 2.

The basic operation of this photosensor cell consists of a charge accumulation operation by light incidence, a readout operation, and a refresh operation. In the charge storage operation, for example, the emitter is grounded through the wiring 8, and the collector is biased to a positive potential through the electrode 11. In addition, the base is equipped with capacitor 2 in advance.
It is assumed that a positive pulse voltage V _RF is applied through the electrode 9 in a refresh operation to bring the emitter 7 to a negative potential, that is, to a reverse bias state.

As will be explained in detail later, due to the positive pulse voltage V _RF applied through the electrode 9 during the refresh operation, the potential of the p region 6, which is the base, becomes -aV _RF
It is set to a negative potential expressed by . However, a is a constant determined by the capacitance division between the capacitance of the capacitor 2 and the base-collector and base-emitter capacitances.

In this state, when light 14 enters from the front side of the photosensor cell as shown in FIG. 1, electron-hole pairs are generated within the semiconductor.
Of these, electrons flow toward the n-region 12 side because the n-region 12 is biased to a positive potential, but holes are rapidly accumulated in the p-region 6. Due to the accumulation of holes in the p region, the potential of the p region 6 gradually changes toward a positive potential.

If the amount of change in the base potential is ΔV _B , the base potential will be −aV _RF + when the storage operation is completed.
ΔV _B.

In the read operation state, the emitter and wiring 8 are kept in a floating state, and the collector is held at a positive potential V _CC . In this state, when a positive read voltage V _RE is applied to the electrode 9, the base potential becomes a(V _RE −V _RF )+ΔV _B. In this way, when the base potential is biased in the positive direction with respect to the emitter potential, electrons are injected from the emitter to the base, and since the collector potential is positive, they are accelerated by the drift electric field and are transferred to the collector. reach. Although some of the charge accumulated in the base region 6 is lost as a base current, the value is 1/hfe of the collector current, which is a very small value, and the attenuation of the charge in the base region can be almost ignored.

When the positive voltage V _RE applied to the electrode 9 is returned to zero volts, a voltage of -a·V _RE is added to the base potential, contrary to when it was applied, so the base potential becomes equal to the positive voltage V _RE Return to the state before applying −aV _RF +ΔV _B.

Next, the operation of refreshing the charges accumulated in p region 6 will be explained.

In the optical sensor cell having the above configuration, as already mentioned, the charges accumulated in the p region 6 are not eliminated by the read operation. Therefore, in order to input new optical information, a refresh operation is required to eliminate the previously accumulated charges. At the same time, it is necessary to charge the potential of p region 6, which is in a floating state, to a predetermined negative voltage.

In the optical sensor cell having the above configuration, the refresh operation is also performed by applying a positive voltage to the electrode 9, similarly to the read operation. At this time, the emitter is grounded through the wiring 8. The collector is the electrode 11
Keep it at a positive potential through.

When a positive voltage V _RF is applied to the electrode 9 in this state, a voltage aV _RF is instantaneously applied to the base electrode as in the previous read operation. This voltage biases the base and emitter in the forward direction and makes them conductive, current begins to flow, and the base potential gradually decreases.

Then, as the pulse of the positive voltage V _RF falls, the base potential is set to the predetermined negative potential −aV _RF as described above, and the above operations are repeated.

Next, a first example of a photoelectric conversion device according to the present invention using the above-mentioned optical sensor cell will be described.

In FIG. 3, 1 ₁ to 1 _o are photoelectric conversion transistors, and 2 ₁ to 2 _o are capacitors for transmitting control signals to the photoelectric conversion transistors, each of which is arranged in n pieces. 6 ₁ to 6 _o are sample and hold circuits, which perform on/off control of output signals from the emitter terminals of photoelectric conversion transistors 1 ₁ to 1 _o .
Controls MOS transistors 3 ₁ to 3 _o , capacitors 4 ₁ to 4 _o that accumulate the output signals, and reading of the accumulated output signals from the capacitors.
It is composed of MOS transistors 5 ₁ to 5 _o . 19 is a logic circuit that controls the on/off operation of the MOS transistors 5 ₁ to 5 _o ; 21 is an amplifier that reads out the output signal; 20 is a common output line; 24
18 is a MOS transistor that discharges the charge accumulated in the common output line 20; 18 is a positive voltage input terminal;
15 is a power input terminal, 22 is an output terminal, and 23 is a power input terminal.
16 is a control signal input terminal that sends a control signal to the MOS transistor 24; 16 is a control signal input terminal that sends a control signal to the MOS transistors ₃₁ to _3o ; 17 is a control signal input terminal that sends a control signal to the capacitors ₂₁ to _2o ;
7 ₁ to 7 _o are output terminals of the logic circuit.

The operation of the first embodiment of the photoelectric conversion device according to the present invention will be described below. Here, MOS transistors 3 ₁ to 3 _o , 5 ₁ to 5 _o , 24 shown in FIG.
is the N channel.

In the storage operation, first, the control signal input terminal 16 is set to H.
Input the level and turn on MOS transistors 3 ₁ to 3 _o .
ON state, output terminals 7 ₁ to 7 _o of logic circuit 19
All of them output H level to turn on the MOS transistors ₅₁ to _5o , and input H level from the control signal input terminal 23 to turn on the MOS transistor 24.
By turning on the ON state, all the emitters of the photoelectric conversion transistors 1 ₁ to 1 _o are grounded, and by further inputting a positive bias voltage from the positive voltage input terminal 18, all of the photoelectric conversion transistors 1 ₁ to 1 _o are grounded. Bias the collector with a positive potential.

Furthermore, due to the refresh operation described later, the bases of the photoelectric conversion transistors 1 ₁ to 1 _o are at a negative potential −
aV _RF is set. In this state, the photosensor cell is irradiated with light to accumulate holes in the base. Here, the accumulated voltage of the base is assumed to be ΔV _B.

In the read operation, an H level is input to the control signal input terminal 16 to turn on the MOS transistors 3 ₁ to 3 _o , and an L level is output from all output terminals 7 ₁ to 7 _o of the logic circuit 19 to turn on the MOS transistor 5 _{1 .} ~5
By turning _o off, all emitter terminals of photoelectric conversion transistors 1 ₁ to 1 _o are connected to capacitor 4.
₁ to 4 Connect with _o . Furthermore, by inputting a positive bias voltage from the positive voltage input 18, all the collectors of the photoelectric conversion transistors 1 ₁₁ to 1 _1o are biased to a positive potential. In this state, when a pulse of positive voltage V _RE is input from the control signal input terminal 17, the base potential of the photoelectric conversion transistor of the photosensor cell irradiated with light becomes a(V _RE - V _RF ) + ΔV _B , and the base current changes. A collector current thus determined flows, and the output voltage (optical information signal) of the photoelectric conversion transistor is held in the connected capacitor. On the other hand, the base voltage of the photoelectric conversion transistor of the photosensor cell that is not irradiated with light is a(V _RE − V _RF )
When V _RE = V _RF , the base voltage becomes 0 V and no charge is accumulated in the connected capacitor.

To read the voltage held in the capacitors 4 ₁ to 4 _o from the output terminal 22, the control signal input terminal 1
Input L level from 6 to MOS transistor 3 ₁
~3 _o is turned off, output terminals 7 ₁ ~ 7 _o of the logic circuit sequentially output H level, and the MOS
This is realized by sequentially turning on the transistors 5 ₁ to 5 _o . However, each time each held voltage is read out from the output terminal 22 through the amplifier 21, an H level is input from the control input terminal 23 to turn on the MOS transistor 24, and the signal is accumulated in the read capacitor. Discharge the accumulated charge and set the control input terminal 23 to L level again.
The MOS transistor 24 is turned off. In this way, one line can be read by sequentially performing the read operation from the sample hold circuits 6 ₁ to 6 _o to the output terminal 22 for 6 ₁ to 6 _o .

Here, for example, a certain photoelectric conversion transistor 1
The time required to read from sample hold circuit 6 _i from _i to sample hold circuit 6 i is t _RE1 , the time required to read the voltage held in sample hold circuit 6 _i from output terminal 22 t _RE2 , capacitor 4 of sample hold circuit 6 _i If the time required to discharge the charge of _i is t _BE3 , and if each sensor cell is under the same conditions, the time required to read one line is t _RE1 + n
(t _RE2 + t _RE3 ). Sample hold circuit 6 ₁ ~
Since high- _speed switching MOS transistors are used for the MOS transistors 5 ₁ to 5 _o constituting the capacitor 4 _i , the output terminal 22
The readout time _tRE2 and the charge discharge time _tRE3 are small values. On the other hand, photoelectric conversion transistor 1 ₁
~1 _o has an amplification effect, but as the density of optical sensor cells increases, the size of each cell decreases, so the amount of carriers generated in the base region decreases, and the emitter current remains at a certain level. value. Therefore, the readout time t _RE1 from the photoelectric conversion transistor is relatively long, t _RE1 〓t _RE2 , t _RE1 〓 _{t RE3}
becomes.

Here, the readout time t _RE1 from the photoelectric conversion transistor depends on the capacitance of the capacitors 4 ₁ to 4 _o .
Further, the capacitance of the capacitors 4 ₁ to 4 _o is determined by the stray capacitance of the common output line 20.

Therefore, in this embodiment, capacitors 4 ₁ to
The one line read time when the capacitance of 4 _o is set equal to the stray capacitance of the common output line 20 will be compared with the one line read time in the conventional example shown in FIG.

First, in the conventional example shown in _{FIG .}
Similarly, since the discharge time from the common output line 20 is t _RE3 , the one line read time is n(t _RE1 +t _RE3 ). Similar to the photoelectric conversion device according to the present invention described above, t _RE1 〓t _RE3 . Comparing the readout time of one line with the photoelectric conversion device according to the present invention in a line sensor with a large value of n, it becomes n(t _RE1 +t _RE3 ) 〓 t _RE1 +n (t _RE2 + t _RE3 ), and the photoelectric conversion device according to the present invention indicates that sufficiently high-speed reading is possible.

Next, in the refresh operation, an H level is input to the control signal input terminal 16 to turn on the MOS transistors 3 ₁ to 3 _o , and an H level is output to all output terminals 7 ₁ to 7 _o of the logic circuit 19.
The MOS transistors 5 ₁ to 5 _o are turned on, and an H level is input from the control signal input terminal 23 to turn the MOS transistor 24 on, and all emitters of the photoelectric conversion transistors 1 ₁ to 1 _o are grounded. In addition, by inputting a positive bias voltage from the positive voltage input terminal 18, all collectors of the photoelectric conversion transistors 1 ₁ to 1 _o are biased to a positive potential. In this state, a refresh operation is performed by inputting a pulse of positive voltage V _RF from the control signal input terminal 17, and as described above, the base potential returns to the initial state of negative potential -aV _RF . At this time, at the same time as the base potential is reset, the potentials of the capacitors 4 ₁ to 4 _o are also reset.

The operation of the line sensor is realized by repeating the storage, readout, and refresh operations described above.

Note that in this embodiment, the MOS transistors 3 ₁ to 3
Although 3 _o , 5 ₁ to 5 _o , and 24 have all been described as n-channels, they can also be constructed of complementary MOS transistors that are p-channels or a combination of p-channels and n-channels.

Next, a second embodiment of the photoelectric conversion device according to the present invention will be described.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

In the figure, 1 ₁₁ to 1 _no photoelectric conversion transistors, 2 ₁₁ to 2 _no photoelectric conversion transistors 1 ₁₁ to
_1. They are capacitors that transmit control signals to the capacitors, and are two-dimensionally arranged in n columns and m rows.
6 ₁ to 6 _o are sample and hold circuits, and MOS transistors 3 ₁ to 3 _o control output signals from the photoelectric conversion transistors 1 ₁₁ to 1 _no emitter terminals.
and a capacitor 4 connecting one of the main electrodes of the MOS transistors 3 ₁ to 3 _o and the power input terminal 15.
₁ to 4 _o , MOS transistors 9 ₁ to 9 _o whose gate electrodes are connected to one main electrode of the MOS transistors 3 ₁ to 3 _o , and the MOS transistors 9 ₁ to 9 _o and the power input terminal 25. The main electrodes are connected to each other, and the gate electrode is connected to the terminal 7 of the logic circuit 19a.
MOS transistors 5 _{1 to 7} connected to MOS transistors ₁ to 7 _o , respectively
_5o , and resistors ₈₁ to _8o , which are connected at one end to the other main electrode of the MOS transistors ₉₁ to _9o and the common output line 20, and at the other end to the power supply input terminal 15. 17 is a control signal input terminal that provides a control signal to the optical sensor cell; 16 is a control signal input terminal that provides a control signal to the MOS transistors 3 ₁ to 3 _o ;
18 is a positive voltage input terminal, 22 is an output terminal, and 26 is a positive voltage input terminal.
A control input terminal 27 provides a control signal to the MOS transistors ₁₀₁ to _10o , and a power input terminal 27.

The operation of the second embodiment of the present invention will be described below with reference to FIG.

As described above, the photoelectric conversion transistors 1 ₁₁ to 1 _no according to the present invention realize photoelectric conversion through basic operations consisting of an accumulation operation, a read operation, and a refresh operation. All shown in Figure 4
Assuming that the MOS transistor is N-channel,
It is assumed that the positive power input terminal 18 and the power input terminal 25 are at a positive voltage, and the power input terminal 15 and the power input terminal 27 are grounded.

In the storage operation, first, by inputting an H level to the control input terminal 26, the MOS transistors 10 ₁ to 10 _o are turned on, and all emitters of the photoelectric conversion transistors 1 ₁₁ to 1 _on are grounded.
In addition, all the collector terminals of the photoelectric conversion transistors 1 ₁₁ to 1 _no are fixed to a positive voltage by a positive voltage input from the positive power input terminal 18, and a positive voltage V is input from any terminal of the control signal input terminals 17 ₁ to 17 _n . _{An RF} pulse is applied, and the bases of the photoelectric transistors 1 ₁₁ to 1 _no are set at a predetermined negative potential. In this state, the photosensor cell is irradiated with light to accumulate holes in the base.

Note that the pulse application for giving a negative potential to the bases of the photoelectric conversion transistors 1 ₁₁ to _{1 no} may be applied to only one row, or may be applied to multiple rows at the same time.

Next, in the read operation, an H level is input to the control signal input terminal 16 to turn on the MOS transistors ₃₁ to _3o , and an L level is input to the control signal input terminal 27.
Input the level and select MOS transistors 10 ₁ to 10
By turning _o off, all the emitter terminals of photoelectric conversion transistors 1 ₁₁ to 1 _no are opened, and by the positive bias voltage input from the positive voltage input terminal 18, photoelectric conversion transistors 1 ₁₁ to 1 no are turned off.
1 Bias all collector terminals of _no to positive potential. In this state, the control signal input terminals 17 ₁ to 1
7 Apply pulses of positive voltage V _RE sequentially or arbitrarily to _n .

Assume now that a pulse of voltage V _RE is applied to input terminal 17 _i . As a result, the outputs of the photoelectric conversion transistors 1 _i1 to 1 _io are held in the capacitors 4 ₁ to 4 _o of the sample and hold circuit, and the accumulated voltages of the capacitors 4 ₁ to 4 _o are transferred to the MOS transistors 9 ₁ to 9 _o. is applied to each gate electrode.

Next, the output terminal 22 is output from the sample hold circuit.
For reading, input an L level signal from the control input terminal 16 and read the MOS transistors 3 ₁ to 3 _o .
OFF state, output terminal ₇ of logic circuit 19
~7 Sequentially output H level signals from _o to MOS
This is performed by sequentially turning on the transistors 5 ₁ to 5 _o .

That is, when an H level is output from the output terminal ₇₁ of the logic circuit 19, the MOS transistor ₅₁ is turned on, and the positive voltage applied to the terminal 25 is applied to the MOS transistor ₉₁ .
As a result, a current corresponding to the voltage applied to the gate electrode flows between the two main electrodes of the MOS transistor ₉₁ .
A voltage corresponding to the accumulated voltage of the capacitor 4 ₁ is generated across the resistor 8 ₁ , and this voltage is outputted from the output terminal 22 as an optical information signal of the photoelectric conversion transistor 1 _i1 . Similarly, capacitor 4 ₁ ~
The voltages accumulated at 4 _o are sequentially read out to the output terminal 22 and output.

When the i-th row optical information signal is thus read out, the accompanying photoelectric conversion transistors 1 _i1 to 1 _io and the capacitors 4 ₁ to 4 _o are refreshed.

First, an H level is input from the control input terminal 16 to turn the MOS transistors 3 ₁ to 3 _o on, and an H level is input from the control input terminal 26 to turn the MOS transistors 10 ₁ to 10 _o on. As a result, the charges accumulated in the capacitors 4 ₁ to 4 _o are
It is discharged through MOS transistors 3 ₁ to 3 _o and 10 ₁ to 10 _o . Similarly, the refresh operation of the photoelectric conversion transistors 1 _i1 to 1 _io is performed by applying a positive voltage to the input terminal 17 _i .

When the above refresh operation is completed, the photoelectric conversion transistors 1 _i1 to 1 _io start the storage operation.
In parallel with this, the read operation and refresh operation of the photoelectric conversion transistors 1 _j1 to 1 _jo in the j-th row are performed in the same manner as described above.

That is, since the optical information signal of each row is collectively held in the capacitors 4 ₁ to 4 _o and then outputted serially, the reading and refreshing operations of a certain row and the storage operations of other plural rows are Can be done at the same time.

Note that the read operation and refresh operation may be performed not only for each row but also for a plurality of rows simultaneously.

The operation of the circuit shown in FIG. 4, which is the second embodiment of the present invention, has been described above. The characteristics of the circuit shown in FIG. can be done at the same time. Therefore, the photoelectric conversion operation can be performed in a sequence in which the time from the refresh operation to the read operation for each row is constant regardless of the row.

FIG. 5 is an operation sequence diagram for explaining the operation of the second embodiment more clearly.

In the same figure, the period indicated by the symbol R is the period from the photoelectric conversion transistor to the sample and hold circuits 6 ₁ to 6 _o.
The period _indicated by _{symbol R}
The period indicated by the symbol ST indicates the storage operation, and the period indicated by the symbol W indicates that a certain photoelectric conversion transistor other than the row marked with the symbol W is activated. This indicates that reading is in progress. That is, in period W, the base potential of the photoelectric conversion transistor is negative potential and is in the storage operation state, but the emitter potential is read from the emitter of the photoelectric transistor in another row to the sample and hold circuit. The potential is changing to positive. but,
In this case, the emitter potential and base potential maintain a reverse bias state, which is similar to the storage operation. What should be noted in FIG. 5 is that the time from symbol R in each row until the next symbol R appears is constant regardless of the row. This is particularly significant when the number of rows m increases, that is, when the density is increased and the number of optical sensor cells is increased. That is, when the number of rows m is large, it takes a long time to read the output from the first row to the mth row. Therefore, for example, if all rows are refreshed once and then the storage and read operations are performed, the last row to be read will take a long time to read, and the photoelectric conversion characteristics will be significantly lower than the first row to be read. However, in the circuit of FIG. 4 and the operation sequence of FIG. 5 according to the present invention, the time from the refresh operation to the read operation is constant regardless of the row, which improves the above disadvantage. can. In the second embodiment of the present invention shown in FIG. 4, all MOS transistors are N-channel.
Although the example shown is composed of MOS transistors, P-channel MOS transistors or P-channel MOS transistors are also used.
Channel MOS transistor and N-channel
A complementary circuit combining MOS transistors can be used as appropriate. Further, although an example has been shown in which a source follower type amplifier is used as the sample and hold circuit amplifier, it is also possible to use other types of amplifiers such as a differential type amplifier.

〔Effect of the invention〕

As explained in detail above, the photoelectric conversion device according to the present invention stores the readout signals of a plurality of optical sensor cells in one capacitor and then outputs them sequentially. It is possible to perform high-resolution and high-speed operation.

In addition, when the optical sensor cells are arranged in a two-dimensional manner, each optical sensor cell can perform a refresh operation immediately after the readout operation is completed, so the storage operation period of each optical sensor cell becomes uniform, the photoelectric conversion characteristics are stabilized, and the conventional Since there is no idle time after the read operation is completed, high-speed operation can be performed. Further, at the same time as resetting the potential of the capacitive element, the first main electrode region is set to the reference potential,
A forward bias is applied between the control electrode region and the first main electrode region to eliminate the capacitor accumulated in the control electrode region. At this time, the second main electrode region is held at a reverse bias potential and the potential of the control electrode region is reset, so that noise due to junction capacitance etc. is less likely to occur and the reset operation is simple.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a photosensor cell constituting a photoelectric conversion device according to the present invention. FIG. 2 is an equivalent circuit of the optical sensor cell. FIG. 3 is a circuit diagram of a first embodiment of a photoelectric conversion device according to the present invention. Fourth
The figure is a circuit diagram of a second embodiment of the photoelectric conversion device according to the present invention. FIG. 5 is an operation sequence diagram of a second embodiment of the photoelectric conversion device according to the present invention. FIG. 6 is a circuit diagram of a conventional photoelectric conversion device. 1 ₁ ~ 1 _o , 1 ₁₁ ~ 1 _no ...photoelectric conversion transistor,
2 ₁ ~ 2 _o , 2 ₁₁ ~ 2 _no ... capacitor, 3 ₁ ~ 3 _o ...
MOS transistor, 4 ₁ ~ 4 _o ... Capacitor, 5 ₁
~ _5o ...MOS transistor, ₆₁ ~ _6o ...sample hold circuit, 81 _{~ 8o} ...resistor, 91 _{~ 9o} ...MOS
Transistor, 10 ₁ to 10 _o ...MOS transistor, 21...amplifier, 24...MOS transistor.

Claims (1)

[Claims] 1. A control electrode region made of a semiconductor of a first conductivity type, and first and second main electrode regions made of a semiconductor of a second conductivity type different from the first conductivity type. , a plurality of transistors capable of accumulating carriers generated by receiving optical energy in the control electrode region; a first switch for selectively holding the first main electrode region at a reference potential; a second switch for selectively connecting a first main electrode region and a capacitive element for reading out a signal from the transistor, and a photoelectric conversion device that performs an accumulation operation, a readout operation, and a refresh operation. Means for biasing the second main electrode region in a direction opposite to the control electrode region during the storage operation, the readout operation, and the refresh operation, and sequentially scanning the signals read out to the capacitive element. scanning means for maintaining the first main electrode region and the capacitive element at the reference potential by operating the first switch and the second switch during the refresh operation; and means for forward biasing a junction between the control electrode region and the first main electrode region to reset the potential of the control electrode region and the capacitor.