JPH05242003A - Data processor - Google Patents

Abstract

PURPOSE:To execute a data reception processing at a high speed, in the data processor provided with an input/output control local processor and a main processor. CONSTITUTION:When an input/output control part 11 receives a frame through a circuit 6, a local CPU 12 in an input/output control local processor writes it in a local memory 13, and thereafter, applies an interruption to a main CPU 21 through an interruption channel 5. In response thereto, the main CPU 21 reads in the frame written in the local memory 13, and thereafter, tries to write it in a receiving data buffer on a main memory 23. As a result, a cache control part 24 writes the frame in an exclusive block corresponding to the receiving data buffer provided in a cache memory 22. Thereafter, a processing to the frame is executed on the cache memory 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor having an input / output control local processor and a main processor.

[0002]

2. Description of the Related Art Conventionally, in a data processing apparatus having an input / output control local processor and a main processor, when a frame is sent from another data processing apparatus or the like, first, the input / output control local processor is A frame is received, and data, error correction code, etc. are extracted from the received frame. Thereafter, the input / output control local processor performs processing such as error correction and transfers the corrected data to the reception data buffer provided on the main memory of the main processor.

When the corrected data is stored in the main memory, the main processor performs processing on the main memory.

[0004]

As described above, conventionally, in the input / output control local processor, data and the like are fetched and error correction processing is performed, and the corrected data is further stored in the main memory of the main processor. Transfer to
Since the main processor was made to perform the processing on the main memory, it was difficult to increase the processing speed.

An object of the present invention is to increase the processing speed of a data processing device having an input / output control local processor and a main processor.

[0006]

In order to achieve the above object, the present invention provides a data processing device comprising an input / output control local processor and a main processor, wherein the input / output control local processor is provided with a local memory. , Writing the received frame to the local memory,
A local CPU that generates an interrupt to the main processor is provided, and a cache memory, a main memory, and a frame stored in the local memory in response to the interrupt are read into the main processor and then read. Main CPU for requesting to write a subframe to the cache memory, and the main CP
A cache control unit for writing the frame in the cache memory in response to the request from U is provided.

[0007]

Operation: Local C in input / output control local processor
The PU writes the received frame to the local memory and issues an interrupt to the main processor.

When the main CPU in the main processor is interrupted, it reads the frame stored in the local memory and then tries to write the read frame in the reception data buffer of the main memory.

Then, the cache controller writes the frame in the cache memory. Main CP
U processes the received frame on the cache memory.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a data processor is an input / output control local processor 1.
And a main processor 2.

The input / output control local processor 1 and the main processor 2 are connected via a bus 3, an input / output control channel 4 and an interrupt channel 5.

The input / output control local processor 1 includes an input / output control unit 11, a local CPU 12, and a local memory 13. The line 6 is connected to the input / output control unit 11.

The main processor 2 is a main CPU 21.
And a cache memory 22, a main memory 23, and a cache control unit 24.

In preparation for receiving a frame added from another data processing device or the like via the line 6, the main CPU 21 in the main processor 2 receives the input / output control unit in the input / output control local processor 1 via the input / output control channel 4. 1
The input / output control information indicating the flag sequence set to 1, the number of bits in the address section, the number of bits in the control section, etc. is read, and the read input / output control information is used as write data to store data in a predetermined area of the main memory 23. A write request with the address as the write address is issued.

Then, the cache control unit 24 determines whether or not a block including the predetermined area exists in the cache memory 22, and if it exists (in the case of a cache hit), the predetermined area in the cache memory 22 exists. Input / output control information is written in the corresponding block.
If the block does not exist (in the case of a cache miss hit), the above block is transferred from the main memory 23 to the cache memory 2
2 is transferred to the above block, the input / output control information is written in the above block on the cache memory 22.

When a frame is sent through the line 6 after the above-mentioned preparation for reception is completed, the input / output control unit 11 starts receiving the frame and the local CPU 12
Receive interrupt is generated for.

When a reception interrupt occurs, the local CPU 12 writes the frame received by the input / output control unit 11 in the local memory 13 as it is.

When a frame is written in the local memory 13, the local CPU 12 interrupts the main CPU 21 in the main processor 2 via the interrupt channel 5 to notify that the frame has been received.

Main CPU 21 in the main processor 2
Is interrupted, the frame stored in the local memory 13 is read via the bus 3, the read frame is used as write data, and the main memory 23
A write request with the address of the above receive data buffer as the write address is issued.

The cache memory 22 is provided with a dedicated block corresponding to the above-mentioned receive data buffer, and the cache control unit 24 is provided in the cache memory 22 when the main CPU 21 issues the write request. Write the frame in a dedicated block.

After that, the main CPU 21 requests reading of the input / output control information stored in the main memory 23. At that time, if a block including the input / output control information exists in the cache memory 22, the cache control unit 24 reads the input / output control information from the cache memory 22 and transfers it to the main CPU 21. If it does not exist, the cache control unit 24 transfers the block including the input / output control information on the main memory 23 to the cache memory 22,
After that, the input / output control information stored in the cache memory 22 is passed to the main CPU 21.

When the main CPU 21 receives the input / output control information, the main CPU 21 performs, on the cache memory 22, processing such as data and error correction code extraction, error correction processing, etc. which the conventional input / output control local processor has performed. After that, the processing which the main processor has conventionally performed is performed on the cache memory 22.

[0024]

As described above, according to the present invention, since the receiving process is performed on the cache memory, the processing speed can be increased as compared with the conventional example.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 ... I / O control Local processor 11 ... I / O control unit 12 ... Local CPU 13 ... Local memory 2 ... Main processor 21 ... Main CPU 22 ... Cache memory 23 ... Main memory 24 ... Cache control unit 3 ... Bus 4 ... I / O control Channel 5 ... Interrupt channel 6 ... Line

Claims (3)

[Claims] 1. A data processing device comprising an input / output control local processor and a main processor, wherein the input / output control local processor writes a local memory and a received frame to the local memory, A main CPU that generates an interrupt to the processor, wherein the main processor reads a cache memory, a main memory, and a frame stored in the local memory in response to the interrupt; Main C requesting to write to the cache memory
A data processing device comprising: a PU; and a cache control unit for writing the frame in the cache memory in response to the request from the main CPU. 2. The data processing apparatus according to claim 1, wherein the main CPU performs processing for the received frame on the cache memory. 3. The cache memory has a dedicated block corresponding to a reception data buffer, and the cache control unit writes the frame in a dedicated block on the cache memory. The described data processing device.