JPH05242016A - Bus width conversion circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Peripheral devices used in various computers,
When performing data transfer between the peripheral device and the computer main unit, the low-speed processing of data transfer, which was dependent on the bus width of the data bus of the conventional peripheral device, was eliminated, and the system bus of the computer main unit was made faster. The purpose is high-speed data transfer that can be followed. [Structure] Between the data bus 1 of the system bus of the computer main body and the data bus direction of the peripheral device controller 3, and between the data bus 2 of the peripheral device controller 3 and the data bus 1 direction of the system bus of the computer main body,
High-speed transfer is realized by providing dedicated latches 6 to 13 and controlling them independently by the latch control unit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus width conversion circuit for performing high speed processing when transferring data having different bus widths in a computer system.

[0002]

2. Description of the Related Art In recent years, computer systems have become remarkably faster as the performance of microprocessors has improved.
In response to the increase in the data bus width of the microprocessor, which contributes to the increase in speed, the data bus width of the system bus of the computer itself is also increasing. On the other hand, the peripheral device connected to the data bus of the system bus of the computer main body through the peripheral device controller does not follow the increase in the data bus width due to the sharing relationship with the conventional device. That is, the data bus width of the controller is determined in accordance with the standard of the peripheral device, and it cannot always match the data bus width of the system bus of the computer main body. Therefore, the access speed between the data bus of the system bus of the computer main body and the data bus of the peripheral device controller is related to the performance of the entire system. In a computer system having different bus widths between the data bus of the system bus of the computer body and the data bus of the peripheral device controller, it is necessary to improve the data transfer rate as much as possible.

A conventional method of transferring data between the data bus of the system bus of the computer main body and the data bus of the peripheral device controller will be described below with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a conventional data transfer circuit. In the figure, 1 is a 32-bit wide data bus of a computer main body, 2 is an 8-bit wide data bus of a peripheral device controller, and a peripheral device controller 3, a peripheral device 4, and an 8-bit wide bidirectional. It is composed of buffers 15, 16, 17, and 18 and a bidirectional buffer control unit 14. The data transfer method between the 32-bit wide data bus 1 of the computer main unit and the 8-bit wide data bus 2 of the peripheral device controller is as follows. Transfer.

When data is transmitted from the system bus side to the peripheral device 4 side, after obtaining the right to use the system bus of the computer main body, according to the 8-bit wide data bus 2 of the peripheral device controller 3 of the peripheral device controller 3, The bidirectional buffer 15 is controlled by the buffer control unit 14 to transfer data. After the data transfer is completed, the system bus of the computer main body is once released. Next, after regaining the right to use the computer system bus,
The bidirectional buffer 16 is controlled by the buffer control unit 14 to transfer data. In this way, by controlling the bidirectional buffers 15, 16, 17, and 18 by the bidirectional buffer control unit 14 while sequentially obtaining the right to use the system bus of the computer main body, the 8-bit width of the peripheral device controller of the peripheral device controller 3 is controlled. Data transfer corresponding to the data bus 2 of.

When sending data from the peripheral device 4 side to the system bus side, first, the right to use the system bus of the computer main body is obtained, and then the bidirectional buffer 15 is controlled by the buffer control section 14 to make the peripheral device controller 3 Data is transferred to the system bus side of the computer main body in the bus width unit of the 8-bit wide data bus 2 of the peripheral device controller. After the data transfer is completed, the system bus of the computer main body is once released. Next, after the right to use the system bus of the computer main body is obtained again, the bidirectional buffer 16 is controlled by the buffer control unit 14 to transfer the data. In this manner, the bidirectional buffers 15, 16, 17, 18 are sequentially controlled by the bidirectional buffer control section 14, so that data transfer corresponding to the 8-bit wide data bus 2 of the peripheral device controller 3 of the peripheral device controller 3 is performed. ..

FIG. 4 is a timing chart showing the operation of the conventional example. In FIG. 4, 19-1, 19-2, 19-
Reference numerals 3 and 19-4 denote the time required to obtain the right to use the system bus of the computer main body, 20-1, 20-2, and 20.
-3 and 20-4 are data transfer times between the system bus and peripheral devices. In both cases of sending data from the system bus side to the peripheral device side and sending data from the peripheral device side to the system bus side, first obtain the right to use the computer system bus during the period 19-1. Then, in the period 20-1 thereafter, the bidirectional buffer 15 is changed to the buffer control unit 1 according to the 8-bit wide data bus 2 of the peripheral device controller 3 of the peripheral device controller 3.
4 to transfer data. After the data transfer is completed, the system bus of the computer main body is once released. Next, in the period 19-2, after obtaining the right to use the system bus of the computer main body again, the bidirectional buffer 16 is set in the buffer control unit 1 in the period 20-2.
4 to transfer data. In this way, the right to use the system bus of the computer main body is sequentially assigned 19-1, 1
Data transfer is performed by controlling the bidirectional buffers 15, 16, 17, and 18 by the bidirectional buffer control unit 14 while obtaining during the periods 9-2, 19-3, and 19-4.

In such conventional means, data transfer is performed in units of the data bus width on the peripheral device side regardless of the data bus width on the system bus side.

[0008]

In such a conventional configuration, the data transfer speed is limited by the data bus width of the peripheral device controller as compared with the speedup of the system bus of the computer main body, so that the entire computer system as a whole. I can't hope for speeding up.

The present invention solves the above problems, and an object of the present invention is to provide a bus width conversion circuit capable of high-speed data transfer.

[0010]

In order to achieve the above object, the present invention is directed to a data bus direction of a peripheral device controller from a data bus of a system bus of a computer main body.
High-speed transfer is realized by providing a dedicated latch corresponding to the transfer direction of the data bus and independently controlling between the data bus of the peripheral device controller and the data bus direction of the system bus of the computer main body.

[0011]

According to the present invention, in the above configuration, high-speed data transfer corresponding to the bus width of the data bus of the system bus of the computer main body can be performed without depending on the data bus width of the peripheral device controller.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A bus width conversion circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a bus width conversion circuit according to an embodiment of the present invention. In the figure, 1 represents a 32-bit wide data bus of a computer main system bus, and 2 represents an 8-bit wide data bus of a peripheral device controller. The peripheral device controller 3, the peripheral device 4, and the 8-bit wide data bus are shown. Latches 6, 7, 8, 9, 10, 1
It is composed of 1, 12, 13 and a latch control section 5. The data transfer method between the 32-bit wide data bus 1 of the computer main unit and the 8-bit wide data bus 2 of the peripheral device controller is as follows. Obtain the right to use the system bus. Then 3
Latches 10, 11, 12, and 2 bits wide data at one time
Latch by 13. After this latch, the system bus is released. After that, the latch 10 is first controlled by the latch control unit 5 according to the 8-bit wide data bus 2 of the peripheral device controller 3 to transfer the data. Next, the latch 11 is controlled by the latch controller 5 to transfer the data. In this way, the sequential latches 10, 1
The data is transferred by controlling 1, 2, and 13 by the latch control unit 5.

It will be described with reference to FIG. 2 that the data transfer speed can be increased by the above method. In FIG. 2, 19
Is the time required to acquire the right to use the system bus of the computer main body, 22-1, 22-2, 22-3, 22-
4 is a data transfer time between the system bus and the peripheral device. In the present invention, first, in the period of 19, the right to use the system bus of the computer main body is obtained. After that, the 8-bit wide latches 10, 11, 12, and 13 latch the transfer data from the system bus at one time during the data transfer time 21 between the system bus and the latch, and at the data transfer time 22 between the latch and the peripheral device. Data is sent from each latch. Compared to the conventional example, this embodiment enables latching at the first time of data transfer from the data bus 1 of the system bus of the computer main body.
Data can be transferred only between 0, 11, 12, 13 and the peripheral device controller 3, and the data transfer time can be shortened as compared with the conventional example. Further, after this data latch, the system bus is released and another processing can be performed.

When data is sent from the peripheral device 4 side to the system bus side, first, the latch 6 is controlled by the latch control unit 5, and the bus width unit of the 8-bit data bus 2 of the peripheral device controller 3 is set as follows. Latch the data. Next, the latch 7 is controlled by the latch controller 5 to latch the data. Thus the latch 6,
After all the latches 7, 8 and 9 have been latched by the latch control unit 5, the right to use the system bus of the computer main body is obtained, and the data transfer is performed once to the 32-bit wide data bus 1 of the system bus of the computer main body. To do.

It will be described with reference to FIG. 2 that the data transfer speed can be increased by the above method. In the present invention, first 8
Data transfer time 22-1, 22-2, 2 between the data latch and the peripheral device by the bit width latches 6, 7, 8 and 9
Latch with 2-3 and 22-4. Next, in the period of 19, the right to use the system bus of the computer main body is obtained. After that, the data is sent to the system bus once at a data transfer time 21 between the system bus and the latch. In this embodiment, as compared with the conventional example, data transfer to the data bus of the system bus of the computer main body is possible at the last one time. Therefore, before the data transfer, between the latches 6, 7, 8, 9 and the peripheral device controller. Data transfer is possible only by this, and the data transfer time can be shortened as compared with the conventional example. Further, before the data transmission, the system bus is released and another processing can be performed.

In this embodiment, the data bus width of the system bus of the computer main body is 32 bits and the data bus width of the peripheral device controller is 8 bits. It goes without saying that the data bus width of the controller is also effective for systems other than 8 bits.

[0018]

As is apparent from the above embodiments, by providing a plurality of exclusive latches and latch control sections in the data transfer direction, the speed of data transfer can be increased, and the computer main body By reducing the system bus occupation time, the performance of the entire computer system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a bus width conversion circuit according to an embodiment of the present invention.

FIG. 2 is a signal diagram showing a transition of operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional bus width conversion circuit.

FIG. 4 is a signal diagram showing an operation transition of a conventional bus width conversion circuit.

[Explanation of symbols]

1 computer system bus 32-bit width data bus 2 peripheral device controller 8-bit width data bus 3 peripheral device controller 5 latch control unit 6 8-bit width latch 7 8-bit width latch 8 8-bit width latch 9 8 bits Width latch 10 8 bit width latch 11 8 bit width latch 12 8 bit width latch 13 8 bit width latch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yosuke Furukawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A bus width conversion circuit comprising m / n latches between an m-width data bus of a system bus of a computer main body and an n-width data bus of a peripheral device controller. 2. A data transfer between a computer main body and a peripheral device converts a bus width of a unidirectional data bus.
The bus width conversion circuit described. 3. The data transfer between the computer main body and the peripheral device converts the bus width of the bidirectional data bus.
The bus width conversion circuit described.