JPH05242017A - Bus control system - Google Patents

Abstract

PURPOSE:To improve the bus efficiency at the time of executing a data transfer through a common bus between plural masters and a slave. CONSTITUTION:When one of plural masters 1-3 issues a command for a data transfer to a slave 4 through a common bus 7, the slave 4 receives this command by a receiving part s8, stores it in a command storage part s3, and also, executes release of the bus 7. In a pre-processing part s2 and a main processing part s1, the command is executed, while reading out the stored command in the command storage part s3. While this command is being executed, since the bus 7 is released, other masters 2-3 become useable.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a bus control system, and more particularly to a bus control system in the case where a plurality of masters send and receive data to and from a slave via a common bus.

[0002]

2. Description of the Related Art When configuring an information processing apparatus, in order to transfer data between a plurality of devices such as a central processing unit, a main storage device, an input / output device, etc., each device is connected to a commonly usable bus. To control.

In conventional bus control, when a master device for data transfer makes a bus use request and is permitted to use the bus in accordance with arbitration, the master device monopolizes the bus. Then, the transfer command is issued and the transfer data is transmitted or received, and after the transfer is completed, the bus is released to control one transfer cycle.

Therefore, while the slave device receives and processes the command issued from the master device, the master device is in a state of monopolizing the bus, and other masters cannot use the bus during the so-called exclusive bus use system. Is becoming

In the above-described conventional bus control method, when one master device uses the bus, it requests the use of the bus, and when the use of the bus is permitted, the bus monopolizes the bus and issues commands and sends and receives data. Performed during one bus usage cycle. Therefore, if the time required for command and data processing in the slave device becomes long, one bus use cycle becomes long, and there is a waiting time during which data transfer on the bus is not actually performed during internal processing of the slave device. However, there is a problem that transfer efficiency is reduced.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus control system which improves bus transfer efficiency.

[0007]

According to the present invention, a plurality of masters for issuing a command for data transfer, a data transmission bus common to the masters, and data transmission / reception according to a command sent via the bus A bus control system for an information processing apparatus including a slave for performing processing, comprising means for controlling release of the bus during command processing of the slave in response to reception of the command by one of the masters. A bus control system characterized by the above is obtained.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, masters 1 to 3 are connected to a slave 4 via common buses 6 and 7, and a master 1 is connected by a bus arbitration unit 5.
Arbitration for bus usage of ~ 3 is performed.

Masters 1 to 3 have the same structure, and master 1
Is only shown. The master 1 includes a main processing unit m1 that performs basic processing other than transfer control of the command / data bus 7, a bus use request unit m2 that requests use of the bus, and a control signal transmission / reception unit that transmits / receives and controls transfer control signals of the bus. m3, a command / data transmitting unit m4 for transmitting a command and data to the bus, a response receiving unit m5 for recognizing and receiving a response from the slave 4 to the command sent by the master to the bus, and a response from the slave 4 When data is transmitted, the data reception unit m6 that receives this data controls the transfer of the bus in accordance with the transfer request from the main processing unit, and when the transfer request for the bus is accepted, the new transfer request is not accepted until the transfer is completed. The transfer control unit m7 is configured to perform.

The main processing unit m1 is connected to the transfer control unit m7 by the transfer request m8 to the transfer control unit m7 and the transfer permission and end notification m9 from the transfer control unit m7, receives data from the data receiving unit m6 and transmits command data. Part m
4 is connected to an internal command / data bus m10 for sending a command / data.

The transfer control unit m7 receives the bus use request m11 and the bus use permission notification m12 to request the bus use request unit m2.
Then, the transmission / reception control m13 causes the control signal transmission / reception unit m3 to
In response to the command / data transmission request m14, the command data transmission unit m4, in the reception data transfer m15 to the data reception unit m6, and in the cycle end notification m16, the response reception unit m4.
5 are connected respectively.

The response receiving unit m5 instructs the cycle end instruction m17.
Also, it is connected to the control signal transmission / reception unit m3 at the response reception timing m18 and to the data reception unit m6 at the data reception timing m19.

The bus use request part m2 is a bus use request signal b.
1 and the bus use permission signal b2 are connected to the bus arbitration unit 5, the control signal transmission / reception unit m3 is connected to the control bus 6 by the control signal transmission / reception b3, and the command data transmission / reception unit m is connected.
4, the response receiver m5 and the data receiver m6 are connected to the command data bus 7 by the command / data transmission / reception b4.

The slave 4 has a main processing unit s1 for executing the execution process of the commands sent from the masters 1 to 3, and a pre-processing unit s for executing the pipeline operable process before passing it to the main processing unit.
2. A command storage unit s3 that temporarily stores commands transmitted from the master, a data storage unit s4 that temporarily stores data transmitted from the master, and a control that processes commands transmitted from the master in the order received. An in-order transfer control unit s5, a control signal transmission / reception unit s7 for transmitting / receiving and controlling a transfer control signal of the bus, a bus use request unit s6 for making a bus use request, and a command storage unit s3 for receiving a command sent from the master. Command receiving section s8, a data receiving section s9 that receives data transmitted from the master and sends it to the data storage section s4, and a response transmitting section s10 that transmits a processing end response to the master after the processing of the command transmitted from the master is completed. , The command is processed by the main processing unit s1, and the data transmission unit s11 transmits data to the master.

The main processing unit s1 is connected to the execution instruction transfer s12 and the execution data transfer s13, and the processing end notification s14 informs the sequential transfer control unit s5 to the internal transmission data bus s15.
Are connected to the data transmission section s11.

The preprocessing unit s2 is connected to the command storage unit s3 by the stored command transfer s16, to the data storage unit s4 by the stored data transfer s17, and to the order transfer storage unit s5 by the process acceptability notification s18. Command storage s
3 is a storage command transfer instruction s from the sequential transfer control unit s5
19, the received command transfer s from the command receiving unit s8
20 are connected to each.

The data storage section s4 is connected to the stored data transfer instruction s21 from the sequential transfer control section s5 and to the received data transfer s22 from the data receiving section s9, respectively. The sequential transfer control unit s5 notifies the bus use request unit s6 of the transmission / reception control s6 by the bus use request s23 and the bus use permission notification s24.
25, the control signal transmitting / receiving unit s7 is instructed to send data s
26, the data transmission / reception unit s11 is instructed to send a response transmission instruction s2.
7 are connected to the response transmission unit s10.

The control signal transmission / reception unit s7 is connected to the command reception unit s8 by the command reception timing s28 and the command cycle end instruction s29. The command reception unit s8 is connected to the data reception unit s9 at the data reception timing s30.

The bus use request section s6 is a bus use request signal a.
1 and the bus use permission signal a2 are connected to the bus arbitration unit 5, the control signal transmitting / receiving unit s7 is connected to the control bus 6 by the control signal transmitting / receiving a3, the command receiving unit s8, the data receiving unit s9, the response transmitting unit s10, and the data. The transmission unit s11 is connected to the command / data bus 7 by the command / data transmission / reception a4.

Next, the operation of the present embodiment configured as described above will be described. When a bus use request is generated in the main processing unit m1 in the master 1, the main processing unit m1 transfers the transfer control if the transfer control unit m7 notifies that there is no transfer of the bus currently being processed by the transfer request m8. The transfer request is sent to the part m7, and the command and data are sent to the command data sending part m4.

The transfer control unit m7 controls the bus use request unit m2 in response to the transfer request, and the bus use request unit m2 makes a bus use request to the bus arbitration unit 5. The bus arbitration unit 5 arbitrates the usage request and notifies the bus usage request unit m2 of permission of this request. When the bus use request unit m2 notifies the transfer control unit m7 that the use of the bus is permitted, the transfer control unit m7 controls the command data transmission unit m4 to send the command and data to the bus 7 and the control signal transmission / reception unit m3. It controls and causes the bus 6 to send a control signal of the bus.

When the command is sent to the bus 7, the control signal transmitting / receiving unit s7 sends a command receiving timing to the command receiving unit s8 by the control signal of the bus received from the bus a3, and the command receiving unit s8 sends the command at this timing. To receive. Further, the data receiving unit s9 is connected to the bus a4 according to the data reception timing sent from the command receiving unit s8
To receive data via. Upon receiving the command, the command receiving unit s8 controls the control signal transmitting / receiving unit s7 and sends a command cycle end notification to the control bus 6.

The control signal transmitting / receiving unit m3 receives the command cycle end notification, ends the cycle, and releases the bus. When the command transfer is completed, the transfer control unit m7 waits for a response from the slave. Until the response is received and the transfer is completed, the transfer control unit m7 does not permit the transfer and does not accept a new request.

In the slave 4, the command received by the command receiving section s8 is sent to the command storing section s3, and the data received by the data receiving section s9 is also sent to the data storing section s4. When the pre-processing unit s2 notifies that the process can be accepted, the order transfer control unit s5 controls the command storage unit s3 to send the command to the pre-processing unit s2. If there is data corresponding to the command, the data storage The part s4 is controlled to send data to the preprocessing part s2. The pre-processing unit s2 is capable of pipeline operation and can process the next command / data before sending the command / data to the main processing unit s1.

When the next command / data can be processed, the sequential transfer control unit s5 is notified. If the command storage unit s3 has an instruction to be processed next, the sequential transfer control unit s5
Is continuously sent to the preprocessing unit s2. The execution data is sent from the pre-processing unit s2 to the main processing unit s1 via the execution instruction s13, and the execution process is performed. The main processing unit s1 operates exclusively and does not accept the next instruction during execution of one process.

When the processing of the main processing section s1 is completed, the order transfer control section s5 is notified of the completion of the processing. When the processing instruction is data read from the slave, the main processing section s1 sends the data to the response transmission section s10. .. When the sequential transfer control unit s5 receives the processing end notification from the main processing unit s1, it controls the bus use requesting unit s6, and the bus use requesting unit s6 makes a bus use request to the bus arbitration unit 5.

When the bus arbitration unit 5 arbitrates to permit use of the bus, the sequential transfer control unit s5 controls the response transmission unit s10 to send a response to the command / data bus 7 and the control signal transmission / reception unit s7. , And sends control signals to the control bus 6.

When reading data from the slave 4, the sequential transfer control unit s5 controls the data transmission unit s11 to send the data to the bus 7. When the response command is sent to the bus, the control signal transmission / reception unit m3 receives the control signal and sends the response reception timing to the response reception unit m5. At this timing, the response receiving unit m5 receives the response, and in the case of a read command from the slave, sends the data receiving timing to the data receiving unit m6, and at this timing the data receiving unit m6 receives the sent data. ..

When the response receiving section m5 receives the response, it gives an instruction to end the response cycle, and the control signal transmitting / receiving section m3 sends a response cycle end notification to the bus 6. The control signal transmitting / receiving unit s7 receives the response cycle end notification, ends the cycle, and releases the bus.

When the response receiving unit m5 receives the response, the response receiving unit m5 notifies the transfer controlling unit m7, and the transfer controlling unit m7 notifies the main processing unit m1. In the case of a read command from the slave 4, the data receiving unit m6. Is controlled to cause the main processing unit m1 to transfer the data.

As described above, the master 1 releases the bus after issuing the command, permits the use of the bus by another master, and the slave 4
When the internal processing is completed after receiving the command, makes a bus use request and controls to send a response. Therefore, during command processing from the master 1, commands are also received and stored from other masters 2 and 3, the processes are executed in the order in which they are received, and a control is performed to send a response to each master after the process is completed. ..

Next, a description will be given using a timing chart. FIG. 2 is a timing chart of this embodiment. CLK
Is a clock signal, BRQ1 to BRQ4 masters 1 to 3 and slave 4
Bus use request signals BAK1 to BAK4 are bus use permission signals for masters 1 to 3 and slave 4. CMD is a timing signal for sending a command to the bus, DAT is a timing signal for indicating that a response is being sent to the bus, EOC is a timing signal for notifying the end of transfer of a command or response, and CAD is a command for sending to the bus. And data are shown respectively.

The master 1 activates BRQ1 (L level) at timing 2-11. When BAK1 becomes active (L level) at the timing of 2-12 and use of the bus is permitted, CMD becomes active (L level) at the timing of 2-13.
At the same time, the command c1 is sent to the bus to make BRQ1 inactive (H level). When BRQ1 becomes inactive (H level), BAK1 also becomes inactive (H level).

When the slave 4 receives the command c1, it becomes EO.
Activates C (L level), completes the command cycle, and releases the bus. Master 2 is timing 2-21
Make BRQ2 active (L level). When BAK2 becomes active (L level) at the timing of 2-22 and use of the bus is permitted, CMD becomes active (L level) at the timing of 2-23 and command c2 is sent to the bus and BRQ2 Is made inactive (H level). When BRQ2 becomes inactive (H level), BAK2 also becomes inactive (H level).

Further, the command d2 is followed by the data d2.
To the bus. When the slave 4 receives the command c2, it makes EOC active (L level), ends the command cycle, and releases the bus. Further, the data d2 is received.

The master 3 performs the same processing as the master 1.
When the bus use request is made by BRQ3 and the bus use is permitted by BAK3, the command c3 is sent to the bus and the bus is released.

The command c1 is preprocessed for 2-t11 hours.
2-t 12-hour main processing ends the processing. When the processing is completed, the slave 4 activates BRQ4 (L level) at the timing of 2-41, BRK4 becomes active (L level) at the timing of 2-42, and the use of the bus is permitted,
At the timing of 2-43, DAT is made active (L level), the response r1 is sent to the bus, and BRQ4 is made inactive (H level). When BRQ4 becomes inactive (H level), BAK4 also becomes inactive (H level).

Further, the data d1 is transmitted following the response r1. When the master 1 recognizes that r1 is a response to the command c1 issued by itself, EO at the timing 2-44.
C is made active (L level), the response cycle is completed, the bus is released, and the data d1 sent from the slave 4 is received.

Command c2 is 2-t21 pre-processing and 2-
The processing is completed by the main processing for t22 hours. The pre-processing can be pipelined, and if the waiting time of the pipeline processing is 2-tp, the processing of c1 is started and the processing of c2 can be executed after 2-tp time.

When the processing of c2 is completed, the slave 4 becomes 2-51
BRQ4 becomes active (L level) at the timing of
When K4 becomes active (L level) at the timing of 2-52 and the use of the bus is permitted, DAT becomes active (L level) at the timing of 2-53 and a response r2 is sent to the bus.
To make BRQ4 inactive (H level). BR
When Q4 becomes inactive (H level), BAK4 also becomes inactive (H level).

When the master 2 recognizes that r2 is a response to the command c2 issued by itself, the master 2 activates EOC at the timing 2-54 to end the response cycle and release the bus. Similarly, the command c3 issued by the master 3 starts the process of the command c2, and can be executed after 2-tp time, and is completed by the pre-process of 2-t31 time and the main process of 2-t32 time, and the response is returned. It is transmitted to the master 3.

After that, the masters 1 to 3 make a trial calculation of the transfer performance of the bus assuming that the bus is accessed at the shortest operable cycle interval.

The time for performing one transfer of the master 1 is BRQ1
If the response to the command issued from 2-11 is sent from the slave and EOC becomes active (L level) until 2-44, counting one pulse of CLK with 1T: It becomes 12T shown by CT1. 12T if word transfer is performed in one transfer cycle
The transfer time is one word.

The other masters also need the same transfer time, and when the effect of this embodiment is not obtained, the above transfer time has the maximum transfer capability.

In this embodiment, when the masters 1 to 3 operate in the shortest processing time, the master 1 activates the BRQ 1 (L level) 2-11 and the master 3 responds to the command issued by itself. During the time CT2 until 2-64 when the received EOC becomes active (L level), three transfer cycles of masters 1 to 3 are executed. Therefore, 1
When one word is transferred in one cycle, 18T / 3 word = 6T / 1 word.

[0047]

As described above, according to the present invention, when a plurality of masters are connected to the data transmission bus used in the information processing apparatus, while the slave is executing the instruction issued by the master, Since the master can use the bus and can continuously issue commands to the slave, issuing commands during the waiting time generated by the slave's command processing has the effect of improving bus usage efficiency.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the block of FIG.

[Explanation of symbols]

 1 to 3 master 4 slave 5 bus arbitration unit 6 control bus 7 command / data bus m1 main processing unit m2 bus use request unit m3 control signal transmission / reception unit m4 command data transmission unit m5 response reception unit m6 data reception unit m7 transfer control unit s1 Main processing unit s2 Pre-processing unit s3 Command storage unit s4 Data storage unit s5 Sequence transfer control unit s6 Bus use request unit s7 Control signal transmission / reception unit s8 Command reception unit s9 Data reception unit s10 Response transmission unit s11 Data transmission unit

Claims (1)

[Claims] 1. A plurality of masters for issuing a command for data transfer, a common data transmission bus for the master, and a slave for performing a data transmission / reception process according to a command transmitted via the bus. A bus control system for an information processing apparatus including, characterized in that means for controlling the release of the bus is provided during the command processing of the slave in response to the reception of the command by one of the masters. Bus control system.