JPH0524254A - Image processing device - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to reduce the memory capacity required for data transmission between the printer controller and the printer engine. In an image processing apparatus provided between a printer controller (not shown) and a printer engine (not shown), a main memory receives a command indicating a data transmission format from a printer controller at a preceding stage by a command processing unit 10. , The command processing unit 10 by the input / output switcher 8
The image data is input by switching to the data transmission format according to the command input from, and the image data is stored in the memories 1, 2 and 3 line by line. The image data is transmitted from the memory by switching to the data transmission format according to the command input from the unit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and, for example, to an image processing apparatus which stores a plurality of lines of input image data and processes it.

[0002]

2. Description of the Related Art Recently, as an output device of a computer,
Recording devices using electrophotographic technology such as laser beam printers have come into widespread use. These devices have many merits such as high image quality and low noise, which contributed to the rapid expansion of the DTP (desk top publishing) field particularly in terms of high image quality.

Most recently, multilevel image processing using pulse width modulation (hereinafter referred to as "PWM") has been proposed as a technique for achieving both resolution and halftone reproducibility at a higher level. Various types of image data transmission from the external device at that time are considered.

For example, in order to improve gradation in a printer that prints at 600 dpi (dot per inch),
Main scanning, sub-scanning 4 lines, total 16 dot units, ie 1
There is one that expresses multiple gradations, for example, 256 gradations, with 50 lines. In the case of considering the reduction of the page memory on the controller side also in the transmission type of image data at that time, (a) 8 bits (2 8 = 256) are transmitted in 150 dpi units.

(B) Four bits are divided into four lines in units of 600 dpi, and are added on the printer engine side to be converted into eight bits.

(C) Six bits are divided into two lines in units of 300 dpi, and added on the printer engine side to be converted into eight bits. There is a method such as.

In the methods (b) and (c), a plurality of multi-valued data must be referenced in order to determine the gradation of the pixel of interest, and a storage means is required on the printer engine side. is there.

In order to eliminate such a defect, the multi-valued image processing unit 50 shown in FIG. 5 is used. The multivalued image processing unit 50 is provided between a printer controller (not shown) and a printer engine (not shown). A printer controller (not shown) sends multi-valued image data 15 in synchronization with a synchronizing signal generated by a horizontal synchronizing circuit (not shown). The toggle memory 16 of the multi-valued image processing unit 50 adjusts a difference in data density between a printer controller (not shown) and a printer engine (not shown).
It has the same configuration as IFO (first in first out). For example, when the printer controller sends multi-valued image data of 300 dpi, one line is stored in the toggle memory 16, and when the next horizontal synchronizing signal is output, a clock having a frequency twice the written clock is used. The multi-valued image data for the line is read.

The multivalued image data 17 thus read out from the toggle memory 16 is input to the main memory unit 18 and stored for a predetermined line.

For example, in the case of the method (b), 4 bits for 7 lines including the line of interest 3 lines before and after the line of interest, that is, 28 lines, and in the case of the method (c), the line of interest is included. 6 bits for 3 lines, that is, 18 lines are stored. The addition processing unit 19 selects several lines from the multi-valued image data output from the main memory 18, adds them, converts them into 8 bits, and outputs them. The PWM processing unit 20 performs processing based on the 8-bit multivalued image data so as to express the gradation, and sends it to the printer engine.

The internal structure of the main memory 18 is shown in FIG.
Shown in. In FIG. 6, the 8-bit multi-valued image data sent from the toggle memory 16 is latched in the 3-state buffer 66. The memories 61 to 65 are 8-bit wide SRAMs and have a word length capable of storing image data for one line. For example, in the operation of the memory 61, several states are set in one address, and the stored multi-valued image data is output to the 3-state buffer 67 and then the image from the 3-state latch buffer 66 is output. Write the data. Also, to prevent data collision, 3
The latch signal of the state buffer 66, the output enable signal, and the output enable signal of the memory 61 are managed in different states. The other memories 62 to 65 and the three-state latch buffers 67 to 71 also perform the same operation, and by repeating this cycle, multi-valued image data is sequentially sent to the lower memory, and the main memory 1 of the entire main memory 1
The image data of a predetermined number of lines is always stored in 8.

[0012]

However, in the above-mentioned conventional example, since each memory is assigned to each line, the data transmission format of the above three methods (a), (b), (c) is used. To support, I needed a lot of memory. That is, as shown in FIG. 7, since it is necessary to store a maximum of 7 lines of image data, the line "4" must be the target line, that is, the print line, and the print misalignment in each data transmission format is required. In order to prevent this, for example, a delay of 3 lines is generated even at the time of transmitting 8 bits in the above (a) to align the printing positions. Therefore, there is a drawback that the sum of the maximum number of bits that must be stored for each line, that is, 46 lines must be stored.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object of the present invention is to provide an image processing apparatus capable of reducing a memory capacity required for data transmission between a printer controller and a printer engine. It is in the point of providing.

[0014]

[Means for Solving the Problems]
In order to achieve the object, the image processing apparatus according to the present invention, in the image processing apparatus for adjusting the data transmission format between the pre-stage device and the post-stage device, a command input means for inputting a command indicating the data transmission format from the pre-stage device, Data input means for inputting image data according to the command input by the command input means, storage means for storing the image data input by the data input means in line units, and the storage means according to the command input by the command input means And output means for outputting the image data stored in step 1 to the subsequent device.

[0015]

According to this structure, the command input means inputs a command indicating the data transmission format from the pre-stage device, the data input means inputs the image data according to the command input by the command input means, and the storage means inputs the image data. The image data input in step S1 is stored line by line, and the output unit outputs the image data stored in the storage unit to the succeeding device in accordance with the command input by the command input unit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. <First Embodiment> FIG. 1 is a block diagram showing a first embodiment of the image processing apparatus according to the present invention. In the present embodiment, the basic configuration of the image processing apparatus arranged between the printer controller and the printer engine is the same as that of FIG. 5, so the configuration of the main memory will be described.

In FIG. 1, reference numerals 1, 2 and 3 are 8-bit width memories having a capacity capable of storing one line of transmitted image data. Further, 4 to 7 are 3-state latches, and the input / output has an 8-bit width. An input / output switch 8 determines 32-bit output data from 32-bit input data by a 2-bit instruction signal 11 sent from the command processing unit 10.

A command processing unit 10 determines a data transmission format by a command 12 sent from a printer controller (not shown).

Input / output pins DQ1 to DQ of the memories 1, 2 and 3
Q8 is the input pin D1 of 3-state latch 5, 6, 7
The output pins M11 to M18, M21 to M28, and M3 of the input / output switching circuit 8 are simultaneously connected to D8.
1 to M38 are also connected.

Next, the operation will be described. Since the basic configuration is almost the same as the conventional example, the input / output switch 8 will be mainly described for each data transmission format.

FIG. 2 shows the input / output switch 8 according to the first embodiment.
3 is a diagram for explaining the connection state of FIG. 3, and FIG. 3 is a diagram for explaining the stored contents of the memory according to the first embodiment.

In the case of the 8-bit data transmission format, that is, the data transmission format of the above (a), the printer controller sends the 8-bit format by the command 12 before transmitting the data. In response to this, the command processing circuit 10 outputs an instruction signal 11 to the input / output switch 8. The input / output switch 8 receives the instruction signal 11 and inputs as shown in FIG.
Define output relationships. For example, input data bit 8
(MSB) is input to L18 of the input / output switch 8, and M
It is output from 18. After that, DQ of memory 1,2,3
8 is input for each horizontal synchronizing signal. Eight-bit data for each line is stored in the memories 1, 2, and 3.

FIG. 3 shows the stored contents of each memory. The addition processing section (not shown) outputs M41 to M48 of the input / output switch 8.
8 bits are input, and at this time, the delay of the actual print line is 3 lines.

Next, a 4-bit data transmission format, that is,
In the case of the data transmission format of (b) described above, the input / output switch 8 defines input / output as shown in FIG. 2 (b). That is,
Input image data bit 4 (MSB) is input / output switch 8
Input to L14, and then output from M14, and DQ1 to 4, DQ5 to 8 of memory 1 and memory 2 for each horizontal synchronization.
DQ1 to 4, DQ5 to 8 and memory 3 DQ1 to 4 and DQ
Input to Q5-8. As a result, 4 bits of image data for 6 lines are stored (see FIG. 3). In addition to the current line, 7-bit 4-bit data is sent to an addition processing unit (not shown) for processing. Also in this case, the delay of the print line is 3 lines.

The same applies to the 6-bit data transmission format, that is, the data transmission format of (c) described above. The input / output switch 8 is defined as shown in FIG.
The storage state of No. 3 is as shown in FIG. 3C, and a total of four lines of data are stored. The addition processing units are M25 to M28, M31 to M38, M41 to M46 of the input / output switch 8.
Select the output of and process. The printing delay in this case is 3
It is a line.

Further, in FIG. 2, the input / output switching unit 8 has three
It is a state output, and is controlled so as to collide with the output data of the memories 1 to 3.

As described above, according to the first embodiment, the input data can be stored in a structure in which a predetermined amount of memory is owned between the printer controller and the printer engine and multi-value image data for several lines can be stored. The memory capacity can be reduced by switching the data to be input to each memory according to the bit width of.

<Second Embodiment> FIG. 4 is a block diagram showing a second embodiment of the image processing apparatus according to the present invention.

In the above-described first embodiment, the delay from the current line to the printing line is uniquely 3 lines. Therefore, in the 8-bit transmission format, the 6-bit transmission format, etc., the memory of the first several lines is This is done for synchronization with other transmission formats, but in the second embodiment, this point is considered,
A command line has been added to enable output with the shortest delay. Since the basic structure is almost the same as that of the first embodiment, the description thereof will be omitted. Here, only the internal structure of the input / output switch 8 is shown in FIG.

In FIG. 4, in the shortest delay mode for 8-bit transmission of (d), the current line is directly connected to M41 to M48.
Therefore, 8-bit image data without a delay can be output to the addition processing unit. Further, in the case of (e) 6 bit transmission shortest delay, 1 line delay data can be output.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0032]

As described above, according to the present invention,
Between the printer controller and the printer engine,
The memory capacity required for data transmission can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a diagram illustrating a connection state of an input / output switch 8 according to the first embodiment.

FIG. 3 is a diagram illustrating stored contents of a memory according to the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the image processing apparatus according to the present invention.

FIG. 5 is a block diagram showing a configuration of a multi-valued image processing unit according to a conventional example.

FIG. 6 is a block diagram showing an internal configuration of a main memory unit according to a conventional example.

FIG. 7 is a block diagram showing storage contents of a main memory unit according to a conventional example.

[Explanation of symbols]

1,2,3 memory 4, 5, 6, 7 latch 8 I / O selector 10 Command processing circuit 16 Toggle memory part 18 Main memory section 19 Addition processing unit 20 PWM processing unit

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Claims (3)

[Claims] 1. An image processing apparatus for adjusting a data transmission format between a pre-stage device and a post-stage device, comprising command input means for inputting a command indicating the data transmission format from the pre-stage device.
Data input means for inputting image data according to the command input by the command input means, storage means for storing the image data input by the data input means in line units, and the storage means according to the command input by the command input means An image processing apparatus comprising: an output unit that outputs the image data stored in 1. to a subsequent apparatus. 2. The image processing apparatus according to claim 1, wherein the data input means includes switching means for switching to one of a plurality of data transmission formats prepared in advance in accordance with a command input from the pre-stage device. 3. An image processing apparatus according to claim 1, further comprising timing switching means for switching timing when outputting the image data stored in said storage means in accordance with a command input from said pre-stage device.