JPH05243730A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH05243730A JPH05243730A JP4555192A JP4555192A JPH05243730A JP H05243730 A JPH05243730 A JP H05243730A JP 4555192 A JP4555192 A JP 4555192A JP 4555192 A JP4555192 A JP 4555192A JP H05243730 A JPH05243730 A JP H05243730A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- copper plating
- circuit
- current density
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000007747 plating Methods 0.000 claims abstract description 35
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052802 copper Inorganic materials 0.000 claims abstract description 21
- 239000010949 copper Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 7
- 238000005553 drilling Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 2
- 229910000365 copper sulfate Inorganic materials 0.000 description 5
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005488 sandblasting Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005201 scrubbing Methods 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Electroplating And Plating Baths Therefor (AREA)
- Electroplating Methods And Accessories (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、印刷配線板の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board.
【０００２】[0002]
【従来の技術】印刷配線板の代表的な製造工程として、
穴あけを行った後、全面に無電解銅めっきを行い、必要
な回路部分以外にレジストを形成した後、回路部分にの
み銅めっきを行う。この銅めっき後、レジストを剥離
し、無電解同めっきの層をエッチング除去し、回路を形
成する方法が知られている。2. Description of the Related Art As a typical manufacturing process of a printed wiring board,
After drilling, electroless copper plating is performed on the entire surface, a resist is formed on portions other than required circuit portions, and then copper plating is performed only on the circuit portions. A method is known in which after the copper plating, the resist is peeled off and the electroless same plating layer is removed by etching to form a circuit.
【０００３】[0003]
【発明が解決しようとする課題】この回路部分にのみ行
なう銅めっきの時に、下地に凹凸あるいは異物が存在す
ると、ヒゲ状の析出（ウィスカーと呼ぶ。）が発生し、
長さが百ミクロン程度に達すると、隣接するラインやパ
ッドとの間で短絡することがある。When copper is plated only on this circuit portion, if unevenness or foreign matter is present on the base, whisker-like deposition (called whiskers) occurs,
When the length reaches about 100 microns, a short circuit may occur between adjacent lines or pads.
【０００４】本発明は、回路銅めっきを行なう時に発生
するウィスカーの防止を目的とする。An object of the present invention is to prevent whiskers generated when plating circuit copper.
【０００５】[0005]
【課題を解決するための手段】本発明の印刷配線板の製
造法は、穴あけを行った後、全面に無電解銅めっきを行
い、必要な回路部分以外にレジストを形成し、回路部分
にのみ銅めっきを行い、レジストを剥離し、無電解同め
っきの層をエッチング除去し、回路を形成する印刷配線
板の製造方法において、電解銅めっきにより回路形成を
する場合、電流密度を２段階以上の段階にわけ、めっき
初期は低電流密度でめっきを行い、下地をカバーリング
した後、通常の電流密度でめっきを行うことを特徴とす
る。The method for manufacturing a printed wiring board according to the present invention is such that after making holes, electroless copper plating is performed on the entire surface and a resist is formed on portions other than the necessary circuit portions, and only the circuit portions are formed. When a circuit is formed by electrolytic copper plating in a method for manufacturing a printed wiring board in which copper plating is performed, a resist is peeled off, an electroless same plating layer is etched and removed, and a circuit is formed, a current density of two or more steps is used. It is characterized in that the plating is performed at a low current density in the initial stage of plating, the base is covered, and then the plating is performed at a normal current density.
【０００６】[0006]
【作用】硫酸銅めっきのウィスカーの原因は十分に解明
されていないが、銅めっきを行う基板の下地に凹凸が多
い場合、及びサンドブラストやスクラブ研磨などによ
り、表面にＡｌ2Ｏ3やＦｅ2Ｏ3の研磨粒子が残存した場
合にウィスカーが発生しやすいことがわかっている。一
方、発明者らは、鋭意検討の結果、図１に示すように、
このように下地に凹凸や粒子が存在した場合でも、低い
電流密度でめっきを行うことによりウィスカーの発生が
抑制されるという知見を得た。ウィスカーの発生は、突
起や異物表面に電流が集中し、ラセン状に銅の結晶が成
長することにより発生すると考えられるが、電流密度が
低い場合には、硫酸銅めっきのレベリング作用の方が勝
り、下地をカバーリングしてしまうためにウィスカーに
なりにくいと予想される。[Function] Although the cause of whisker in copper sulfate plating has not been fully clarified, Al 2 O 3 or Fe 2 O on the surface may be formed when there are many irregularities on the base of the substrate on which copper plating is performed, or by sandblasting or scrubbing. It is known that whiskers are likely to occur when the abrasive particles of 3 remain. On the other hand, as a result of intensive studies, the inventors have shown that, as shown in FIG.
As described above, it was found that even when unevenness or particles are present on the base, the generation of whiskers can be suppressed by plating at a low current density. The generation of whiskers is considered to occur due to the concentration of current on the surface of protrusions and foreign particles, and the growth of copper crystals in a spiral shape.However, when the current density is low, the leveling effect of copper sulfate plating is superior. , It is expected that whiskers are unlikely to occur because the foundation is covered.
【０００７】[0007]
【実施例】銅めっきの組成は、次のような組成で行っ
た。 （１）硫酸銅 ： ６０ g/l （２）硫酸 ：２００ g/l （３）塩素 ： ５０mg/l （４）添加剤（メルテックス社） ＣＧ−１２５Ａ ： ５ml/l ＣＧ−１２５Ｂ ： ２５ｍｌ／ｌ （５）温度 ： ２４℃ めっきを行う基板は、その効果を判り易くするために、
ウィスカーの発生を助長すると考えられる処理として、
宇治電化学工業株式会社製のトサエメリー＃２８０でホ
ーニング（サンドブラスト）した後、ドライフィルムを
ラミネートし、焼き付け現像を行った基板を用いた。こ
の基板を、銅めっきの前処理工程で脱脂、ソフトエッチ
ングを行い、硫酸銅めっき槽に入れ通電を行った。通電
は０．５Ａ／ｄｍ２ で２０分間通電した後、１．５A/
dm2 で５３分めっきを行った。ホーニングを行った基板
を硫酸銅めっきを行ったが、０．５A/dm2 で２０分めっ
き後、１．５A/dm2 で５３分めっきを行った基板は１Ｐ
Ｎ（５００×５００）あたり３個ウィスカーが発生した
が、１．５A/dm2 で６０分めっきを行った基板は５０個
ウィスカーが発生し、２段階でめっきを行った基板の方
がはるかにウィスカーの発生が少なかった。EXAMPLE The composition of copper plating was as follows. (1) Copper sulfate: 60 g / l (2) Sulfuric acid: 200 g / l (3) Chlorine: 50 mg / l (4) Additive (Meltex) CG-125A: 5 ml / l CG-125B: 25 ml / l (5) Temperature: 24 ° C. For the substrate to be plated, in order to make the effect easy to understand,
As a process that is thought to promote the occurrence of whiskers,
After honing (sandblasting) with Tosa Emery # 280 manufactured by Uji Denki Kagaku Co., Ltd., a dry film was laminated and baked and used for the substrate. This substrate was degreased and soft-etched in a pretreatment step of copper plating, and put in a copper sulfate plating bath to be energized. Energization is 0.5 A / dm 2 for 20 minutes, then 1.5 A / dm 2.
Plating was performed with dm 2 for 53 minutes. The substrate after honing was plated with copper sulfate, but after plating with 0.5 A / dm 2 for 20 minutes and then with 1.5 A / dm 2 for 53 minutes, 1P was used.
Three whiskers were generated per N (500 x 500), but 50 whiskers were generated on the substrate plated for 60 minutes at 1.5 A / dm 2 , and the substrate plated in two steps is much more There were few occurrences of whiskers.
【０００８】[0008]
【発明の効果】以上に説明したように、本発明によっ
て、ウィスカーの発生を防止した印刷配線板の製造方法
を提供することができる。As described above, according to the present invention, it is possible to provide a method for manufacturing a printed wiring board in which whiskers are prevented from occurring.
【図１】本発明の作用を説明するための線図である。FIG. 1 is a diagram for explaining the operation of the present invention.
【図２】従来例を説明するための線図である。FIG. 2 is a diagram for explaining a conventional example.
【図３】本発明の一実施例を説明するための線図であ
る。FIG. 3 is a diagram for explaining an example of the present invention.
Claims (1)
を行い、必要な回路部分以外にレジストを形成し、回路
部分にのみ銅めっきを行い、レジストを剥離し、無電解
同めっきの層をエッチング除去し、回路を形成する印刷
配線板の製造方法において、電解銅めっきにより回路形
成をする場合、電流密度を２段階以上の段階にわけ、め
っき初期は低電流密度でめっきを行い、下地をカバーリ
ングした後、通常の電流密度でめっきを行うことを特徴
とする印刷配線板の製造方法。1. After drilling, electroless copper plating is performed on the entire surface, a resist is formed on portions other than required circuit portions, copper plating is performed only on the circuit portions, the resist is peeled off, and electroless copper plating is performed. When a circuit is formed by electrolytic copper plating in a method of manufacturing a printed wiring board in which a layer is etched away to form a circuit, the current density is divided into two or more stages, and plating is performed at a low current density in the initial stage of plating. A method for manufacturing a printed wiring board, which comprises covering an underlayer and then plating at a normal current density.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4555192A JPH05243730A (en) | 1992-03-03 | 1992-03-03 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4555192A JPH05243730A (en) | 1992-03-03 | 1992-03-03 | Manufacture of printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05243730A true JPH05243730A (en) | 1993-09-21 |
Family
ID=12722500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4555192A Pending JPH05243730A (en) | 1992-03-03 | 1992-03-03 | Manufacture of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05243730A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000080496A (en) * | 1998-09-03 | 2000-03-21 | Ebara Corp | Filling plating method for base material having fine holes and / or fine grooves |
| KR20030080413A (en) * | 2002-04-08 | 2003-10-17 | 주식회사 심텍 | The electroplating method of micro via hole for the use of multiple layers printed circuit board using step current density |
| JP2003318544A (en) * | 2002-04-22 | 2003-11-07 | Toppan Printing Co Ltd | Multilayer wiring board and method of manufacturing the same |
| JP2004190073A (en) * | 2002-12-10 | 2004-07-08 | Toppan Printing Co Ltd | Structure-graded copper foil, method for producing the same, etching method, copper foil pattern, storage method |
| JP2004197228A (en) * | 2004-03-17 | 2004-07-15 | Ebara Corp | Filling plating method for base material having fine holes and / or fine grooves |
| JPWO2003030602A1 (en) * | 2001-09-28 | 2005-01-20 | 凸版印刷株式会社 | Multilayer circuit wiring board, IC package, and method for manufacturing multilayer circuit wiring board |
| JP2005256178A (en) * | 2005-05-18 | 2005-09-22 | Ebara Corp | Method for hole-filling plating of substrate having fine holes and / or fine grooves |
| JP2005272874A (en) * | 2004-03-23 | 2005-10-06 | Sumitomo Bakelite Co Ltd | Method for producing circuit board |
| JP2008028337A (en) * | 2006-07-25 | 2008-02-07 | Shinko Electric Ind Co Ltd | Manufacturing method of electronic parts |
| KR100826113B1 (en) * | 2006-09-28 | 2008-04-29 | 삼성전기주식회사 | Printed Circuit Board and Manufacturing Method |
| JP2020017712A (en) * | 2018-07-26 | 2020-01-30 | 健鼎（無錫）電子有限公司Ｔｒｉｐｏｄ （ＷＵＸＩ） Ｅｌｅｃｔｒｏｎｉｃ Ｃｏ．， Ｌｔｄ． | Method of manufacturing circuit substrate structure |
-
1992
- 1992-03-03 JP JP4555192A patent/JPH05243730A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000080496A (en) * | 1998-09-03 | 2000-03-21 | Ebara Corp | Filling plating method for base material having fine holes and / or fine grooves |
| JPWO2003030602A1 (en) * | 2001-09-28 | 2005-01-20 | 凸版印刷株式会社 | Multilayer circuit wiring board, IC package, and method for manufacturing multilayer circuit wiring board |
| US7584535B2 (en) | 2001-09-28 | 2009-09-08 | Toppan Printing Co., Ltd. | Method of manufacturing multi-layer wiring board |
| KR20030080413A (en) * | 2002-04-08 | 2003-10-17 | 주식회사 심텍 | The electroplating method of micro via hole for the use of multiple layers printed circuit board using step current density |
| JP2003318544A (en) * | 2002-04-22 | 2003-11-07 | Toppan Printing Co Ltd | Multilayer wiring board and method of manufacturing the same |
| JP2004190073A (en) * | 2002-12-10 | 2004-07-08 | Toppan Printing Co Ltd | Structure-graded copper foil, method for producing the same, etching method, copper foil pattern, storage method |
| JP2004197228A (en) * | 2004-03-17 | 2004-07-15 | Ebara Corp | Filling plating method for base material having fine holes and / or fine grooves |
| JP2005272874A (en) * | 2004-03-23 | 2005-10-06 | Sumitomo Bakelite Co Ltd | Method for producing circuit board |
| JP2005256178A (en) * | 2005-05-18 | 2005-09-22 | Ebara Corp | Method for hole-filling plating of substrate having fine holes and / or fine grooves |
| JP2008028337A (en) * | 2006-07-25 | 2008-02-07 | Shinko Electric Ind Co Ltd | Manufacturing method of electronic parts |
| KR100826113B1 (en) * | 2006-09-28 | 2008-04-29 | 삼성전기주식회사 | Printed Circuit Board and Manufacturing Method |
| JP2020017712A (en) * | 2018-07-26 | 2020-01-30 | 健鼎（無錫）電子有限公司Ｔｒｉｐｏｄ （ＷＵＸＩ） Ｅｌｅｃｔｒｏｎｉｃ Ｃｏ．， Ｌｔｄ． | Method of manufacturing circuit substrate structure |
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