JPH05250066A - Programmable clock synthesizing circuit - Google Patents

Abstract

PURPOSE:To generate a clock signal having an arbitrary duty ratio from a frequency higher than a basic clock frequency to a lower frequency. CONSTITUTION:This circuit is provided with a control register 5 to store the frequency of the desired clock signal to be outputted and the value of the duty ratio and to output that value, data conversion part 6 to convert the output of the control register 5 into a prescribed bit sequence and to output it, and memory part 4 to store the output of the data conversion part 6 and to store it from the inputted address value to an M-th address. Synchronously to the output signal of a basic clock oscillator 1, data from the address to the M-th address in the memory part 4 designated by an address counter 2 to output the address value are read by a data serializer 7A or 7B designated by a serializer control signal alternately designated by a serializer control circuit 16, and the clock signal is outputted synchronously to the output of a synchronizing signal oscillator 18 from the data serializer 7A or 7B designated by an output control signal generator 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable clock synthesizer circuit, and more particularly to a programmable clock synthesizer circuit for generating a clock signal for an information processing device such as a personal computer.

[0002]

2. Description of the Related Art A conventional programmable clock synthesis circuit has, for example, a basic clock oscillator 1 for generating and outputting a basic clock signal and an internal voltage control oscillator, as shown in FIG. PLL that outputs a signal synchronized with the phase of the basic clock signal
Circuit 8 and control register 10 for storing a setting signal input from the outside and outputting a selection signal according to the setting signal
And a clock selector 9 which outputs the frequency of the output signal of the PLL circuit as a clock signal of a frequency obtained by dividing the frequency by the integer value corresponding to the selection signal, and the basic clock signal is converted into a desired frequency by the clock selector 9. And is used as a clock signal.

[0003]

The conventional programmable clock synthesis circuit described above is a clock signal having the same frequency as the basic clock signal output from the basic clock oscillator 1 or a frequency value of the basic clock signal which is not 1. Only a clock signal whose frequency is the value divided by a numerical value can be output, and the duty ratio, that is, the time when the signal level is high for the entire time during one period The ratio is the PLL circuit 8
However, it has the drawback that it cannot be made variable.

An object of the present invention is to provide a programmable clock synthesizing circuit which can obtain a clock frequency higher than the basic clock frequency and can make the duty ratio of the clock signal variable.

[0005]

A programmable clock synthesizing circuit according to the present invention inputs a control register for storing and outputting a frequency of a clock signal to be generated and a duty ratio thereof to be generated inputted from the outside, and an output of the control register. And a data conversion unit for converting into a bit string composed of S elements predetermined according to the duty ratio and the frequency designated as, and an output corresponding to the designated address signal by temporarily storing the output of the data conversion unit. To the M-th address, which is a value obtained by dividing the number S of elements of the bit string output from the data conversion unit by a predetermined integer value, the address strobe signal is added as a frequency data string. The memory unit that outputs the frequency data string and the frequency data string when the first serializer control signal is added. First output as converted to a clock signal to a serial number in synchronism with the frequency data stream synchronization signal the storage when the first output control signal is applied
Data serializer and a second serializer control signal is applied to store the frequency data string, and a second output control signal is applied to convert the stored frequency data string into a serial value synchronized with the synchronization signal. A second data serializer for converting and outputting as a clock signal; a basic clock oscillator for generating and outputting a basic clock signal; a synchronizing signal oscillator for generating and outputting the synchronizing signal having a frequency M times that of the basic oscillator; An address counter that counts the number of repetitions of the waveform of the basic clock oscillator, outputs the value as an address signal, and resets the value when the count reaches a predetermined number S / M, and the basic clock signal Of the address signal and a predetermined length after the address signal. A memory controller that outputs a strobe signal, a serializer control circuit that outputs the first and second serializer control signals alternately in synchronization with the basic clock signal, and a second serializer control signal that synchronizes with the basic clock signal Is output, the output control signal generator alternately outputs the first output control signal and the second output control signal when the first serializer control signal is output. Has been done.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a programmable clock synthesis circuit of the present invention, and FIG. 2 is a block diagram of FIG.
FIG. 3A is a timing chart showing the operation of the programmable clock synthesis circuit shown in FIG. 3, and FIG. 3A is an explanatory diagram showing the stored contents of the control register 5 shown in FIG.
3B is an explanatory diagram showing the contents of the data conversion unit 6 shown in FIG. 1, and FIG. 3C is an explanatory diagram showing the stored contents of the memory unit 4 shown in FIG. is there.

As shown in FIG. 1, the programmable clock synthesizing circuit of the present embodiment stores a frequency of a clock signal to be output by the clock synthesizing circuit input from the outside and a control register 5 for storing and outputting the duty ratio thereof. When,
A data conversion unit 6 which receives the output of the control register 5 as an input and generates and outputs a predetermined number of bits having a frequency and a duty ratio specified in the output of the control register 5.
And a memory unit 4 that receives the output of the data conversion unit 6,
The data serializers 7A and 7B that store the frequency data string output from the data memory unit 4, convert it to serial data and output it as a clock signal, the basic clock oscillator 1 that outputs the basic clock signal, and the period of the basic clock signal are monitored. An address counter 2 that counts and outputs the count value to the memory unit 4 as an address signal, and a basic clock signal as an input, and an address strobe signal at a predetermined timing with respect to the memory unit 4 for each cycle of the basic clock signal. A memory controller 3 for outputting a serial clock signal, a serializer control circuit 16 for inputting a basic clock signal and alternately outputting a serializer control signal to the data serializers 7A and 7B at a predetermined timing for each cycle of the basic clock signal; With a clock signal as input, Output control signal for outputting the output control signal to the data serializer 7A or 7B alternately and at a predetermined timing in synchronization with the data serializer 7A or 7B to which the above-mentioned serializer control signal is not output. It comprises a generator 17 and a sync signal oscillator 18 which outputs a sync signal having a frequency N (N is an integer) times the frequency of the basic clock signal.

Now, the oscillation frequency of the synchronizing signal oscillator 18 is set to M (M is an integer) times the oscillation frequency of the basic clock oscillator 1, and when the count value of the address counter 2 becomes N, the value is reset and new. Set to start the cout from 1. Further, the output of the data conversion unit 6 is assumed to consist of S (S is an integer) bit strings, and M · N
The data conversion unit 6 outputs the value so that it becomes an integral multiple of S. The memory unit 4 is assumed to have a storage capacity for exactly storing the S bit strings.

First, the frequency of a clock signal to be output from the data serializers 7A and 7B and its duty ratio are input to the control register 5 from the outside. If the input value is, for example, a frequency of 10 MHz and the duty ratio is 50%, the control register 5 displays the frequency and the duty ratio as shown in FIG. 3 (A), for example. Is stored and the value is output to the data conversion unit 6. The data converter 6 converts the input value into a bit string as shown in FIG. 3B, that is, the frequency and duty ratio input to the control register 5 by the synchronization signal output from the synchronization signal oscillator 18. The clock signal is converted into a value having a period such that the clock signal is output from the serializers 7A and 7B and the total number of bits is S, and the value is output to the memory unit 4 and stored therein.

FIG. 3C shows the contents of the data stored in the memory unit 4, in which the data input from the data conversion unit 6 is stored in a storage area composed of N · M = S addresses. It shows the state of being. That is, the output data of the data conversion unit 6 starts from the storage area at the upper left corner of FIG. 3C and is sequentially stored in the horizontal direction. When the Mth storage area is stored, the data that follows is immediately below the upper left corner. Of N is stored in the portion of 2 and is sequentially stored from there to the right. In this way, the last data is stored in the storage area at the lower right corner.

In order to output the desired clock signal in this way, the control register 5 and the data conversion unit 6 store the desired data in the memory unit 4 in advance.

When the basic clock signal 11 is output from the basic clock oscillator 1 as shown in FIG. 2, the address counter 2 counts the value N of the number of repetitions of the basic clock signal 11 and outputs the count value N as the address signal 12. Is output to the memory unit 4. The address counter 2 increments its count value by 1 every repetition cycle of the basic clock signal 11, outputs the value whose count value becomes N, resets the count value, and recounts the count value from 1. Set to.

The address strobe signal 13 is output from the memory controller 3 to the memory section 4 in synchronization with the basic clock signal 11 every cycle of the basic clock signal 11 described above. When the level of the address strobe signal is low, the address unit 4 frequency-converts M storage areas starting from the address value specified by the address signal 12, that is, one row of data shown in FIG. The data string 14 is output to the data serializers 7A and 7B.

The serializer control circuit 16 and the output control signal generator 17 respectively output the serializer control signal and the output control signal in synchronization with the basic clock signal 11. The serializer control signal is alternately output to the data serializers 7A and 7B. Also, the output control signal is output alternately to the data serializers 7A and 7B and to either the data serializer 7A or 7B to which the serializer control signal is not added.

Here, the serializer control circuit 16 outputs the first serializer control signal to the data serializer 7.
The serializer control circuit 16 is set to output to A, and the output control signal generator 17 is set to output the first output control signal to the data serializer 7B.

When the output level of these serializer control signals becomes low level, for example, the data serializer reads and stores the data output from the memory section 4, and when the output control signal becomes low level. The data stored internally from the data serializer is serially synchronized with the output signal of the synchronization signal oscillator 18 and the memory unit 4
These data serializers 7A and 7B are arranged so as to serially output the address values of the data stored in
And are set.

Since the outputs of the data serializers 7A and 7B are connected in parallel as shown in FIG. 1, the data serializers 7A and 7B are synchronized with the sync signal output from the sync signal oscillator 18. The clock signal 15 will be output.

Therefore, the duty ratio is set to an arbitrary value with a frequency higher than the frequency of the basic clock signal output from the basic clock oscillator 1 and lower than the frequency of the synchronous signal output from the synchronous signal oscillator 18. The signal can be output to the outside.

As is clear from the above description, if the ratio of the frequency of the sync signal output from the sync signal oscillator 18 to the basic clock frequency 11 is increased, the frequency and duty ratio of the clock signal can be made wider. And can be changed minutely.

[0021]

As described above, in the programmable clock synthesis circuit of the present invention, the frequency and duty ratio of the clock signal to be output to the control register 5 are input from the outside, and the control register 5 is controlled. The output is converted by the data conversion unit 6 into data having a desired bit string, stored in the memory unit 4, and synchronized with the basic clock signal 11 output from the basic clock oscillator 1 to start the first address to be called by the address counter 2. Is output, and the output of the memory controller 3 causes both the data serializers 7A and 7B to output M bit strings starting from the designated address value in the memory unit 4. Since the clock signal is output in synchronization with the output signal of the synchronization signal oscillator 18 having a frequency higher than that of the basic clock signal 11, the clock having a frequency higher than that of the basic clock signal 11 and the duty ratio changed It has an effect that a signal can be output.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a programmable clock synthesizer circuit of the present invention.

FIG. 2 is a timing chart for explaining the operation of the programmable clock synthesis circuit of this embodiment.

3 is an explanatory diagram showing data contents of a control register 5, a data conversion unit 6, and a memory unit 4 shown in FIG.

FIG. 4 is a block diagram showing an example of a conventional programmable clock synthesis circuit of this type.

[Explanation of symbols]

 1 Basic Clock Oscillator 2 Address Counter 3 Memory Controller 4 Memory Section 7A Data Serializer 7B Data Serializer 16 Serializer Control Circuit 17 Output Control Signal Generator 18 Synchronous Signal Oscillator

Claims (1)

[Claims] 1. A control register for storing and outputting a frequency of a clock signal to be generated and a duty ratio of the clock signal input from the outside, and a control register which is predetermined according to a duty ratio and a frequency designated by an output of the control register as an input. And a data conversion unit for converting into a bit string composed of S elements, and the output of the data conversion unit is temporarily stored and the number of elements S of the bit string output from the data conversion unit from the address corresponding to the designated address signal. A value stored in a range up to the M-th address, which is a value obtained by dividing the value by a predetermined integer value, as a frequency data string, and is output when an address strobe signal is added;
When the serializer control signal is applied, the frequency data sequence is stored, and when the first output control signal is applied, the stored frequency data sequence is converted into a serial value in synchronization with a synchronization signal and output as a clock signal. A first data serializer and a serializer that stores the frequency data string when a second serializer control signal is applied, and stores the frequency data string when the second output control signal is applied, in synchronization with the synchronization signal. A second data serializer for converting into a value and outputting as a clock signal, a basic clock oscillator for generating and outputting a basic clock signal, and a synchronizing signal oscillator for generating and outputting the synchronizing signal having a frequency M times that of the basic oscillator And counting the number of repetitions of the waveform of the basic clock oscillator and outputting the value as an address signal. S quantity G is a predetermined number of times
Address counter that resets the value when / M is reached, and a memory controller that outputs the address strobe signal of a predetermined length after a predetermined time from the address signal in synchronization with the basic clock signal. A serializer control circuit that alternately outputs the first and second serializer control signals in synchronization with the basic clock signal; and a serializer control circuit that outputs the second serializer control signal in synchronization with the basic clock signal. 1
And an output control signal generator that alternately outputs the second output control signal when the first serializer control signal is being output.