JPH05250314A - Information processor - Google Patents

Abstract

PURPOSE:To provide an information processor which simplifies and speeds up the arbitration of an extended input/output bus at the time of making access from an arithmetic processor to an input/output device. CONSTITUTION:Extended bus adapters 21, 22, and 23 for which the information processor having basic input/output buses 1, 2, and 3 and one extended input/ output bus 4 is equipped with so as to connect two input/output buses are provided with flags 31, 32, and 33 which indicate whether or not the extended input/output bus 4 is in use internally as extended input/output bus utilization arbitrating means. Further, an extended input/output bus utilization arbitration signal 34 can be outputted and the flag in another extended bus adapter can be changed. When the arithmetic processor 5 makes access to the input/output device 4, the extended bus adapter 21 checks the flag 31 to facilitate and speed up the arbitration of the extended input/output bus 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in which a plurality of basic input / output buses commonly use one additional input / output bus via an additional bus adapter, and in particular each additional bus adapter uses an additional input / output bus. The present invention relates to an information processing device having arbitration means.

[0002]

2. Description of the Related Art In a conventional information processing apparatus, as shown in the block diagram of FIG. 2, for example, an arithmetic processing unit 5 on a basic input / output bus 1 is activated for an input / output device 14 on an expanded input / output bus 4. When the instruction is applied, the instruction reaches the additional input / output bus arbitration circuit 51 via the additional bus adapter 41, and it is determined whether the additional input / output bus 4 is in use, and a response is returned to the arithmetic processing unit 5. Was becoming.

[0003]

The above-described conventional information processing apparatus uses the additional input / output bus when the instruction from the arithmetic processing unit uses the input / output device on the additional input / output bus through the additional bus adapter. To get it, I had to go through an additional I / O bus arbitration circuit separately. Therefore, it takes time to start the additional input / output bus arbitration circuit.

An object of the present invention is to provide an information processing apparatus capable of simplifying arbitration of an additional input / output bus when accessing an input / output device from an arithmetic processing device and increasing the speed.

[0005]

An information processing apparatus of the present invention has a plurality of basic input / output buses, and an arithmetic processing unit, a main storage device, and a plurality of input / output devices are provided on each of the basic input / output buses. In an information processing device having an expansion bus adapter for providing an expansion input / output bus and having a plurality of input / output devices on the expansion input / output bus, each expansion bus adapter has an expansion input / output bus use arbitration means. It is the structure which has.

The information processing apparatus of the present invention outputs a flag indicating whether the input / output bus is used for the additional input / output bus use arbitration means and an additional input / output bus use arbitration signal to all the additional bus adapters. By providing a function, it is desired to use the additional input / output bus when the arithmetic processing device on the plurality of basic input / output buses exchanges information with the input / output device on the additional input / output bus. Check if the expansion bus adapter connected to the device is flagged.If it is not flagged, return an acceptance response to the relevant processing unit and set a flag for the expansion bus adapter. When the extension I / O bus is used after the arbitration signal is output by using the extension I / O bus and the extension I / O bus has been used, the above flag is cleared and the bus cycle is terminated, and the flag is set. It may return a rejection response to the processing unit of the corresponding.

[0007]

According to the present invention, each additional bus adapter connected to the basic input / output bus is provided with additional input / output bus use arbitration means, and whether each additional input / output bus use arbitration means uses the additional input / output bus. By adding a flag indicating whether or not the arithmetic processing unit on the basic I / O bus accesses the I / O device on the expansion I / O bus, whether the expansion I / O bus is in use at the expansion bus adapter Therefore, arbitration of the additional input / output bus can be simplified and the speed can be increased.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

1, 2, 3 are basic input / output buses, 4 are additional input / output buses, 5, 6, 7 are arithmetic processing units, 8, 9, 10 are main storage units, 11, 12, 13, 14, 15 , 16 are input / output devices, 21, 22, 23 are additional bus adapters, 3
Reference numerals 1, 32 and 33 are flags indicating whether or not the additional input / output bus 4 is in use, and 34 is an additional input / output bus use arbitration signal.
Further, the extension bus adapters 21, 22, 23 are provided with flags 31, 32, 3 indicating whether or not the extension input / output bus 4 is in use.
I have 3. In addition, the additional input / output bus use arbitration signal 34
Is a signal for connecting the respective extension bus adapters 21, 22, 23, and flags 31 and 3 are generated by this signal.
2, 33 changes.

Next, the operation will be described.

For example, when the arithmetic processing unit 5 on the basic input / output bus 1 activates the input / output device 14 on the extension input / output bus 4, the instruction is sent to the extension bus adapter 21 and is incorporated therein. The case where the flag 31 in the existing additional input / output bus use arbitration means is reset, that is, the case where the additional input / output bus 4 is not used will be described.

First, an acceptance response is returned to the arithmetic processing unit 5, the flag 31 is set, the additional input / output bus use arbitration signal 34 is output, and all the flags in the system are set. As a result, the arithmetic processing unit 5 has acquired the additional input / output bus 4, and exchanges information with the input / output unit 14. When the arithmetic processing unit 5 finishes transferring the information, it resets the flag 31, outputs the additional input / output bus use arbitration signal 34, resets all the remaining flags 32 and 33 in the system, and adds the additional input / output bus 4. Inform you that you have released the.

On the contrary, when the processor 5 on the basic input / output bus 1 activates the input / output device 14 on the additional input / output bus 4, when the instruction is sent to the additional bus adapter 21, the additional input is added. When the flag 31 in the output bus use arbitration means is set, that is, when the additional input / output bus 4 is in use, the additional bus adapter 21 is connected to the arithmetic processing unit 5.
Returns a rejection response to.

[0015]

As described above, according to the present invention, the extension bus adapter incorporates the extension I / O bus use arbitration means, and further has therein a flag indicating whether or not the extension I / O bus is in use. When the expansion adapter outputs an expansion input / output bus use arbitration signal when the input / output device is used, the expansion can be performed when the arithmetic processing unit on the basic input / output bus issues a command to the input / output device on the expansion input / output bus. There is an effect that the arbitration of the input / output bus can be simplified and the speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional information processing device.

[Explanation of symbols]

1,2,3 Basic input / output bus 4 Expansion input / output bus 5,6,7 Arithmetic processing unit 8,9,10 Main storage device 11,12,13 14,15,16 Input / output device 21,22,23 Expansion bus Adapter 31, 32, 33 Flag that indicates whether the extension I / O bus is in use 34 Extension arbitration bus use arbitration signal

Claims (2)

[Claims] 1. An expansion bus adapter for providing a plurality of basic input / output buses, and providing an arithmetic processing unit, a main storage device, a plurality of input / output devices, and an expansion input / output bus on each of the basic input / output buses. And an information processing device having a plurality of input / output devices on the additional input / output bus, each of the additional bus adapters having an additional input / output bus use arbitration means. 2. The extension I / O bus use arbitration means is provided with a flag indicating whether or not the I / O bus is used and a function of outputting an extension I / O bus use arbitration signal to all extension bus adapters. , An arithmetic processing unit on a plurality of basic input / output buses is connected to an arithmetic processing unit that wants to use the additional input / output bus when exchanging information with the input / output device on the additional input / output bus. Check whether or not the flag is set on the expansion bus adapter. If the flag is not set, send an acceptance response to the relevant processing unit, set a flag on the expansion bus adapter and use the expansion input / output bus. After outputting the arbitration signal, use the additional input / output bus. After the use of the additional input / output bus is finished, the above flag is cleared and the bus cycle is finished. The information processing apparatus according to claim 1, which returns a rejection response.