JPH01134653A - Priority control system for common bus - Google Patents

Abstract

PURPOSE:To change a priority even when a system is operated by controlling the contents of the internal registers of respective bus masters freely changeably through a busmaster having the highest priority in the system in which plural bus masters are connected to a common bus. CONSTITUTION:To a common bus 10, correspondingly to respective plural microprocessors, bus masters 8-0-8-N are connected, to which internal registers 6 are also provided besides bus requesting signal selecting circuits 4, bus priority signal selecting circuits 5, and bus arbitrating circuits 7. Thereafter, for example, when the content of the register 6 of a bus master 8-0 is set correspondingly to the highest priority at the time when the system is risen with the bus master 8-0, the value is still held even when the system is operated after the power is turned on, and the bus master 8-0 freely writes the contents of the internal registers of the other bus masters 8-1-8-N according to their priorities which are respectively different through a data signal line 1 of the bus 10. As the result, the priority can be changed desirably even when the system is operated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a system consisting of a microprocessor.
This paper relates to a bus arbitration method for a shared bus in a system consisting of multiple microprocessors.

(Prior Art) Conventionally, the priority of bus requests for this type of shared bus has been fixedly determined by a deep switch on the bus master board or the backboard of the unit. Request priority could not be changed.

(Problems to be Solved by the Invention) In the prior art shared bus priority control method described above, the priority of bus requests for the shared bus is determined when the power is turned on, and the priority cannot be changed while the system is running. I'm afraid the drawback is that it cannot be done.

An object of the present invention is to, in a system in which a plurality of bus masters are connected to a shared bus, transmit a bus request signal from bus arbitration to the bus request signal line of the shared bus corresponding to the contents of all internal registers to each bus master; A shared bus priority signal corresponding to the contents of an internal register is given as a bus priority signal for bus arbitration, and the contents of the internal register are set at the time of system startup so that the bus request for all shared buses is in the highest state. Is the content of the other bus master's internal registers retaining that value? Rewriting via shared bus data signal line, priority of each bus master? The object of the present invention is to provide an entire shared bus priority control method that eliminates the above-mentioned drawbacks by controlling the priority order and allows the priority order to be changed even during system operation.

(Ninth Means to Solve All Problems) The shared bus priority control system according to the present invention includes a plurality of bus masters and a shared bus consisting of a data signal line, a bus request signal line, and a bus priority signal line. Each bus master includes a bus request signal selection circuit, a bus priority signal selection circuit, an internal register, and a bus arbitration circuit.

The bus request signal selection circuit is for inputting and outputting bus request signals to and from the bus request signal line of the all-shared bus.

The bus priority signal selection circuit is for inputting/outputting a shared bus priority signal corresponding to the priority to/from all bus priority signal lines.

The internal register is used to set all nine contents corresponding to the bus request signal and the bus priority signal.

The bus arbitration circuit sets the contents of the internal register register so that the bus request for all shared buses is at its highest level when the system is started up, and while the system is running, it retains all the values set above and uses the internal registers of other bus masters. This is the tth system that rewrites the contents of the data via the data signal line of the shared bus and controls the priority order.

(Example) Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a boot diagram showing an embodiment of a shared bus priority control method according to the present invention.

In FIG. 1, 10 is a shared bus, 1 is a data signal line of the shared bus 10, and 2 is a bus request signal line of the shared bus 10.
3 is a bus priority signal line of the shared bus 10, 4 is a bus request signal selection circuit, 5U bus priority signal selection circuit, 6Fi internal register, 7 is a bus arbitration circuit, and 8-0.8-N are bus masters, respectively. .

The shared bus 10 includes a data signal line 1, a bus request signal line 2, and a bus priority signal line 3.

The bus masters 8-0.8-N have the same configuration, and the bus mask 8-0 includes a bus request signal selection circuit 4 and a bus priority signal selection circuit 5.

It has an internal register 6 and a bus arbitration circuit 7.

For example, when the bus master 8-0 starts up the system, the contents of the internal register 6 are set to a value that makes the shared bus 10's bus request the highest, and this value is held while the system is running. The bus master s-o writes values representing different priority values to the internal registers of other bus masters through all the data signal lines 1 of the shared bus 10. The bus request signal selection circuit 5 of the bus master 8-0 selects the bus request signal line 2t corresponding to the value of the internal register 6.
- Connected to the bus request signal line 2 of the bus 10 (shared from the bus arbitration circuit 7).

Among the bus priority signal lines 3 of the shared bus 10, the bus priority signal lines of the shared bus 10 corresponding to the internal registers are connected to bus priority input signal lines of the bus arbitration circuit 7. By rewriting the contents of the internal registers of other bus masks during system operation, the bus master 8-0 can completely change the bus request priority of the shared bus 10 of the bus master.

(Effects of the Invention) As described above, the present invention provides a system in which a plurality of bus masters are connected to a shared bus.

Each bus master sends the bus request signal from bus arbitration to the bus request signal line of the shared bus corresponding to the contents of the internal register, and uses the shared bus priority signal corresponding to the contents of the internal register as the bus priority signal for bus arbitration. Set the internal register contents at system startup so that the shared bus has the highest bus demand, hold that value while the system is running, and set the contents of the internal registers of other bus masters so that the shared bus has the highest bus demand. By controlling the priority order of each bus master by rewriting via the data signal line of the bus mask, there is an effect that the bus request priority order of the shared bus of the bus mask can be changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a shared bus priority control system according to the present invention. 1 to 3... Signal line 4... Bus request signal selection circuit 5... Bus priority signal selection circuit 6... Internal register 7... Bus arbitration circuit 8... Bus master 10... Shared Bus patent applicant NEC Corporation

Claims (1)

[Claims] Multiple bus masters, data signal lines, bus request signal lines,
and a shared bus consisting of a bus priority signal line, wherein each bus master inputs/outputs a bus request signal to/from a bus request signal line of the shared bus. a selection circuit; a bus priority signal selection circuit for inputting and outputting a shared bus priority signal corresponding to the priority to the bus priority signal line; and a bus priority signal selection circuit for inputting and outputting a shared bus priority signal corresponding to the priority to the bus priority signal line; an internal register to be set, and the contents of the internal register are set at the time of system startup so that the bus request for the shared bus is in the highest state, and the set value is maintained while the system is running. and a bus arbitration circuit for rewriting the contents of internal registers of other bus masters via the data signal line of the shared bus and controlling the priority order of the shared bus. control method.