JPH0525143B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device for performing linear transformation such as enlargement, reduction, rotation, etc. of image data.

[Conventional technology]

As shown in Figure 2, linear transformation of image data formed by multiple pixels is a transformed image in which the source image ("A" indicated by a solid line in the figure) is moved, enlarged, reduced, or rotated. (“A” indicated by a broken line in the figure). In Figure 1,
A shows movement, B shows enlargement, C shows rotation, and D shows an example of a general linear transformation that combines movement, enlargement, and rotation.

These linear transformations are defined by equation (1), where the coordinates on the source image are (X, Y) and the coordinates on the transformed image corresponding to (X, Y) are (x, y). .

x y=PQ RSX-Xo Y-Yo+xo yo...(1) Here, P, Q, R, S are conversion coefficients, Xo, Yo
is the origin coordinate of the source image, and xo and yo are the translation amounts of the converted image.

Conventional equipment that performs this linear transformation has a method of sequentially transferring each pixel on the source image to the (x, y) position on the transformed image calculated from the coordinates (X, Y) of that pixel using equation (1). There was a thing called
229669). In addition, in another conventional device, the inverse matrix of the transformation matrix of equation (1) is obtained, and from the coordinates (x, y) of the lattice point on the transformed image obtained in advance from equation (1),
The coordinates (X, Y) on the corresponding source image are determined from the above inverse matrix, and the pixel data determined by some means from (X, Y) or the surrounding pixel data is used as the pixel at (x, y). data (see Japanese Patent Application Laid-Open No. 56-76683).

[Problem that the invention seeks to solve]

In the case of the first conventional device described above, the coordinates (x, y) of the grid point on the converted image are calculated and rounded to the coordinates of the grid point closest to the coordinates (x, y), so all the grid points on the converted image are There was a problem that it could not be generated. On the other hand, in the case of the second conventional device described above, pixel data of the corresponding source image is obtained from the grid point coordinates on the converted image, so unlike the first conventional device, missing pixels on the converted image do not occur. . However, since the source images are accessed randomly, if the source images are captured sequentially, i.e. for faster speeds,
When a configuration is adopted in which source images are transferred in a fixed order by a DMA controller or the like via a FIFO register, the efficiency is extremely low and high speed cannot be achieved.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus that can capture source image data at high speed and performs linear transformation processing so that no pixel of the transformed image is lost.

[Means for solving problems]

The purpose of the above is to convert the coordinate string of the grid points that constitute the straight line on the transformed image corresponding to one line on the source image into 2 A first digital differential analyzer (hereinafter abbreviated as DDA) for interpolating and sequentially generating points so as to connect them in a 4-connection or 8-connection mode, and the number of pixel data included in a line on a source image. Based on the number of pixels on the converted image corresponding to this line, the readout signal of the source image and the pixel data readout thereby are converted into the first
A second DDA that generates a write signal for writing to the coordinates generated by the DDA constitutes an image conversion means that converts the source image line by line. The connection mode between the coordinates of corresponding points on each converted image of the starting point of the line is set to 4 connection mode when the interpolation between two points by the first DDA is 8 connection mode, and the above interpolation is 4 connection mode. This is achieved by providing a starting point generating means that generates each starting point so that when the connected mode is in the 8 connected mode. However, 4-connection means that two lattice points are adjacent to each other in any of the directions a to d, as shown in Figure 3A, and 8-connection means that two lattice points are adjacent to each other in any of the directions a to d, as shown in Figure 3B. It is said that the two lattice points are adjacent in any of the eight directions a to h.

[Effect]

DDA is the second edition of "Principles of Interactive Computer Graphics", published by McGraw-Hill, 1979, pages 21 to 27 ("PRINCIPLES OF INTERACTIVE").
COMPUTER GRAPHICS”Second Edition,
McGRAW−HILL KOGAKUSHA, LTD.PP21
-27) is described in detail. For this operation, assume that the slope of a straight line on a two-dimensional plane (x, y) with an arbitrary slope and the coordinates of the starting point and ending point are given. If the longer one of the x and y components of the straight line is x and the shorter one is y, then when x is changed by 1 along the straight line, the value of y will change in steps smaller than 1 depending on the slope of the straight line. variable and generally not an integer value. Therefore, DDA converts this y value into a rounded integer value and outputs it as integer coordinates (x, y), and has the function of approximating and outputting a straight line using grid points (points with integer coordinates). be. So the first
In DDA, coordinates of grid points are generated to connect each line on the converted image with 8/4 connection, and the second
Using the above function, DDA realizes control to redundantly allocate the smaller number of pixels to the line with the larger number of pixels on the source side and the line on the converted image side. Furthermore, by using the starting point generation means, the distance between the starting points is 4/8.
Since they are connected, there is a 4/8 connection between the starting points of each line on the converted image, and an 8/4 connection within each line, so that data is always provided to all pixels on the converted image. Moreover, the operations by these two DDAs operate sequentially along the line to generate coordinates and control data writing there, and the order of data extracted from the source image remains the same as the line order of the source image. This allows the use of FIFO registers and enables high-speed processing.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

(Configuration of Embodiment) FIG. 4 shows the overall configuration of the image processing device of the present invention, in which the CPU 1 reads pixel data on the source image from the main memory 2 that stores the source image, and connects the bus 3. Write to FIFO register 4 via

The image conversion device 5 receives parameters such as the size of the source image, the size and position of the converted image, which will be described later, from the CPU 1 via the bus 3, and is further started to execute the conversion process. In order to read pixel data, a read signal 54 is sent to the FIFO register 4, and read data 45 is sent to the FIFO register 4.
receive. Furthermore, the pixel data on the received source image is written onto the frame memory 6 via the signal line 56 as a converted image.

The frame memory 6 is a storage device that stores image data to be displayed on the display 7, and its contents are constantly read out and sent to the display 7.
Is displayed. This display mechanism is not related to the present invention, so a description thereof will be omitted.

Now, the pixel data on the source image stored in the main memory 2 can be input to the FIFO register 4 in any order by the CPU 1, but below, for simplicity, we will explain the coordinates (X, Y) of the pixel data of the source image. ) are rectangular coordinates, and are grid points where both X and Y are integer values, and the order of pixels sent to the FIFO register 4 is determined by the CPU 1 using the given source image by means described later. Among those with Y coordinates, increase the X coordinate by one starting from the pixel on the grid point with the minimum X coordinate,
It is assumed that one line of pixel data is transmitted in the order of pixels on the grid point with the maximum X coordinate.

FIG. 1 shows an image conversion device 5 that is a feature of the present invention.
In this example, the sequence control circuit 504 operates according to the activation signal from the CPU 1.
An initial FIFO register read signal 508, a conversion start signal 507, and a conversion execution signal 505 are generated. The X counter 502 and the Y counter 503 hold the coordinates of pixels to be written on the converted image as their count values. DDA8 is the X counter 502,
Generates a signal for updating the Y counter 503,
The DDA 9 generates a read signal 54 to the FIFO register 4 and a write signal 506 to the frame memory 6. Direction register 501 is DDA8, DDA
9, holds signals for controlling the X counter 502 and Y counter 503. To these circuits, the CPU
1 can set any value via bus 3.

The internal configuration of DDA8 and DDA9 is the same,
An example of its configuration is shown in FIG. In the figure, the slope register 102 is a register that holds a value of 1 or less, and the value is set from the CPU 1 via the bus 3 and the terminal BIN. The error register 101 is a register that holds a value smaller than 1, and when an enable signal is applied to the EBL terminal, the S terminal output value of the adder 104 is set. The selector 103 is
When the conversion start signal 507 from the INIT terminal does not indicate the start of conversion (when the level is "φ"), the contents of the error register 101 are selected, and the conversion start signal 507
When 7 is starting to convert (when the level is “1”)
Select 0.5 and output. The adder 104 adds the output of the selector 103 and the contents of the slope register 102, sends the fractional part of the addition result to the S terminal (this is set in the register 101 by an enable signal), and sends the fractional part to the C terminal. Outputs the integer part (carry signal) of the addition result. This latter carry signal is input to OR gates 105 and 106. The other input of the OR gate 105 is
The control signal from the DIR terminal is applied via the not gate 107, and the control signal is input to the other input of the OR gate 106. When the control signal is "0", the OR gate 105 outputs even if there is no carry signal. 1, and when the control signal is "1", the OR gate 106 output is set to 1 even if there is no carry signal.
shall be.

As shown in the above-mentioned literature, the DDA with the above configuration has an inclination of 45° or less (when the control signal is 0) or 45° or more (when the control signal is 1) in the first quadrant in the two-dimensional space. ) when given a vector (a straight line starting from the origin), the x coordinate on the vector is +
How much does the y-coordinate increase when it is 1 (integer increment)
It has a function to calculate the value, and each time it increases by +1, the value becomes
AND gates 108, 10 by enable signal
When 9 is open, outputs are output from the X _up and Y _up terminals. In the case of vectors in the second to fourth quadrants, the values of the X and Y terminals of the direction register 501 in FIG. 1 determine whether the X counter 502 and Y counter 503 are set to up counter mode or down counter mode. This can be dealt with by controlling the

(Operation of the Embodiment) Next, a procedure for converting the source image on the main memory 2 and writing it into the frame memory 6 using the hardware described above will be described.

FIG. 6 is a diagram showing the relationship between a source image, which is an image to be converted, and a converted image. Main memory 2
, a rectangle 2 defined by grid points a, b, d, c on a two-dimensional space is created in order from a certain arbitrary address.
Pixel information on each grid point of 1 is stored along a vector 22 starting from grid point a up to grid point d. The image processing device shown in FIG.
Pixel information on the source image is mapped to all pixels included in 1. That is, the image conversion device 5 first converts a vector that is one horizontal line on the source image 21 to
Processing is performed to map pixel data included on 22 to pixels on a vector 62 connecting coordinates A to B on the transformed image. Every time the conversion process for one horizontal line is completed, the CPU 1 instructs the image conversion device 5 to process the next horizontal line, and thereby the vector cd on the source image is converted and the vector cd on the converted image is Processing continues until the image is copied to a CD.

Therefore, first, the conversion process for one horizontal line on the source image will be explained. Now, the number of pixels between grid points a and b of rectangle 21 is L, the number of pixels between grid points a and c is M, and the coordinates of grid points A, B, C, and D of parallelogram 61 (these coordinates are (x _A , y _A ),
Let (x _B , y _B ), (x _C , y _C ), (x _D , y _D ). CPU1
From these values, data is set in each register as follows to initialize the DDAs 8 and 9 shown in FIG.

(a) When |(x _B −x _A )|≧|(y _B −y _A )| (vector
62 is 45° or less) In the tilt register 102 of DDA8 | (y _B −y _A )
|/|(x _B −x _A )|≦1 is set, and the bit output to the L terminal of the direction register 501 is set to “0”.

When |(x _B −x _A )|<|(y _B −y _A )| (vector
62 exceeds 45°) In the tilt register 102 of DDA8 | (x _B −x _A )
|/|(y _B −y _A )|<1 is set, and the bit output to the L terminal of the direction register 501 is set to “1”.
Set.

(b) When x _B −x _A ≧0 (vector 62 is in the 1st and 4th quadrants) Set the bit output to the X terminal of the direction register 501 to “0”.

When x _B −x _A <0 (vector 62 is in the second and third quadrants), the bit output to the X terminal of direction register 501 is set to “1”.

When y _B −y _A ≧0 (vector 62 is in the first and second quadrants), the bit output to the Y terminal of the direction register 501 is set to “0”.

When y _B -y _A <0 (vector 62 is in the third and fourth quadrants), the bit output to the Y terminal of the direction register 501 is set to "1".

(c) x _A to X counter 502 y _A to Y counter 5
Set to 03.

(d) When α=MAX(｜x _B −x _A ｜, ｜y _B −y _A ｜)…(2), if L−1≦α, the reciprocal of the magnification rate is stored in the slope register 102 of DDA9. (L-1)/α is set, and the bit output to the S terminal of the direction register 501 is set to “0”. Here, α in (2) is the number of pixels of vector 62 on the converted image generated in 8-concatenation mode (this number of pixels is the distance of one line of the converted image, that is, the number of pixels that is the result of subtracting the starting point coordinates from the ending point coordinates). (The pixel at the starting point is an uncounted number.)

When L-1>α, set the reduction ratio α/(L-1) in the slope register 102 of DDA9, and set the direction register 5
The bit output to the S terminal of 01 is set to "1".

(e) To the counter in the sequence control circuit 504
Set MAX(L, α).

When the above DDA initial settings are completed, the CPU 1 sequentially reads out pixel data along the vector 22 from the main memory 2 and writes it to the FIFO register 4.
The image conversion device 5 is activated. However, register 4
When the number of words possessed by the vector 22 is smaller than the number of data for one line of the vector 22, the remaining portion after starting up the image conversion device 5 is transferred.

When the CPU 1 activates the image conversion device 5,
The startup register of the sequence control circuit 504 is accessed, thereby causing the sequence control circuit 5
04 is the read signal 50 at the first timing.
8, which is sent out as a read signal 54 via the OR gate 10. FIFO register 4
When it receives the read signal 54, it returns the first input data, that is, the pixel data corresponding to the grid point a of the source image, as the read data 45 at the next second timing.

At the next timing after activation, the sequence control circuit 504 turns off the initial read signal 508 and turns on the conversion start signal 507 and conversion execution signal 505 instead. By turning on both signals,
DDA starts working. Among these, the operation of DDA9 is as follows. If L-1≦α,
Figure 6 Vector 62 from the pixel data on vector 22
Since there is more pixel data on the top, it is necessary to use the same data on vector 22 multiple times to correspond to the pixels on vector 62. At this time, use the initial settings mentioned above.
Due to (d), the S terminal of the direction register 501 is “0”
Since this is input to the DIR terminal of the DDA 9, the output of the OR gate 105 in FIG. 5 is always 1, and since the conversion execution signal 505 is applied to the EBL terminal, X _up is always 1. on the other hand.
Y _up becomes 1 only when the adder 104 outputs a carry. This DDA9's X _up becomes the write signal WEBL to the frame memory 6 (converted image) as shown in Figure 1, and Y _up becomes the read signal for the next pixel data from the FIFO register 4, so in this case it is always Writing to the frame memory 6 is performed (X _up =1), and reading from the FIFO register 4 is performed only when the carry signal becomes 1. When the carry signal is 0, the data of the next source image is not read, and the previously read data is written as data on the frame memory 6, that is, the vector 62, the next time as well. In this way, the DDA 9 performs control to provide data to all pixels on the vector 62 using a small amount of data on the vector 22. Conversely, when L-1>α, the S terminal of the direction register is initially set to “1”, so this time
Y _up is always 1, vector 22 with a large number of pixels is always read from FIFO register 4, _and conversely
is only when the carry signal is 1. Writing to frame memory 6 is performed only at this time, and the carry signal is 0.
When , the data read from vector 22 is discarded. In this way, the DDA 9 controls giving more data on the vector 22 to the vector 62 with a smaller number of pixels.

On the other hand, when DDA9 outputs X _up = 1 and instructs writing to frame memory 6, DDA8 receives this signal to the EBL terminal and becomes enabled.
Outputs X _up and Y _up . This output is made by setting X _up or Y _up corresponding to the longer of the x and y components of vector 62 to 1 (setting the direction register L terminal) according to the initial settings (a) and (b) above. The shorter X _up or Y _up is 1 only when the carry signal is 1, and these
Counters 502 and 5 corresponding to X _up and Y _up
Update 03. Since the counters 502 and 503 are given the coordinates (x _A , y _A ) of point A by the initial setting (c), by updating the counters, the longer of the x and y components of the vector 62 is It is always updated by 1, and the shorter one is updated only when it is a carry 1, and the next address of point a of vector 62 is set. This is an operation of generating coordinates for interpolating between A and B in the 8-connection mode of the DDA8, and pixel data from the FIFO is involved in the generated coordinates under the control of the DDA9 described above.

When the reading/writing of one pixel data is completed in the above manner, the sequence control circuit 504 turns off the conversion start signal 507, and thereafter makes the selector 103 in each DDA 8, 9 select the contents of the error register 101, and also The value set in setting (e), that is, the number of images for one line processing, is decreased by 1 and the process proceeds to the next pixel conversion process.

By repeating the above operations, when the value of the built-in counter becomes 0, the control circuit 504 outputs the conversion execution signal 50.
5 is also turned off, and the conversion process for one line is completed.

When the above conversion process for one line is completed by starting the image conversion device 5 once, the CPU 1
instructs the image conversion device 5 to convert the second horizontal line, but at this time the vector 62 in FIG.
This is equivalent to changing the position of , so change the coordinates (x _A , y _A ) of the start point and end point, etc., and perform initial settings again. In this case, the starting point on the converted image corresponding to the second horizontal line and the horizontal line beyond it on the source image is on AC in Figure 6, but more precisely, it is a grid point close to the straight line AC (integer coordinates ) must be determined as the starting point, and this requires processing similar to generating grid points corresponding to vector 62 using two DDAs in 8-connection mode.

FIG. 7 is an enlarged version of the converted image 61 in FIG. 6, in which the first horizontal line 22 has been converted from the grid point corresponding to the pixel 63 in the direction of the vector 62 as described above. In this embodiment, the starting points in the conversion process after the second horizontal line of the source image are made up of grid points connected in a 4-connection mode. If the starting point is set to 4 connections in this way, and the grid points corresponding to each line are set to 8 connection mode as described above, then
This is because data is written to all grid points in ABDC of the converted image without omission. For example, in Figure 8B, if the converted line is a straight line with an upward angle of 45 degrees to the right, and each line is in 8-connection mode, that is, a mode that allows diagonal pixel succession, and each starting point is also in 8-connection mode, each line The starting point coordinates of are (-2, 2), (-1, 1), (0, 0).
However, if you draw a straight line upward to the right from these starting points using only a series of diagonal pixels, the coordinates (-1, 2),
(0,3), (1,4) line, (0,1), (1,
2), each pixel in the lines (2, 3) will be missed. However, if the starting point connection mode is set to 4 connection mode, the coordinates (-1, 2), (0, 1)
Also serves as the starting point, so no missing pixels occur. The 4-concatenated interpolation may have the same configuration as the 8-concatenated interpolation using the DDA 8, the X counter 502, and the Y counter 503, so that the X and Y counters are not updated by 1 at the same time. That is, unless both counters are updated at the same time, adjacent grid points in the b, d, f, and h directions shown in FIG. 3B will not occur, resulting in 4 connections as shown in FIG. 3A. Although such four-connected interpolation may be configured by hardware, in this embodiment,
This is assumed to be realized by the software of CPU1. However, since the contents of this process are almost the same as the above-mentioned 8-connected interpolation using hardware, a description thereof will be omitted.

Furthermore, after the starting points of the second and subsequent lines on the converted image are determined as described above and the initial settings of the image conversion apparatus are performed, the horizontal line on the source image to be read at that time is determined as follows. First, the number of pixels between ac of rectangle 21 on the source image is M, and the number of pixels N between lattice points A and C of parallelogram 61 on the converted image is 4-connected, so N=|x _C −x _A |+|y _B −y _A |+1 …(3). Therefore, when determining from which pixel column of the source image the first line of the converted image is generated, from the grid point a of the source image, 0.5+(M-1)/(N-1)... (4) is rounded to an integer and is set as the lower line. CPU1 reads this and stores it in FIFO register 4.
You can transfer it to

In this way, the CPU 1 determines the starting point of the second and subsequent lines on the converted image and the line on the source image that should be set in the FIFO register 4 at that time, initializes the image conversion device 5, and then activates it.
By sequentially repeating this operation, the conversion process of the source image 21 into the converted image 61 is completed.

FIG. 8 shows a specific example of linear transformation based on the above operation. The source image in A of the same figure is converted as shown in B of the same figure. Source image grid points (0,0), (0,
3) using the first equation to obtain the transformed coordinates (0,
The number of pixels N between 0) and (-2, 2) is given by the third equation,
N=2+2+1=5. The coordinates of each pixel are (0,0), (0,1), (-1,
1), (-1, 2), (-2, 2), and a line will be drawn using these as starting points. next,
From the fourth equation, it is determined which line of the source image to start conversion from each of these starting point pixels. Since the number of lines M in the source image is "4", the first line (0th line) starting at (0,0) of the converted image is 0th line: 0.5 + 0 x 3/4 = 0. , and so on. 1st line: 0.5 + 1 x 3/4 = 1 2nd line: 0.5 + 2 x 3/4 = 2 3rd line: 0.5 + 3 x 3/4 = 2 4th line: 0.5 + 4 x 3 /4=3. In other words, the conversion line at the starting point (0,0) is the line at Y=0 in the source image (pixels 13, 14,
15, 16), and the conversion line at the starting point (0, 1) is generated using the Y=1 line (pixels 9, 10, 11, 12) of the source image. Starting point (−
1, 1) and (-1, 2) are both the Y=2 line of the source image (pixels 5, 6, 7,
8), and the conversion line at the starting point (-2, 2) is the line at Y=3 of the source image (pixels 1, 2).
2, 3, 4). Through the above operations, pixel data is given to all pixels within the area of the converted image surrounded by the dotted line.

Note that in the above explanation, one line on the converted image is connected in 8-connection mode, and the start point of each line is connected in 4-connection mode, but this is reversed, and one line on the converted image is connected in 4-connection mode. It is clear that data is given to all grid points on the converted image even in the 8-connected mode between the starting points.

〔Effect of the invention〕

According to the above embodiment, the data on each line of the source image is converted sequentially rather than randomly, so it is possible to use the FIFO register.
The CPU 1 reads the source image 21 from the main memory 2, transfers it to the FIFO register 4, and calculates the data to be given to the registers of the image conversion device 5, and the image conversion device 5 reads the FIFO register 4 and transfers it to the frame memory 6. Since the process of writing the converted image can be executed in parallel, there is an effect that high-speed linear conversion processing can be performed, and data can be applied to all pixels on the converted image. Further, the image conversion device 5 is configured to convert 2 in the coordinate system of the frame memory 6.
Since it is possible to interpolate between points and write the data read from the FIFO register 4, it can also be used as a normal straight line generator for other purposes, and has the advantage of being efficient in terms of hardware usage.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of an image conversion device that is a feature of the present invention, FIG. 2 is an explanatory diagram of linear transformation, FIG. 3 is a detailed diagram of 4-connection and 8-connection, and FIG. 4 is a diagram of the present invention. Figure 5 is a diagram showing the internal configuration of the digital differential analyzer (DDA), Figures 6 and 7 are explanatory diagrams of the linear transformation processing method, and Figure 8 is a diagram showing the overall configuration of the image processing device. FIG. 2 is a diagram showing an example of image conversion. 1... CPU, 2... Main memory, 3... Bus, 4... FIFO register, 5... Image conversion device,
6...Frame memory, 7...Display, 8
...DDA, 9 ...DDA, 501 ... Direction register, 502, 503 ... Counter, 504 ... Sequence control circuit.

Claims (1)

[Scope of Claims] 1. Linear transformation processing of one or more combinations of translation, enlargement, reduction, and rotation is performed on predetermined lattice points surrounding a source image to obtain transformed lattice point positions of the predetermined lattice points. In an image processing device that generates a converted image by mapping each pixel of the source image line by line to a conversion area surrounded by the conversion grid points and displays the converted image on the screen, the adjacency relationship of pixels is determined in the vertical, horizontal, and diagonal directions. If the adjacent mode is set to 8-connection mode in any of Generate the starting point of in 4-connection mode,
When each line after conversion is generated in 4-connection mode, means for generating the start point of each adjacent line after conversion in 8-connection mode, and the number of pixels in one line after conversion for the number of pixels in one line of the source image. If the number of pixels is large, each of one or more pixels in the line of the source image is mapped to a plurality of consecutive pixels of the line after conversion, and all pixels of the line after conversion are converted into pixels of the line of the source image. An image processing device characterized by comprising: means for making it compatible with the above. 2 Perform linear transformation processing of one or more combinations of translation, enlargement, reduction, and rotation on predetermined lattice points surrounding the source image to obtain the transformed lattice point positions of the predetermined lattice points, and In an image processing device that maps each pixel line by line to a conversion area surrounded by the conversion grid points to generate a converted image and displays it on the screen, the adjacency of pixels is that they are adjacent in either the vertical, horizontal, or diagonal directions. If the mode is set to 8-connected mode and the mode that is adjacent only in the vertical and horizontal directions is set to 4-connected mode, when each line after conversion is generated in 8-connected mode, the starting point of each adjacent line after conversion is set to 4-connected mode. Generate with
When each line after conversion is generated in 4-connection mode, means for generating the start point of each adjacent line after conversion in 8-connection mode, and the number of pixels in one line after conversion for the number of pixels in one line of the source image. An image processing apparatus comprising means for discarding the pixel data of the line of the source image by the small number of pixels and making the remaining pixels correspond to the line after conversion.