JPH05252004A - Latch circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable stable operation even if there is a variation in the operating time of the circuit elements that make up the latch circuit made up of gate circuits. [Structure] A first AND gate having two input terminals, one of which is negative logic, and a second AN having two input terminals.
It consists of a D gate, a third AND gate having two input terminals, and an OR gate having three input terminals. The control signal is a negative signal of the first AND gate. It is input to a logic input terminal and one input terminal of the second AND gate, and a data input signal is input to the other input terminal of the second AND gate and the third AND gate. Of the first AND gate, the positive logic input terminal of the first AND gate, the other input terminal of the third AND gate and the output terminal of the OR gate, The output terminals of the first to third AND gates are connected to the three input terminals of the OR gate, respectively, and the output terminals of the OR gate are used as output signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit used in various digital circuits, and more particularly, to stable operation without being affected by variations in the operating speed of each gate circuit element forming the latch circuit. It relates to an operating latch circuit.

[0002]

2. Description of the Related Art A conventional latch circuit formed by combining logic gate elements is formed as shown in FIG. FIG. 5 shows a conventional latch circuit composed of a plurality of gate circuits. The control signal C of the latch circuit is the first input of the second AND gate 2 and the second input circuit i12 forming the inverting input circuit of the first AND gate 1.
Is input to the input circuit i21. Further, the data input signal D is inputted to the second input circuit i22 of the second AND gate 2. Also, the output signal S1 of the first AND gate 1
, The output signal S2 of the second AND gate 2 is O
Input to R Gate 5. The output signal Q of the OR gate 5 is the latch output signal of this latch circuit. Further, the latch output signal Q is input to the first input circuit i11 of the first AND gate 1. FIG. 6 shows an example of the circuit operation in the circuit configuration described above. In FIG. 6, the horizontal axis represents time, and the vertical axis represents changes in each signal. In FIG. 6, C indicating a signal change is a control signal, D indicating a signal change is a data input signal, S1 indicating a signal change is an output signal of a first AND gate, and S2 indicating a signal change is a second AND gate. The gate output signal and Q indicating the signal change respectively indicate the latch output signal of this latch circuit. The upper part of each signal is H (high) and the lower part is L (low). Now, for example, when the control signal C changes from H (high) to L (low) at the time t1 while the data input signal D is H (high), the output signal S of the second AND gate 2 is output.
2 changes from H (high) to L (low), but the output signal Q up to that point was H (high), so the first AND
The gate output signal S1 changes from L (low) to H (high), and the output signal of this latch circuit is maintained at H (high). Therefore, as shown in the truth table of Table 1, when the control signal input is H (high), the data input signal D is output as it is, and when the control signal input is L (low), the data input signal D does not change. Instead, the data input signal D before the control signal input changes to L (low) is latched.

[0003]

[Table 1]

[0004]

By the way, in the conventional latch circuit as described above, for example, as shown in FIG. 7, in the logic gate element constituting this latch circuit, the AND gate 1 If the element operates later than the element of the AND gate 2, it may not operate normally. FIG. 7 shows the same change state of each signal as in FIG. In FIG. 7, the element of AND gate 1 is AN
If it operates later than the element of the D gate 2, there is a period in which the signal S1 and the signal S2 are at the same time L (low) when the control signal C changes from H (high) to L (low). From t2, the output signal Q of the latch circuit during that period is L
Become (low). If the operation delay of the element of the AND gate 1 is large, the signal S1 cannot change to H (high),
The output signal Q of the latch circuit remains changed from H (high) to L (low) and fails in latching. As described above, the conventional latch circuit has a problem that a stable latch operation may not be performed if the operating speeds of the elements that form the circuit vary. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to provide a latch circuit that operates stably even if there is a variation in the operating time of the circuit elements forming the latch circuit.

[0005]

In order to solve the above problems, a latch circuit according to the present invention comprises a first AND gate having two input terminals, one of which is a negative logic, and two input terminals. With a second AND gate, a third AND gate with two input terminals, and an OR with three input terminals
A gate and a control signal from the first AN.
Input to the negative logic input terminal of the D gate and one input terminal of the second AND gate, and input the data input signal to the second input gate.
Other AND gate and the third AND gate described above.
Input to one input terminal of the OR gate, and the positive input terminal of the first AND gate is connected to the other input terminal of the third AND gate and the output terminal of the OR gate. , The above first
The output terminals of the third AND gate are connected to the three input terminals of the OR gate, respectively, and the output terminal of the OR gate is used as an output signal. Further, the latch circuit according to the present invention is controlled by the control signal.
In a latch circuit for latching a data input signal, a logical operation circuit composed of a plurality of logic gate circuits to which a control signal, a data input signal and a latch output signal are inputted, a 2-input AND gate A two-input OR gate for receiving a signal from the AND gate and the logical operation circuit and the AND gate, and one input terminal of the AND gate has a data terminal.
It is possible to add a data input signal to make the output of the OR gate a latch output signal and feed back this output signal to both the logical operation circuit and the AND gate. ..

[0006]

The latch circuit according to the present invention has a basic configuration shown in FIG.
With this configuration, even if there is a variation in the operating time of the circuit elements that make up the latch circuit, the latch circuit operates reliably and reliably without malfunction. Further, in the structure shown in FIG. 2 having another structure, even if the operating speeds of the gate circuit elements forming the inside of the latch circuit vary,
Data input signal at the moment when the input signal is inverted,
Stable and reliable operation by the latch circuit output signal.

[0007]

Embodiment 1 First, Embodiment 1 according to the present invention will be described in detail with reference to FIG. 1 showing a schematic block and FIG. 2 showing a schematic operation characteristic. In FIG. 1, element circuits having the same functions as those of the conventional one are denoted by the same reference numerals as those in FIG. That is, similarly to the conventional circuit, the control signal C of the latch circuit is the second input circuit i12 of the first AND gate 1 and the first input circuit i21 of the second AND gate 2.
Are typing in. The second input circuit i12 of the first AND gate 1 forms an inverting input circuit. Further, the data input signal D is the second input circuit i22 of the second AND gate 2.
Are typing in. Further, the latch output signal Q is the first AN
It is input to the first input circuit i11 of the D gate 1. Further, in FIG. 1, the latch output signal Q is input to the first input circuit i31 of the third AND gate 3, and the third AND gate 3
The data input signal D is input to the second input circuit i 32 of the gate 3. The AND gate 1 outputs the output signal S1 and the AND gate 2 outputs the output signal S2. The output signal S3 of the third AND gate 3 is input to the OR gate 4 together with the output signals S1 and S2 of the above-mentioned two AND gates, and the output of this OR gate 4 is It forms the latch output signal Q of the latch circuit.

Of the operations of the above circuit, the data input signal D
Is H (high), the control signal C is H (high)
The operation will be described in detail with reference to FIG. 2 which shows an outline operation when changing from L to low. In FIG. 2, the horizontal axis shows time and the vertical axis shows changes in each signal. In FIG. 2, C indicating a signal change is a control signal, D indicating a signal change is a data input signal, S1 indicating a signal change is an output signal of a first AND gate, and S2 indicating a signal change is a second AND gate. The gate output signal and S3 indicating the signal change are the output signals of the third AND gate and the Q indicating the signal change are the latch output signals of this latch circuit, respectively. The upper part of each signal is H (high) and the lower part is L (low). Although the waveform diagram is not shown in the operation of the circuit configuration shown in FIG. 1, when the data input signal D is L (low) and the control signal C is H (high) as in the truth table described in Table 1, First
AND gate 1 output signal S1 is L (low), second AND gate 2 output signal S2 is L (low), and third A gate
The output signal S3 of the ND gate 3 is also L (low), and the output signal Q of the latch circuit is L (low). Data input signal D is H (high) and control signal C is H (high)
In the case of, the output signal S1 of the first AND gate 1 is L
(Low), the output signal S2 of the second AND gate 2 is H
(High), the output signal S3 of the third AND gate 3 is determined by the output signal Q of the latch circuit, and the output signal Q of the latch circuit is H (high). When the control signal C changes from H (high) to L (low) while the data input signal D is L (low), the output signal S2 of the second AND gate 2 is L.
The output signal Q until then remains L (low)
Therefore, the first AND gate output signal S1 also remains L (low). The output signal Q of the latch circuit is L (low) while the third AND gate output signal S3 remains L (low). As shown in FIG. 2, the data input signal D is H
In the high state, the control signal C becomes H at time t1.
When changing from (high) to L (low), the output signal S2 of the second AND gate 2 changes from H (high) to L (low), but the output signal Q up to that point is H (high). Therefore, the first AND gate output signal S1 changes from L (low) to H (high). Therefore, the output signal of this latch circuit is maintained at H (high). Therefore, also the third
AND gate output signal S3 remains unchanged at H (high). That is, as shown in the truth table shown in Table 1, when the control signal input is H (high), the data input signal D is output as it is, and when the control signal input is L (low), the data input signal D changes. Instead, the data input signal D before the control signal input changes to L (low) is latched.

The data input signal D is H (high) when the operation time of the element forming the first AND gate 1 is delayed from that of the element 2 forming the second AND gate 2. In this state, the control signal C changes from H (high) to L (low)
The general operation when changing to is as shown in FIG.
In FIG. 3, the horizontal axis represents time and the vertical axis represents C, D, S1, S as in FIG.
The signal changes of 2, S3 and Q are shown. In FIG. 3, when the element of the AND gate 1 operates later than the element of the AND gate 2 by t2, when the control signal C changes from H (high) to L (low), the signals S1 and S2
There is a period in which L is low at the same time. However, during that period, the output signal S3 of the third AND gate 3 is maintained at H (high) because the output signal Q of the latch circuit is in the H (high) state. Therefore, the output signal Q of the latch circuit is H
Maintained as high.

Second Embodiment: A second embodiment of a latch circuit according to the present invention will be described with reference to a schematic block diagram of FIG. In FIG. 4, reference numeral 10 is a logical operation circuit composed of a plurality of logical gate circuits. The control signal C of the latch circuit, the data input signal D, and the output signal Q of the latch output circuit are fed. The output of the logical operation circuit 10 is input to one input terminal of the OR gate 6 which is a logical addition circuit. Reference numeral 3 is a 2-input AND gate, and the data input signal D and the signal Q from the latch output circuit are fed back and input. This A
The output of the ND gate 3 is input to the 2-input OR gate 6 together with the output of the logical operation circuit 10 and logically added to obtain the latch circuit output signal Q.

By configuring the circuit as shown in FIG. 4, even if the operating speeds of the respective gate circuit elements constituting the logical operation circuit 10 vary, at the moment when the control input signal is inverted. Stable and reliable operation is achieved by the data input signal and the latch circuit output signal.

[0012]

As described above, since the first embodiment of the present invention is configured as shown in FIG. 1, even if the circuit elements constituting the latch circuit have variations in operating time, the latch circuit malfunctions. It has an excellent effect that it operates stably without fail. In addition, since the configuration of the second embodiment is configured as shown in FIG. 4, even if the operating speeds of the gate circuit elements forming the latch circuit vary, the data at the moment when the control input signal is inverted is changed. -There is an effect that it operates stably and reliably by the input signal and the latch circuit output signal.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a first embodiment of a latch circuit according to the present invention.

FIG. 2 is a characteristic diagram showing an operation example of a latch circuit according to the present invention.

FIG. 3 is another characteristic diagram showing an operation example of the latch circuit according to the present invention.

FIG. 4 is a schematic block diagram showing a second embodiment of the latch circuit according to the present invention.

FIG. 5 is a schematic block diagram showing a conventional latch circuit configuration.

FIG. 6 is a characteristic diagram showing an operation example of a conventional latch circuit.

FIG. 7 is a characteristic diagram showing a problem of a conventional latch circuit.

[Explanation of symbols]

 1,2,3: AND gate 4,6: OR gate 10: Logical operation circuit C: Control signal D: Data input signal Q: Latch output signal

Claims (2)

[Claims] 1. A first AND gate having two input terminals, one of which is negative logic, a second AND gate having two input terminals, and a third AND gate having two input terminals. It consists of an AND gate and an OR gate with three input terminals.
The control signal is input to the negative logic input terminal of the first AND gate and one input terminal of the second AND gate, and the data input signal is input to the second AND gate. Input to the other input terminal of the third AND gate and one input terminal of the third AND gate, and the positive logic input terminal of the first AND gate and the other of the third AND gate. The input terminal is connected to the output terminal of the OR gate, the output terminals of the first to third AND gates are connected to the three input terminals of the OR gate, respectively, and the OR gate is connected. The latch circuit is characterized in that the output of the output terminal of is used as an output signal. 2. A latch circuit for latching a data input signal according to a control signal, comprising a plurality of logic gate circuits to which a control signal, a data input signal and a latch output signal are inputted. And a 2-input OR gate (6) for receiving a signal from the AND gate (3) and the logical operation circuit (10). Preparation, AND gate
A data input signal is applied to one input terminal of
The output of the OR gate (6) is used as a latch output signal, and the output signal is fed back to both the logical operation circuit (10) and the AND gate (3). Latch circuit characterized by.