JPH05257500A - Voice data control system - Google Patents

Abstract

(57) [Summary] [Construction] When a write failure occurs when writing digital voice data from the RAM 3 to the PROM 5, the write control unit 4 writes the same digital voice data to the next address and the check result by the check unit 7. (Fault location)
Is written in EPROM5. At the time of reading, the determination unit 8 reads the check result from the EPROM 5 and determines whether digital audio data can be read. The read control unit 6 includes a determination unit 8
Then, the control data (start address, end address) and failure occurrence address data are read from the EPROM 5, the address of the normally written data is re-edited, and the digital voice data is read from the EPROM 5. [Effect] The efficiency of writing the digital audio data from the RAM to the ROM can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio data control system for controlling writing of digital audio data from a RAM to an EPROM and reading of the digital audio data from an EPROM in an audio output device.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing a conventional audio data control system, which is a RAM 3 for temporarily storing input digital audio data 1 and an EP for semi-fixed storage.
ROM5, RAM3, the check section 7 for checking the digital voice data stored in EPROM5, R
AM3, EPROM5 and write control section 4 having a connection path to the check section 7, and read control section 6 for reading the digital audio data semi-fixedly stored in the EPROM5 as the output digital audio data 2 also having a connection path to the EPROM5. The configuration of an audio output device having and is shown.

The operation will be described below. At the time of writing the digital voice data from the RAM 3 to the EPROM 5, the write control unit 4 uses the digital voice data in the RAM 3 to write E
Writing to PROM 5 Start address and end address are calculated, and digital voice data and control data (start address and end address) are written to EPROM 5. In the writing process, the writing control unit 4 activates the checking unit 7 to make the EPROM 5
Check the verification of the digital voice data and control data written in.

When a write failure occurs, the write control unit 4 sends the failure occurrence address and the failure display to the outside and stops the write operation. When the write operation ends normally, the operation shifts to the read operation.

When reading the digital voice data written in the EPROM 5, the read control unit 6 reads the control data from the EPROM 5 and obtains the read start address and end address of the digital voice data of the EPROM 5,
The digital voice data is read and sent as output digital voice data 2 to the outside.

[0006]

In the conventional voice data control system described above, when a writing failure occurs in the process of writing the digital voice data temporarily stored in the RAM to the EPROM, the EPROM is replaced and the writing is performed again. Since work is started, there is a drawback that work efficiency is poor.

[0007]

SUMMARY OF THE INVENTION A voice data control system of the present invention is a RAM for temporarily storing input digital voice data and an EPRO for semi-fixed storage.
M, a write controller for writing the digital audio data stored in the RAM to the EPROM, and the EPRO.
A read control unit for reading digital audio data from M,
In a voice output device configured with a check unit for checking digital voice data written in the EPROM, a determination unit activated from the read control unit is provided,
The check result by the check unit is written in the EPROM by the write control unit, and when the digital voice data is read, the check unit reads the check result from the EPROM and determines whether or not the digital voice data can be read.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. A RAM 3 for temporarily storing input digital audio data 1 and an EP for semi-fixed storage.
ROM5, RAM3, the check section 7 for checking the digital voice data stored in EPROM5, R
AM3, EPROM5 and check section 7 have a write control section 4 each having a connection path, a judgment section 8 for reading the check result from the EPROM 5 and judging whether or not the digital audio data can be read, and a connection path for the EPROM5 and the judgment section 8. A configuration of a voice output device having a read control unit 6 for reading out the digital voice data semi-fixedly stored in the EPROM 5 as the output digital voice data 2 based on the readability information of the determination unit 8 is shown.

The operation will be described below. At the time of writing the digital voice data from the RAM 3 to the EPROM 5, the write control unit 4 uses the digital voice data of the RAM 3 as a basis.
Write to EPROM5 Calculate start address and end address,
Digital voice data is written to the EPROM 5. In the writing process, the writing control unit 4 activates the checking unit 7 to perform a verification check of the digital voice data of the EPROM 5 for each writing address.

At the time of a write failure (verification check error), the write control unit 4 identifies the write address in which the failure occurred, writes the same failed data again in the next address, and continues the write operation. When the writing and verification operations of the digital voice data are completed, the writing control section 4 writes the control data (start address, end address) and the failure occurrence address data in the EPROM 5, performs the verification check operation, and ends the series of writing operations. .

When the digital voice data written in the EPROM 5 is read, the read control unit 6 activates the determination unit 8 to read the control data (start address, end address) and fault occurrence address data from the EPROM 5, and normalize the read data. The address of the written data is re-edited, the digital voice data is read from the EPROM 5, and output as the output digital voice data 2 to the outside.

[0013]

As described above, according to the present invention, the determination unit activated by the read control unit for reading the digital voice data is provided, and the check result by the check unit for checking the digital voice data is EPR by the write control unit.
At the time of writing to the OM and reading data, the determination unit reads the check result from the EPROM and determines whether the digital voice data can be read. Therefore, it is possible to improve the efficiency of writing the digital voice data from the RAM to the ROM. effective.

[Brief description of drawings]

FIG. 1 is a block diagram of an audio output device showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional audio output device.

[Explanation of symbols]

 1 Input Digital Audio Data 2 Output Digital Audio Data 3 RAM 4 Write Control Section 5 EPROM 6 Read Control Section 7 Check Section 8 Judgment Section

Claims (1)

[Claims] 1. A RAM for temporarily storing input digital audio data and an E for semi-fixed storage.
A PROM, a write control unit for writing the digital voice data stored in the RAM into the EPROM, and the E control unit.
In a voice output device comprising a read control unit for reading digital voice data from a PROM and a check unit for checking digital voice data written in the EPROM, a determination unit activated by the read control unit is provided. The writing control unit writes the check result in the EPROM, and when the digital voice data is read, the determination unit reads the check result from the EPROM and determines whether or not the digital voice data can be read. Voice data control method.