JPH05257566A - Digital signal synchronizing circuit - Google Patents

Abstract

PURPOSE:To generate a signal synchronized with a higher frequency by receiving and controlling an asynchronous signal by two flip flops whose clock inputs are second and third clock signals which have a half frequency of a clock signal to be synchronized with and have opposite phases. CONSTITUTION:A first clock signal 1 is the target clock with which an asynchronous signal 0 should be synchronized, and a second clock signal 2 has a half frequency of the signal 1. A third clock signal 3 is the inverted signal of the signal 2. A flip flop 11 takes the second clock signal 2 as the clock input and takes the asynchronous signal 0 as the data input and outputs an output signal 4. A flip flop 12 takes the third clock signal 3 as the clock input and takes the asynchronous signal 0 as the data input and outputs an output signal 5. Gates 13 and 14 output AND 6 and OR 7 between output signals 4 and 5 respectively. A selector 15 switches AND 6 and OR 7 to output an objective synchronous signal 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital logic circuit, and more particularly to a synchronizing circuit for asynchronous digital signals.

[0002]

2. Description of the Related Art Conventionally, this kind of synchronizing circuit is for converting an asynchronous signal into an output signal synchronized with a clock signal of a specific frequency.

As the simplest method, there is a method in which an asynchronous signal is input to one flip-flop whose clock input is a clock signal to be synchronized and its output is regarded as a synchronized signal. However, with this method, when the asynchronous signal changes during the change prohibition period of the data input of the flip-flop (from the setup time before the clock signal to the hold time after the clock signal), the movement of the output signal of the flip-flop is out of spec. Then, the so-called meta-stable state in which the time until the output stabilizes is considerably longer than the delay time on the spec. When a metastable condition occurs, the signal can no longer be treated as a sync signal.

Therefore, as a second method, in order to avoid a metastable state, a second flip-flop is placed in series after the first flip-flop, and a clock signal for synchronization is given as a common clock for the two flip-flops. There is a method of regarding the output of the second flip-flop as a synchronized signal. A circuit using this method is shown in FIG.

According to this method, even if the output signal 102 of the flip-flop 21 enters the metastable state, it does not appear directly in the output signal 103 of the flip-flop 22. The probability that the output signal of the FF 22 will be in the metastable state depends on the recovery time of the output of the FF 21 from the metastable state and the frequency of the clock signal, but if the recovery time is longer than the clock cycle, it will be in the metastable state. Therefore, the frequency of the clock signal cannot be made higher than a certain limit in order to keep the probability of being in the metastable state at a practically low level.

As a third method, as shown in FIG. 5, 1 / n (n = 2, n) of the first clock signal 201 to be synchronized.
A second clock signal 202 synchronized with the first clock signal and having a frequency of 3, ...
There are 32 common clock inputs.

In this method, the clock input of the flip-flop can be synchronized with the clock of a higher frequency because it can be synchronized with the clock of a higher frequency, but there is a drawback that the followability of the synchronization signal with respect to the asynchronous signal is deteriorated. . FIG. 6 shows a delay time T (D) from an asynchronous signal to a synchronization signal in a circuit using the second clock signal 202 having a frequency half that of the first clock signal 201.
Indicates. From this figure, it can be seen that T (D) = 4 × T (CLK1) in some cases.

[0008]

As described above, the above-mentioned conventional synchronizing circuits have their respective drawbacks, and it is impossible to form a synchronizing signal which is synchronized with a clock signal having a high frequency and has a good followability with respect to an asynchronous signal. There is a point.

[0009]

SUMMARY OF THE INVENTION The digital signal synchronizing circuit of the present invention is a half of the first clock signal to be synchronized.
And a third clock signal which is an inverted signal of the second clock signal, wherein the second clock signal is a clock input and the asynchronous signal is a data input. A first flip-flop, a second flip-flop that receives the third clock signal as a clock input and the asynchronous signal as a data input, and a first gate that outputs a logical product of the output signals of the first and second flip-flops A second gate for outputting a logical sum of the output signals of the first and second flip-flops,
A selector for switching the outputs of the first and second gates to output a synchronizing signal; and a third flip-flop for receiving the first lock signal as a clock input and the output signal of the selector as a data input, The output of the three flip-flops controls the selector.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
In the figure, 1 is a first clock signal, which is a target clock for synchronizing the asynchronous signal 0. 2 is the first
The second clock signal has a frequency that is half that of the clock signal 1, and the third clock signal 3 is an inverted signal of the second clock signal 2. The flip-flop 11 is the second
The clock signal 2 is used as a clock input, the asynchronous signal 0 is used as a data input, and the output signal 4 is output. The flip-flop 12 outputs the output signal 5 with the third clock signal 3 as a clock input and the asynchronous signal 0 as a data input. The gate 13 outputs a logical product 6 of the output signals 4 and 5, and the gate 14 outputs a logical sum 7 of the output signals 4 and 5. The selector 15 switches between the logical product 6 and the logical sum 7 and outputs the target synchronization signal 8.

The flip-flop 1 receives the synchronizing signal 8 as a data input and the first clock signal 1 as a clock input, and outputs an output signal 9 to control the selector 15. Sector 15
Is a logical product 6 when the output signal 9 is “0”, and the output signal 9
When is "1", logical sum 7 is selected.

FIG. 2 is a time chart when the asynchronous signal 0 changes in the data input changeable period in the above digital signal synchronizing circuit. In the figure, the delay between the asynchronous signal 0 and the synchronous signal 8 is T (D) = 2 × T (CLK
1).

In FIG. 3, the asynchronous signal 0 is the flip-flop 1
7 is a time chart when the data input change prohibition period of No. 1 is changed. In the figure, the shaded area is a metastable state, and the mesh area is an output signal to which a metastable signal is input.

When the input changes so that the FF 11 is in the metastable state, the output of the FF 12 is not in the metastable state because the FF 12 is in the data input changeable period. Therefore, during the period before and after the rise of the output 6 of the gate 13 and before and after the fall of the output 7 of the gate 14, the signal changes due to a normal delay.

When the output 9 of the FF 16 is "0", the output 6
Selector 15 selects output 7 when "1".
Is controlled, the metastable state does not influence the output 8 of the selector 15. Therefore, the synchronizing signal delayed from the clock signal 1 by the delay of the gate 13 or 14 and the selector 15 is output. That is, the delay between the asynchronous signal 0 and the synchronous signal 8 is T (D) ≦ 2 × T (CLK1).

In order that the synchronization signal 8 is not affected by the metastable state, the frequencies of the clock signal 2 and the clock signal 3 must be below a certain limit, which is the third conventional method (FIG. 5). , The limit of the clock 202 in FIG. 6). However, since the delay between the asynchronous signal and the synchronizing signal is T (D) = 4 × T (CLK1), the synchronizing signal of the present invention has better followability.

The same applies when the asynchronous signal 0 changes during the data input change prohibition period of the flip-flop 12.

[0019]

As described above, according to the present invention, two flip-flops, which have as their clock inputs the opposite second and third clock signals having a frequency half that of the clock signals to be synchronized, are asynchronous. By receiving the signals in parallel and controlling them in the subsequent circuit, there is an effect that it is possible to generate a synchronization signal that is synchronized with a higher frequency and has good tracking characteristics.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform chart showing an example of operation.

FIG. 3 is a waveform chart showing another example of the operation.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is a circuit diagram showing another conventional example.

FIG. 6 is a waveform chart showing the operation of a conventional example.

[Explanation of symbols]

 11, 12, 16 Flip-flop 13, 14 Gate 15 Selector

Claims (1)

[Claims] 1. Half of the first clock signal to be synchronized
And a third clock signal which is an inverted signal of the second clock signal, wherein the second clock signal is a clock input and the asynchronous signal is a data input. A first flip-flop, a second flip-flop that receives the third clock signal as a clock input and the asynchronous signal as a data input, and a first gate that outputs a logical product of the output signals of the first and second flip-flops A second gate for outputting a logical sum of the output signals of the first and second flip-flops,
A selector for switching the outputs of the first and second gates to output a synchronizing signal; and a third flip-flop for receiving the first lock signal as a clock input and the output signal of the selector as a data input, A digital signal synchronizing circuit characterized in that the selector is controlled by the output of three flip-flops.