JPH05257860A - Information processing equipment - Google Patents

Abstract

(57) [Abstract] [Object] An object of the present invention is to efficiently use a bus and improve system performance. [Structure] The display memory 5 can be accessed by the access request of the graphics processor 6 itself.
At the time of an access request from an external device such as U2 or DMAC3, a stop request signal via the stop control unit 7 makes it possible to temporarily stop the access request of the graphics processor 6, and the CPU 2 or DM
By giving priority to an access request from an external device such as AC3 and accessing the display memory 5 via the graphics processor 6, the load of the bus 8 is reduced without unnecessarily occupying the bus 8 and the system is reduced. Improve performance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function of generating an address in a processor to access a memory, and a memory using an address in the processor or an address from the outside according to an access request from the outside. The present invention relates to an information processing device having a function of accessing to.

[0002]

2. Description of the Related Art A function for generating an address in a processor to access a memory, and a function for accessing a memory by using an address in the processor or an address from the outside according to an access request from the outside. In the conventional information processing apparatus having the above, when an access request in the processor and an access request from the outside are simultaneously issued, either access request is processed first by the exclusive control in the processor, and after the completion, another access request is processed. Processing one access request. This will be described in more detail.

FIG. 8 shows the entire system of a conventional information processing apparatus using a graphics processor, for example. That is, a memory 51 that stores programs and data, a CPU 52 that performs data processing and device control by the programs, a direct memory access controller (DMAC) 53 that controls data transfer on behalf of the CPU 52, and data that is displayed on the display 54 are stored. Display memory 55, C in display memory 55
It is composed of a graphics processor 56 that draws a figure or the like according to an instruction from the PU 2.

A memory 51, a CPU 52, a DMAC 53,
The graphics processors 56 are connected by a common bus 57. Where the graphics processor 5
6 can generate an address in the graphics processor 56 according to an instruction from the CPU 52 and automatically draw it in the display memory 55. In addition, the CPU 52
Alternatively, an external device such as the DMAC 53 can access the display memory 55 via the graphics processor 56 as if it were accessing itself.

Next, when the CPU 52 accesses the display memory 55 via the graphics processor 56, if the drawing sequencer in the graphics processor 56 is not operating, the CPU 52 continuously displays the display memory 5.
5 can be accessed.

However, while the drawing sequencer in the graphics processor 56 is operating, the CPU 5
When the access request is issued from 2, the access request signal of the access request from the CPU 52 is kept waiting by the exclusive control because it conflicts with this.

As a result, the bus 57 continues to be occupied by the access request signal of the CPU 52 until the access of the drawing sequencer in the graphics processor 56 is completed, which hinders the access of other devices connected to the bus 57. As a result, the system performance was significantly reduced.

[0008]

As described above, when the access request from the processor itself and the access request from the outside are issued, either access request is processed first by the exclusive control, and the other is processed after the completion. Was processing the access request. However, if an access request from the outside such as a CPU is generated via the bus while the processor itself is accessing the access request, the access request is kept waiting by the exclusive control. Therefore, there is a problem that the bus is occupied until the access of the processor is completed, another access request cannot be issued to the bus, and as a result, the system performance is significantly deteriorated. Therefore, it is an object of the present invention to provide an information processing device that can efficiently use a bus and improve system performance.

[0009]

An information processing apparatus according to a first invention is a storage means for storing information, and a first processing means for processing information using the information stored in the storage means. And second processing means for accessing the storage means through the first processing means, and the second processing means.
Detecting the access request signal from the processing means
And means for interrupting the processing by the processing means.

An information processing apparatus according to a second aspect of the invention is a storage means for storing information, a first processing means for processing information using the information stored in the storage means, and the above-mentioned first means. Second processing means for accessing the storage means through the processing means, a direct memory access controller for controlling transfer of processing information in place of the second processing means, the direct memory access controller, and the second A bus connecting the processing means and the first processing means, and means for detecting an access request signal from the second processing means or the direct memory access controller to interrupt the processing by the first processing means. It consists of

[0011]

In the information processing apparatus according to the first aspect of the present invention, information is stored in the storage means, the stored information is processed by the first processing means, and the storage means is accessed through the first processing means. Is performed by the second processing means, the access request signal from the second processing means is detected, the processing by the first processing means is interrupted, and the processing by the second processing means is preferentially executed. It is a thing.

An information processing apparatus according to a second aspect of the present invention stores information in storage means, uses the stored information for processing by the first processing means, and accesses the storage means through the first processing means. Is performed by the second processing means or the direct memory access controller.
The processing means, the second processing means, and the direct memory access controller are connected by a bus, and an access request signal from the second processing means or the direct memory access controller is detected to interrupt the processing by the first processing means. By preferentially executing the processing by the second processing means or the direct memory access controller, the bus occupation time by the second processing means or the direct memory access controller is minimized.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. As the processor of this embodiment, a graphics processor that performs graphic drawing processing and the like will be described.

FIG. 1 shows the entire system according to an embodiment of the information processing apparatus of the present invention. That is, a memory 1 for storing programs and data, a CPU 2 for performing data processing, device control, etc. by the programs, a CPU
Direct memory access controller (DMAC) 3 for controlling data transfer in place of 2, display memory 5 for storing data to be displayed on display 4, graphics processor 6 for drawing graphics and the like on display memory 5 in accordance with instructions from CPU 2. , A stop control unit 7 for generating a stop request signal for temporarily suspending an internal drawing sequencer to the graphics processor 6 according to an instruction from the CPU 2 and detecting a stop status from the graphics processor 6. .. Memory 1 and CP
The U2, the DMAC3, the graphics processor 6, and the stop control unit 7 are connected by a common bus 8.

The CPU 2 accesses the memory 1 via the bus 8, accesses the register of the DMAC 3, the stop control unit 7 or the graphics processor 6, and the display memory 5 as if the display memory 5 was accessed via the graphics processor 6. You can access it as if you were directly connected to. Similarly, the DMAC 3 can access the memory 1 and the display memory 5.

The graphics processor 6 has a drawing sequencer, which will be described later, for straight line drawing, rectangular drawing, copying, etc., and the graphics processor 6 itself can access the display memory 5 by generating an address.

FIG. 2 shows the configuration of the stop control unit 7, which is composed of a decoder 11, a controller 12, a register 13 and a buffer 14 each connected to a bus 8.
Upon receiving the access request signal b sent from the CPU 2 or the DMAC 3 via the bus 8, the register 13 outputs a stop request signal to the graphics processor 6. Further, the stop status signal from the graphics processor 6 is detected by the buffer 14 and sent to the CPU 2.

FIG. 3 shows the configuration of the graphics processor 6. That is, the system interface 20 that interfaces with the CPU 2 or an external device via the bus 8, the drawing sequencer 21 that controls the drawing sequence, and the drawing sequencer 21 that receives the stop request signal S from the stop control unit 7 A mask section 22 formed of an AND circuit for masking the access request signal a, an access request signal a from the drawing sequencer 21 via the mask section 22, and an access request signal from an external device such as the CPU 2 via the system interface 20. The processing by the priority order determination unit (arbiter) 23 and the drawing sequencer 21 that performs exclusive control with b and determines which processing is executed is interrupted,
A stop status generator 24, which is an AND circuit that generates a stop status indicating that the request from the drawing sequencer 21 is not being processed, a controller 25 that controls the display memory 5 and the entire graphics processor 6, and a display memory. 5, from the address generator 26 that generates an address for accessing 5, or an address on the bus 8 in the case of an external access, or a specified address, data from the bus 8 and the display memory 5. Data processing unit 27 for processing the data of
It consists of and.

FIG. 4 shows the configuration of the priority order determining unit 23. The AND circuits 31 to 39, the OR circuits 40 to 43,
And a flip-flop circuit 44, 45, and a reset signal and a clock signal are supplied from the controller 25. Here, the access request signals a and b
When signals occur simultaneously and continuously, the signal a and the signal b are alternately processed as described later.

If the signals A and B are signals that are enabled when the signal a or the signal b is selected, the signal A is a. It is enabled under the condition of b + a ・ b ・ B, and the signal B is! a ・ b + a ・ b ・! It is enabled under the condition of B. Next, the operation in such a configuration will be described.

First, the CPU 2 sets necessary parameters in the graphics processor 6 via the bus 8. When the graphics processor 6 draws on the display memory 5, an access request signal a is issued from the drawing sequencer 21 of the graphics processor 6, and the stop control unit 7
If the stop request signal S from is not input, the signal a is enabled and input to the priority order determination unit 23.

If there is no access request signal b from the outside such as the CPU 2, the priority order determining section 23 selects the signal a,
Signal A is enabled. Upon receiving the signal A, the controller 25 outputs a necessary address from the address generation unit 26 to the display memory 5, and outputs the data from the data processing unit 27 to the display memory 5 to control access to the display memory 5.

Upon completion of one access, the controller 25 issues an end signal to the drawing sequencer 21 to terminate it, and also issues a reset signal to cause the priority determining section 23 to determine the priority again. If the access request signal b is not output from the CPU 2, the sequence of the drawing sequencer 21 is completed and is repeated until the access request signal a disappears.

If there is no signal a from the drawing sequencer 21 and only the signal b from the outside of the CPU 2 or the DMAC 3 via the bus 8, the signal b is enabled and the priority order determining unit 23 receives the signal B. Is enabled. Upon completion of one access, the controller 25 sends the CP via the system interface 20 and the bus 8.
An end signal is issued to U2 or DMAC3 to end the process, and a reset signal is issued to re-establish the priority order determination unit 2
At 3, the order of priority is determined. If the access request signal a is not issued from the drawing sequencer 21, the CPU 2
Alternatively, the sequence is repeated until the access request signal b disappears after the sequence of DMAC3 is completed. (See Figure 5)

Next, the processing operation when the access request signals a and b come from both the drawing sequencer 21 and the CPU 2 will be described. Here, consider a state in which the stop request signal S from the stop control unit 7 shown in FIG. 2 is not input to the mask 22.

An access request signal a from the drawing sequencer 21 and an access request signal b from the CPU 2 are input to the priority order determining section 23. In the priority order determination unit 23,
First, the AND circuit 31 inputs “1” of the signal a and “0” which is the inverted signal b and outputs “0”, and the AND circuit 32 outputs “1” of the signal a and “1” of the signal b. The AND circuit 33 receives the output "1", and the AND circuit 33 receives the inverted "0" of the signal a and the signal "1" of the signal b and outputs "0".

The flip-flop circuit 45 at this point
Is an output “0” by a clear signal from the controller 25, and one input of the AND circuit 34 is “0”,
One input of the AND circuit 35 is inverted to be "1". The AND circuit 34 receives the output “0” of the flip-flop circuit 45 and the output “1” of the AND circuit 32 and becomes an output “0”, and the AND circuit 35 inverts the output “0” of the flip-flop circuit 45. 1 "and AND circuit 32
Output "1" is input to output "1".

The output "0" of the AND circuit 31 and the output "0" of the AND circuit 34 are input to the OR circuit 40 to become the output "0". Flip-flop circuit 4 at this point
4 is an output “0” according to a clear signal from the controller 25. The AND circuit 36 becomes an output "0" by the output "0" of the flip-flop circuit 44 and the reset signal "0".

The AND circuit 37 receives the output “0” of the OR circuit 40 and the inverted signal “1” of the reset signal “0” and becomes an output “0”. The output “0” of the AND circuit 36 and the output “0” of the AND circuit 37 are input to the OR circuit 42, and the output becomes “0”. In the flip-flop circuit 44, since the output of the OR circuit 42 is "0", the signal a is not selected as a result.

The output "0" of the AND circuit 33 and the output "1" of the AND circuit 35 are input to the OR circuit 41, and the output becomes "1". The AND circuit 38 becomes an output "0" by the output "0" of the flip-flop circuit 45 and the reset signal "0". The AND circuit 39 receives the output “1” of the OR circuit 41 and the inverted signal “1” of “0”, and outputs “1”. The output “0” of the AND circuit 38 and the output “1” of the AND circuit 39 are input to the OR circuit 43 and become the output “1”. The flip-flop circuit 45 enables the signal B by the output "1" of the OR circuit 43 and the clock signal which are input. Thus
First, the access request signal b from the CPU 2 is selected, the signal B is enabled, and the display memory 5 is accessed from the CPU 2 side.

When this is completed, the priority order determination unit 23 determines the priority order of the next access, and since the signal b of the CPU 2 was selected last time, the signal a of the drawing sequencer 21 is selected next, the signal A is enabled, and the drawing is performed. The display memory 5 is accessed from the sequencer 21 side.
That is, since the output of the flip-flop circuit 45 becomes "1", the output "1" of the flip-flop circuit 45 and the output "1" of the AND circuit 32 are input to the AND circuit 34 and become the output "1". ..

The output "0" of the AND circuit 31 and the output "1" of the AND circuit 34 are input to the OR circuit 40 to become the output "1". The AND circuit 37 receives the output “1” of the OR circuit 40 and the inverted signal “1” of the reset signal “0” and outputs “1”. The OR circuit 42 outputs the output “0” of the AND circuit 36 and the output “1” of the AND circuit 37.
And are input and the output becomes "1".

The flip-flop circuit 44 enables the signal A by the input "1" of the OR circuit 42 and the clock signal. In this way, the access request signal a from the drawing sequencer 21 is secondly selected and the signal A
Are enabled, and the display memory 5 is accessed from the drawing sequencer 21 side.

Thus, the drawing sequencer 21 and the CPU 2
By alternately repeating the access by and, the processing on the drawing sequencer (DS) 21 side and the CPU 2 side are alternately repeated as shown in FIG. Therefore, while the access by the signal a from the drawing sequencer 21 is being performed, the signal b from the CPU 2 is kept waiting, and during this time, the bus 8 is occupied, so that other operations using the bus 8 are hindered. .. Next, the processing operation according to the present invention will be described with reference to FIG.

When the stop request signal S of FIG. 3 is disabled and the drawing sequencer 21 of the graphics processor 6 is not operating, the output of the stop status generator 24 is "1", that is, the graphics processor. The stop status signal 6 is enabled. At this time, when the signal a is output from the drawing sequencer 21, the gate of the mask section 22 is open, so the signal A is selected in the priority order determining section 23, and the drawing sequencer 21 accesses the display memory 5. ..

When the CPU 2 accesses the display memory 5, first, the CPU 2 gives an access request signal b to the stop controller 7 in FIG. As a result, the stop request signal S
Are provided to the graphics processor 6. As a result, the signal a from the drawing sequencer 21 in FIG.
Even if it is output, it is masked by the masking unit 22, becomes disabled, and is not subject to priority order determination.

Therefore, when the CPU 2 accesses the display memory 5 at this time, the processing can be performed without waiting for the access, and the processing can be continued until the CPU 2 releases the access request signal b. As a result, the bus 8 is not occupied for an unnecessary time such as a waiting time for an access request, and the system performance can be improved. Then, if the CPU 2 releases the access request signal b, the drawing sequencer 21 becomes immediately accessible.

As described above, according to the above embodiment,
At the time of an access request from an external device such as the CPU 2 or the DMAC 3, the stop request signal output via the stop control unit 7 temporarily stops the access request from the drawing sequencer 21 of the graphics processor 6, and the CPU 2 Alternatively, the access request from the external device such as the DMAC 3 can be prioritized. Therefore, since the bus 8 is not unnecessarily occupied, the load on the bus 8 is reduced and the system performance is improved. When the I / O device is accompanied by an access from the outside, the I / O device cannot wait, so the present invention is particularly effective.
Although the graphics processor is used in this embodiment, the invention is not limited to this, and the external device may not be the CPU. Further, the stop request signal does not have to be passed through the stop control unit, and may be directly input from an external device.

[0039]

As described in detail above, according to the present invention,
It is possible to provide an information processing device that can efficiently use a bus and improve system performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a stop control unit.

FIG. 3 is a diagram showing a configuration of a graphics processor.

FIG. 4 is a diagram showing a configuration of a priority order determination unit.

FIG. 5 is a diagram showing a timing at the time of CPU operation.

FIG. 6 is a diagram showing a timing when the CPU and a drawing sequencer operate.

FIG. 7 is a diagram showing timing in the present invention.

FIG. 8 is a diagram showing a schematic configuration of a conventional information processing apparatus.

[Explanation of symbols]

1 ... Memory, 2 ... CPU, 3 ... DMAC, 4 ... Display, 5 ... Display memory, 6 ... Graphics processor, 7 ... Stop control unit, 21 ... Drawing sequencer, 22 ... Mask unit, 23 ... Priority order determining unit, 24 ... Stop status generator, 25 ... Controller, 26 ... Address generator,
27 ... Data processing unit.

Claims (2)

[Claims] 1. Storage means for storing information, first processing means for processing information using the information stored in the storage means, and access to the storage means through the first processing means. An information processing apparatus comprising: a second processing unit to perform; and a unit for detecting an access request signal from the second processing unit to interrupt the processing by the first processing unit. 2. Storage means for storing information, first processing means for processing information using the information stored in the storage means, and access to the storage means through the first processing means. Second processing means for performing, a direct memory access controller for controlling transfer of processing information in place of the second processing means, the direct memory access controller, and the second
And a means for interrupting the processing by the first processing means by detecting an access request signal from the bus connecting the processing means and the first processing means, and the second processing means or the direct memory access controller. An information processing apparatus comprising: