JPH02143364A - Processing priority control method and processor system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of controlling a processor in a computer system, and particularly to improving the processing speed of a processor when there is a large difference between the amount of input data and the amount of output data. The present invention relates to a processing priority control method and processor system suitable for processing.

[Prior Art] Generally, in a processing processor that performs specific data processing such as an image processor that performs encoding processing and decoding processing of image data, input data received via an input buffer is The output data generated through processing is output via the output sofa. As processing progresses, such a processor issues a read request or a write request to a control side such as a control processor, depending on the states of the input buffer and output buffer. The control side blindly responds to this request and outputs a read or write 1- command. If a data read request and a data write request are output at the same time, one of the requests (
For example, the method is based on a lead request).

In addition, related methods of this type include Japanese Patent Application Laid-open No. 5
There are those disclosed in JP 8-88971, JP 58-71768, and the like.

[(Problem that A Ming is trying to solve) In the above processing processor, the operation of the internal data processing block is interrupted or resumed depending on the state of the human cover sofa and the output buffer.For example, when the input buffer becomes empty, , data processing is interrupted because there is no input data to process, and when the output buffer is full, data processing is interrupted to prevent the output data in the output buffer from being destroyed by subsequent output data,
Both are in a waiting state. Data processing in the waiting state reads input data into the input buffer (read)
or after outputting the output data from the output buffer (
6. In a particular processor, the amount of input data and the amount of output data are significantly different, and the magnitude relationship between the two amounts of data changes depending on the processing content.

For example, in the image processor described above, the amount of image data is greater than the amount of code data, so in encoding processing, input data is greater than output data, and conversely, in decoding processing, output data is greater than input data. Therefore, in the decoding process, there is a high possibility that the output buffer will be full, and on the other hand, in the encoding process, the input buffer is likely to be empty.

However, in the above conventional technology, when a read request and a write request are generated from the processor at the same time,
On the other hand, for example, read requests were always prioritized, which was convenient for encoding processing, but not suitable for decoding processing. That is, conventionally, there has been a problem that the processing speed of a processing processor cannot be maximized.

An object of the present invention is to provide a process priority control method that can reduce waiting time due to process interruption and improve processing speed by changing the priority order of operation requests such as read and write depending on the content of the process; Another object of the present invention is to provide a processor system and a control processor for implementing this method.

[Means for Solving the Problems] In order to achieve the above object, a processing priority control method according to the present invention provides a method for controlling processing priority, in which a plurality of operation requests that cannot be executed simultaneously are processed by a processing processor capable of executing a plurality of processings. If these requests occur simultaneously, which one of the plurality of operation requests is given priority is changed depending on the content of the process.

A suitable processor to which the present invention is applied is one in which there is a significant difference in the amount of input data and output data, and the magnitude relationship is reversed depending on the processing content. For example, the image processor executes encoding and decoding of image data, and the plurality of operations that cannot be executed simultaneously are memory read and write operations by the image processor. 6. Processing priority control method according to the present invention can also be applied to a system equipped with a plurality of processing processors and a control processor that controls the operation of the processing processors in response to operation requests from the plurality of processing processors. The priority order when an operation request is issued to the control processor is determined according to the content of processing of each processing processor at the time when the operation request is issued.

Further, a processor system according to the present invention includes a processor capable of executing a plurality of processes, and a control processor that controls the operation of the processor in response to an operation request from the processor. When multiple operation requests occur at the same time, priority determination means determines the priority of each operation request, and the priority determination means determines the priority of the priority determination according to the processing content of the processor at the time when the operation request is generated. The present invention is characterized in that it is provided with priority order changing means for changing the priority order.

The priority determining means and the priority changing means may be provided in the control processor.

The priority order changing means is, for example, a register in which a different value is set depending on the content of processing of the processor, and the priority order determining means is a priority converter whose priority order is controlled by the set value of the register. .

Further, the control processor according to the present invention is a control processor that is used together with a processing processor capable of executing a plurality of processes, and controls the operation of the processing processor in response to an operation request from the processing processor. When multiple operation requests occur at the same time, priority determination means determines the priority of each operation request, and the priority determination means determines the priority order of the priority determination means according to the processing content of the processor at the time when the operation request occurs. The present invention is characterized in that it is provided with priority order changing means for changing the priority order.

According to another aspect, the control processor according to the present invention is a control processor used with a processing processor capable of executing a plurality of processes, and has a latch that holds an operation request flag from the processing processor for a period of time, In a control processor that outputs an operation command to the processor according to the contents of the latch, a register that holds a value according to the processing content of the processor and a register that takes priority when multiple different operation request flags are generated simultaneously from the processor. The present invention is characterized in that it is provided with a priority converter that changes the operation request flag outputted to the first latch in accordance with the value of the register.

[Effect] Hereinafter, typical effects of the present invention will be explained.

In the present invention, the priority order of the control processor's response to the operation request from the processor is changed depending on the content of the processing by the processor. For example, in an image processor, write requests are given priority over read requests in 5 decoding processing, and conversely, read requests are given priority over write requests in encoding processing.

To this end, when executing the decoding process, the priority changing means is set to give priority to write requests, and when executing the encoding process, the same means is set to give priority to read requests. Accordingly, the priority determining means determines the priority according to the settings of the priority changing means when a read request and a write request conflict during data processing by the image processor.

As a result, for example, when open operation requests conflict during decoding processing, the write request is prioritized and the data write command is sent to the image processor, thereby preventing the output buffer from becoming full with a large amount of output data. Prioritize avoidance. Conversely, if open operation requests conflict during encoding processing, a read request is given priority and a data write command is given to the image processor, thereby emptying the input buffer of input data that requires a large amount of processing. Avoid on a priority basis.

In this way, the processing speed of the processor can be maximized and the processing speed of the processor system can be improved.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1st
The figure is a block diagram showing the basic configuration of a multiple processor system according to the present invention.

In FIG. 1, a microprocessor (M, PU) 1 outputs control signals and addresses to the bus, and a memory 2
, the image processor 3 and the control processor 4. Memory 2 is work memory 21
The display memory 22 mainly stores image data to be output to the CRT 5, and the work memory 2]2 stores images generated during processing and data other than images. Processor 3. The three image processors 3 used in the control processor 4 execute decoding processing for converting code data into image data and encoding processing for converting image data into code data. As a configuration for that purpose, the image processor 3 includes a Glock generator 31
, data output bag 32, input data counter 33
．． Output data counter 34, output buffer 35. It consists of an input buffer 36, a data processing block 37, and a control block 38.

The control processor 4 receives the data read request flag or the data write request flag from the image processor 3, and if the flag is data read, writes 2 to the memory 2.
- Then, by outputting an address and a control signal, data is placed on the bus, and a data read command is sent to the image processor 3 to read the data. Further, if the flag is data write, a data write command is given to the image processor 3 to output data to the bus, and the data is transferred to the memory 2. As a configuration for this purpose, the control processor 4 includes a clock generator 41 . Control block 42, latch 442 output buffer 46. It consists of a priority converter control register (priority changing means) 47 and a priority converter (priority determining means) 48.

A flowchart for executing decoding processing or encoding processing using the image processor 3 is shown in FIG. and write LL I II. This I
By writing I I II, the priority converter 48 causes the control block 3 of the image processor 3 to
When both the data read request flag and the data write request flag received from the latch 8 are set, only the data write request flag is output to the latch 44. MPUI
/l in the priority converter control register 47
After writing L tt, a decoding process execution command is given to the control processor 4. In response, the control processor 4 transfers the information from the control block 42 to the image processor 3.
A start command is given to the control block 38 of.

When the image processor 3 receives the activation command from the control processor 4, it outputs a data read request flag from the control block 38 to the control processor 4 in order to input the code data to be processed into the input buffer 36. The control processor 4 receives the data read request flag from the image processor 3 using the priority converter 48 and inputs it to the latch 44 . The control block 42 determines that the output result of the latch 44 is a data read request, and the glock generator 41 synchronizes with the bus operation and outputs the address and control signal to the memory 2, thereby storing the code data. The data is output from the work memory 21 that is currently being used to the bus. At this output point, from the control block 42 to the control block 3 of the image processor 3
Give data read command to 8. The control block 38 is
The clock generator 31 synchronizes with the operation of the bus, and sends the code data output to the bus through the data input/output buffer 32 to the single-person cover sofa 36 (however, the input cover sofa 36 constitutes a FIFO consisting of several stages of lunches). ). At the same time, the input data counter 33 is counted up to count the input data, and it is checked whether the latches constituting the input buffer 36 are empty. In this embodiment, it is determined that the counter is empty until the count value reaches a certain value. After inputting data to the input buffer 36,
The code data is transferred to the data processing block 37, and after decoding, the output buffer 35 (however, the output buffer 36
The image data is also transferred to the FIFO (which also constitutes a FIFO consisting of several stages of latches). At the same time, the output data counter 34 is counted up to check whether the output buffer 35 has overflowed. In this embodiment, when the count value reaches a certain value, it is determined that the tank is full.

The control block 38 checks the overflow of the output sofa and the empty state of the input sofa from the values of the input data counter 33 and the output data counter 34, and sends a data read request flag or a data write request flag to the control processor 4 according to the result. Output.

If an overflow of the output buffer 35 and an empty state of the input buffer sofa 36 occur simultaneously while the image processor 3 is executing a decoding process, the input buffer 36 is
An empty state of 2 means that the latch closest to the data input/output buffer 32 has become empty, and an overflow of the output buffer 35 means that the latch closest to the data input/output buffer 32 has become full.6 Therefore, Code data remains in the input cover sofa 36, but the output buffer 35 is full of image data. Therefore,
By giving priority to the operation of outputting image data from the output sofa 35, the period during which the operation of the data processing block 38 is interrupted is shortened, and the overall processing speed of the image processor 3 is improved. That is, in the above case, control block 3
The data read request flag and the data write request flag are output simultaneously from 8, but the priority converter 4
Since the control block 8 outputs the data write request flag to the latch 44 with priority over the data write request flag, the control block 4
2 gives a data write command to the image processor 3. In addition, it is possible to suppress a decrease in the processing speed of the image processor 3 caused by an overflow of the output buffer 35.

Conversely, in the case of encoding processing, the MPUI writes 0'' to the priority converter control register 47. Therefore, the priority converter 48 receives an input with both the data read request flag and the data write request flag set. In this case, the data read request flag is output to the latch 44 with priority over the data write request flag.

The control processor 4 determines the output result of the latch 44 as a data write request in the control block 42, and writes the output result of the latch 44 to the 1 display memory 22.
It outputs image data to the bus, gives a data read command to the image processor 3, and causes the input buffer 36 to latch the image data. The image processor 3 encodes this image data in a data processing block 37, and then transfers it to an output buffer 35 as code data. At the same time, the values of the input data counter 33 and the output data counter 34 are checked, and the data read request flag or the data read request flag or data read request flag of the control processor 4 is checked.
A request flag is output, but if both flags are output at the same time, the priority converter gives priority to the data read request flag over the data write request flag and latches it to the latch 44.
Output to. Therefore, the control block 42 gives a data read command to the image processor 3 with priority.

It is possible to suppress a decrease in the processing speed of the image processor 3 that occurs when the input buffer 36 is empty.

[Effects of the Invention] According to the present invention, depending on the content of the data processing, it is determined in advance whether the output data will be larger than the input data or the case where the input data will be larger than the output data, and based on the results, processing priority is determined. Since the order is changed, it is possible to shorten the period in which data processing is interrupted and becomes in a waiting state when the input buffer of the processor becomes empty or the output buffer becomes full. Therefore, the processing speed of the processor and, in turn, the processing speed of the entire system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a multi-processor system according to the present invention, and FIG. 2 is a flowchart showing the operation of the processors in the system shown in FIG. 1... Microprocessor (M, PU), 2... Memory, 21... Work memory, 22... Display memory,
3... Image processor, 4... Control processor. 31... Clock generator, 32... Data output cover sofa, 33... Input data counter, 34...
... Output data counter, 35 ... Output sofa, 3
6...Input buffer, 37...Data processing block,
38... Control block, 41... Clock generator, 42... Control block, 44... Latch, 46
. . . Input/output buffer, 47 . . . Priority converter control register, 48 . . . Priority converter. Figure 2

Claims (1)

[Claims] 1. When a plurality of operation requests that cannot be executed simultaneously occur during processing by a processor that can execute multiple processes, which of the plurality of operation requests should be prioritized, A process priority control method characterized in that the priority control method changes depending on the content of the process. 2. The processing processor is an image processor that executes image data encoding processing and decoding processing, and the plurality of operations that cannot be executed simultaneously are memory read and write operations by the image processor. Priority control method for the described processing. 3. In a system having a plurality of processing processors and a control processor that controls the operation of the processing processor in response to an operation request from the plurality of processing processors, an operation request is made from the plurality of processing processors to the control processor at the same time. When a request occurs, the priority is set according to the processing content of each processor at the time the operation request occurs.
A processing priority control method characterized by determining. 4. In a system equipped with a processor capable of executing multiple processes and a control processor that controls the operations of the processor in response to operation requests from the processor, if multiple operation requests are received from the processor at the same time. a priority determining means that determines the priority of each operation request when the operation request occurs; and a priority changing means that changes the priority of the priority determination according to the processing content of the processor at the time when the operation request occurs. A processor system comprising: 5. The processor system according to claim 4, wherein said control processor has said priority determining means and priority changing means. 6. The priority order changing means is a register in which different values are set depending on the content of processing of the processor, and the priority order determining means is a priority converter whose priority order is controlled by the set value of the register. 7. The processor system according to item 5 or 6. 7. A control processor that is used with a processor capable of executing multiple processes and controls the operation of the processor in response to operation requests from the processor, wherein multiple operation requests are generated simultaneously from the processor. a priority determining means that determines the priority of the operation request; and a priority changing means that changes the priority of the priority determining means according to the processing content of the processor at the time when the operation request is generated. A control processor comprising: 8. A control processor used with a processor capable of executing multiple processes, which has a latch that temporarily holds an operation request flag from the processor, and outputs an operation command to the processor according to the contents of the latch. The control processor includes a register that holds a value corresponding to the processing content of the processor, and an operation request flag that is output preferentially to the latch when multiple different operation request flags are generated from the processor at the same time. A control processor comprising a priority converter that changes according to a value in a register.