JPH0526334B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a compound semiconductor device with a planarized element surface and a method for manufacturing the same.

(c) Conventional technology and problems Compound semiconductors such as potassium arsenic (GaAs)
has extremely high mobility, and utilizing this feature, ultra-high-speed semiconductor devices have been developed and put into practical use.

Conventional GaAsFETs are manufactured by forming an n-type epitaxial growth layer on a semi-insulating substrate and then removing unnecessary parts, resulting in unevenness on the element surface, and the shoulders of these unevenness are used for wiring. There was a danger that the wire would break.

In order to solve the above-mentioned problems in GaAs integrated circuit devices (ICs), a method of forming channels using selective ion implantation has been developed, and the surface of GaAs semiconductor elements has been planarized. This has made it possible to miniaturize and highly integrate GaAs semiconductors, and GaAs ultra-high-speed semiconductor devices and high-speed memory devices are being developed.

However, with the conventional structure of a GaAs semiconductor device and its manufacturing method, it cannot be said that flattening of the device surface is fully satisfactory. Below is the conventional
The problems of a GaAs semiconductor device and its manufacturing method will be explained with reference to the drawings.

FIGS. 1a to 1h are cross-sectional views of main parts showing a conventional method of manufacturing a GaAsIC. First, as seen in the same a.
Using the photoresist film 2 selectively formed on the surface of the semi-insulating GaAs substrate 1 as a mask, silicon ions (Si ⁺ ) are implanted at approximately 2×10 ¹² [cm ^-2 ] with an implantation energy of approximately 60 [keV]. A dose of ion implantation is performed to form an n-type layer 3. A portion of this n-type layer 3 will later form a channel layer 3'.

Next, the photoresist film 2 used as the mask was removed, and tungsten silicide (W-
A high-melting point metal such as silicon (Si) is deposited using a magnetron sputtering method, and then selectively removed using a newly formed photoresist film (not shown) as a mask using a reactive ion etching method or the like. Then, a gate electrode 4 that makes a spot contact with the n-type layer 3, and a wiring 5 are formed in a region outside the n-type layer 3 on the surface of the GaAs substrate 1 [FIG. 4b].

Next, after removing the photoresist film, a photoresist film (or silicon dioxide (SiO ₂ ) film) 6 with the n-type layer 3 as an opening is formed again, and using this as a mask, a photoresist film of about 200 [keV] is applied. Si ⁺ at a dose of approximately 2×10 ¹³ [cm ^-2 ] at the implantation energy.
Perform ion implantation. In this way, an n ⁺ source region 7 and a drain region 8 are formed (FIG. 3(c)).

Next, the photoresist film 6 used as the mask was removed, and a silicon dioxide (SiO ₂ ) film (not shown) was deposited by chemical vapor deposition (CVD), and this was used as a protective film at approximately 800°C. about 15
Perform annealing for about 1 minute. Next, the SiO ₂ film used as the above-mentioned protective film is removed, and a SiO ₂ film 9 is formed again [FIG. d]. The steps up to this point remain the same in the present invention, which will be described later.

Next, a photoresist film 10 having wide openings over the source region 7 and drain region 8 is selectively formed on the SiO ₂ film 9, and using this as a mask, the underlying SiO ₂ film 9 is selectively removed. death,
The surfaces of the source region 7 and drain region 8 are exposed [FIG. 3(e)]. In the conventional manufacturing method, as shown in the figure, the wiring 5 is still covered with the SiO ₂ film 9 at the end of this process.

Next, by vapor deposition, a metal such as gold/germanium (AuGe) that forms an ohmic contact with the n-type GaAs crystal and gold (Au) are continuously deposited, and then the photoresist film 10 is removed. AuGe and
A so-called lift-off method is applied to remove the Au layer at the same time.
A source electrode 11 and a drain electrode 12 are formed [simultaneous f].

By making the thickness of the AuGe and Au layers deposited in this step approximately the same as the SiO ₂ film 9 deposited previously, the device surface is The area is flattened.

Next, the SiO ₂ film 9 is selectively removed using a photoresist film (not shown) as a mask, and the wiring 5 is removed.
An opening 13 is provided at the top (see figure g).

Next, a SiO ₂ film 14 is deposited on the entire surface by CVD. Further, in order to form a multilayer wiring, a photoresist film 15 having a predetermined pattern is formed on the SiO ₂ film 14 [FIG. 6h]. The figure shows a wiring 5, a source electrode 11, and a drain electrode 12.
This is an example in which upper layer wiring is formed to connect to each.

Next, as shown in FIG. 2, the upper SiO ₂ film 14 is selectively removed using the photoresist film 15 as a mask. Thereafter, titanium (Ti), platinum (Pt), and gold (Au) are laminated and vapor-deposited, and then selectively removed to form upper layer wiring 16, thereby completing the GaAs integrated circuit device.

In this case, in the configuration shown in FIG. 2, the SiO ₂ film 9 and
The SiO ₂ film 14 has a layered structure except for the source electrode, the drain electrode, and the openings above the lower wiring.

At the same time as the source and drain electrodes are formed, another lower electrode (not shown) is formed on the substrate, for example, between the drain electrode 12 and the lower wiring 5 in FIG. 2. Moreover, if the lower electrode is provided to cross, for example, the upper layer wiring 16, the SiO ₂ film 14 is required to insulate between this upper layer wiring and other lower layer wirings, and the laminated structure of the SiO 2 film 14 and the SiO ₂ film 9 is Is required.

Removed in the process shown in Figure 2 in the above explanation
Since the thickness of all SiO ₂ films is the same, work management is easy. That is, the step of removing the SiO ₂ film 9 on the wiring 5 explained in FIG.
The purpose of this step is to make the amount of etching substantially the same over the entire substrate.

As explained above, various methods have been devised and put into practical use in order to flatten the element surface even in conventional manufacturing methods. However, as mentioned above, an extra etching step is required to form the opening 13, and the photoresist film 15 is
There is a problem in that patterning cannot be aligned with high precision. Furthermore, when forming an upper layer interconnection to connect to the interconnection 5 running on the surface of the semiconductor insulating GaAs substrate 1, the step difference in this part is the sum of the thicknesses of the upper and lower SiO ₂ films 9 and 14.
It becomes quite thick and causes disconnection of the upper layer wiring 16.

As described above, with the conventional structure of a semiconductor device made of a compound semiconductor and its manufacturing method, it is difficult to say that the entire area of the substrate is completely flattened to a satisfactory level, even though the aim is to achieve flattening, and additional steps are required. There was a problem.

(c) Purpose of the Invention The present invention eliminates the above problems, flattens the element surface of a compound semiconductor device, reduces the number of steps,
Another object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent disconnection of upper layer wiring and reduce the resistance of the wiring layer.

(d) Structure of the Invention The above object is to provide a gate electrode and a lower layer wiring selectively formed on the surface of a semi-insulating substrate made of a compound semiconductor on which a source region and a drain region are formed, and a semi-insulating substrate. A lower insulating film covering the surface and having a wide opening over the source region, drain region and lower wiring, and a source electrode, a drain electrode and an interlayer metal formed in the opening so as to be substantially flush with the lower insulating film. an upper insulating film that covers the upper part of the lower insulating film and has connection openings to the source electrode, drain electrode, and interlayer metal wiring; This is achieved by a semiconductor device characterized by having an upper layer wiring connected to a metal wiring, and selectively attaching a gate electrode and a lower layer wiring to the surface of a semi-insulating substrate made of a compound semiconductor on which a source region and a drain region are formed. forming a lower insulating film that covers the surface of the semi-insulating substrate and has a wide opening over the source region, drain region and lower layer line; A step of forming a source electrode, a drain electrode, and an interlayer metal wiring so that the source electrode,
A step of forming an upper layer insulating film having a connection opening on the drain electrode and the interlayer metal wiring, and an upper layer wiring that is deposited on the upper layer insulating film and is connected to the source electrode, the drain electrode, and the interlayer metal wiring through the connection opening. This is realized by a method of manufacturing a semiconductor device characterized by comprising a step of forming a semiconductor device.

(e) Examples of the invention The invention will be further explained based on examples.

FIGS. 3a to 3d are sectional views of main parts in the order of manufacturing steps, illustrating the structure and manufacturing method of the embodiment of the present invention as shown in FIG. 4b.

In the semiconductor device according to the present invention, the lower layer wiring 5 and the interlayer metal wiring 24 are arranged at 5 and 2 in FIG. 4b.
Although the shape is as shown in FIG. 4, in order to simplify the drawings, the shape shown in FIGS. 3A to 3D will be explained. Furthermore, Figure 1d
The steps up to this point are carried out according to conventional manufacturing processes, and the next process will be explained in FIG.

First, as shown in FIG. 3a, a photoresist film 20 having wide openings over the source region 7, drain region 8, and lower layer wiring 5 is formed on the lower layer insulating film (SiO ₂ film in this example) 9. Form. Next, using the photoresist film 20 as a mask, the lower insulating film 9 is selectively removed to form contact windows 21 to 23 as openings. In this embodiment, the contact windows 21 and 22 are thus provided on the source region 7 and the drain region 8, and the contact window 23 is also formed on the lower layer wiring 5 at the same time.

Next, as shown in Figure b, a metal that forms ohmic contact with the n-type GaAs crystal, such as AuGe and Au, is deposited on the entire surface, and then a lift-off method is applied to remove the photoresist film 20 and the ohmic film deposited thereon. Remove the metal layer at the same time.

Thus, the contact window 2 as the opening
Ohmic metal layers are formed on the source electrode 11, the drain electrode 12, and the drain electrode 12, respectively.
and interlayer metal wiring 24 are formed.

Next, the photoresist film 20 used as the mask is removed. In this step, by selecting the thickness of the ohmic metal layer to be approximately equal to the thickness of the lower insulating film 9 made of the SiO ₂ film, the device surface is covered with other areas excluding the gate electrode 4 and the lower wiring 5. is approximately flattened.

Next, as shown in _FIG .
A photoresist film 25 having openings above the source region 7, drain region 8, and lower wiring 5 is formed thereon.

Next, using the photoresist film 25 as a mask, the upper insulating film 14 made of the SiO ₂ film is selectively removed, and contact windows as connection openings are opened above the source electrode 7, drain electrode 8, and interlayer metal wiring 24. . Next, the photoresist film 2
5 is removed, and then titanium (Ti), platinum (Pt),
Gold (Au) is laminated and vapor deposited to form the upper layer wiring 16.
form.

Although this is shown in FIG. 3d, the detailed structure of the present invention regarding the lower layer wiring 5 and the interlayer metal wiring 24 is shown in FIG. 4b, and FIG. 4a shows the circuit arrangement thereof. In particular, in FIG. 4b, which is an enlarged sectional view taken along line B-B in FIG. It is used as. That is, a high melting point metal such as tungsten silicide (W-Si), which is the material of the lower wiring 5, generally has a high resistivity. Therefore, the resistance of the wiring layer is reduced by forming a structure in which interlayer metal wiring 24 is laminated on lower layer wiring 5 made of a high melting point metal. Further, an SiO ₂ film 14 as an upper layer insulating film is formed on the interlayer metal wiring 24, and a lead wiring 16' is formed as a cross wiring on top of the SiO 2 film 14.

In this embodiment, the interlayer metal wiring 24 is made of the same material as the ohmic electrodes such as the source electrode 7 and the drain electrode 8, and is formed in the same process.

(f) Effects of the Invention As explained above, according to the present invention, the step of opening the lower layer insulating film 9 prior to forming the upper layer insulating film 14 is not necessary, and the interlayer metal wiring 24 can be used to form the upper layer wiring. It is possible to reduce the level difference between layers, extremely reduce the risk of wire breakage, make the opening in the upper insulating film for the interlayer metal wiring precise, reduce the resistance of the lower wiring layer, and easily form other wiring that intersects with it. The manufacturing process of a semiconductor device made of a compound semiconductor is simplified, and the reliability and manufacturing yield of the semiconductor device are improved.

[Brief explanation of drawings]

1 and 2 are sectional views of main parts for explaining a conventional semiconductor device and its manufacturing method;
The figures are drawings showing an embodiment of the present invention, where a is an explanatory diagram of the main part of the circuit configuration, b is an explanatory diagram of the main part of the embodiment, and Figs. 3 a to 3 d are explanatory diagrams of the manufacturing method of the invention. It is. In the figure, 1 is a semi-insulating substrate made of a compound semiconductor, 3 is an n-type layer, 3' is a channel layer, 4 is a gate electrode, 5 is a lower wiring made of the same material as the gate electrode 4, 7 is a source region, and 8 is the drain region,
9 is a lower insulating film, 10 is a photoresist film, 11
and 12 are source and drain electrodes, 14 is an upper layer insulating film, 16 and 16' are upper layer wirings, 21 and 2
2 is a contact window as an opening to the source and drain, and 23 is a lower layer wiring 5 opened in the same process as the source and drain contact windows 21 and 22.
A contact window 24 serving as an upward opening indicates an interlayer metal wiring formed using the same material and in the same process as the source and drain electrodes 11 and 12.

Claims (1)

[Scope of Claims] 1. A gate electrode and lower layer wiring selectively formed on the surface of a semi-insulating substrate made of a compound semiconductor on which a source region and a drain region are formed, a source region covering the surface of the semi-insulating substrate, A lower insulating film having a wide opening over the drain region and the lower wiring, a source electrode, a drain electrode, and an interlayer metal wiring formed in the opening so as to be substantially flush with the lower insulating film, and the lower insulating film. An upper insulating film that covers the upper part of the film and has connection openings to the source electrode, drain electrode, and interlayer metal wiring; What is claimed is: 1. A semiconductor device comprising: an upper layer wiring; 2 selectively forming a gate electrode and a lower wiring on the surface of a semi-insulating substrate made of a compound semiconductor on which a source region and a drain region are formed;
A step of forming a lower insulating film covering the surface of the semi-insulating substrate and having an opening that widely opens the source region, drain region and lower layer line, and forming a source electrode in the opening so as to be substantially flush with the lower insulating film. a step of forming a drain electrode and an interlayer metal wiring; a step of forming an upper insulating film that covers the upper part of the lower insulating film and has connection openings to the source electrode, the drain electrode, and the interlayer metal wiring; and a step of forming an upper insulating film on the upper insulating film. 1. A method for manufacturing a semiconductor device, comprising the step of forming an upper layer wiring connected to a source electrode, a drain electrode, and an interlayer metal wiring through a connection opening.