JPS57102014A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS57102014A JPS57102014A JP55178418A JP17841880A JPS57102014A JP S57102014 A JPS57102014 A JP S57102014A JP 55178418 A JP55178418 A JP 55178418A JP 17841880 A JP17841880 A JP 17841880A JP S57102014 A JPS57102014 A JP S57102014A
- Authority
- JP
- Japan
- Prior art keywords
- difference
- level
- film
- hole
- films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
PURPOSE:To form a wiring without disconnection at a portion with difference in level by improving the forming means of a wiring connected to a conductive region through a contact hole. CONSTITUTION:After contact holes 301-303 are opened by selective etching of a CVD-SiO2 film 28, an Al-Si alloy film is formed leaving a resist pattern 29. Then resist films 321'-323' are formed on the holos 301-303 and the exposed alloy film 31 on the pattern 29 is removed by etching using the resist films 321'-323' as masks. Then alloy films 31' are left in the contact holes 301-303 which have steep inside walls opened by RIE method, so that difference in level of the hole can be reduced. After that the hole surface is covered by an Al film 33 and wirings 34-36 without discontinuity by difference in level can be formed to the holes 301-303 by patterning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55178418A JPS57102014A (en) | 1980-12-17 | 1980-12-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55178418A JPS57102014A (en) | 1980-12-17 | 1980-12-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57102014A true JPS57102014A (en) | 1982-06-24 |
Family
ID=16048144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55178418A Pending JPS57102014A (en) | 1980-12-17 | 1980-12-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57102014A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59189678A (en) * | 1983-04-13 | 1984-10-27 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| EP1033757A3 (en) * | 1999-02-04 | 2002-03-06 | Hitachi, Ltd. | Insulated gate bipolar transistor |
-
1980
- 1980-12-17 JP JP55178418A patent/JPS57102014A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59189678A (en) * | 1983-04-13 | 1984-10-27 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| EP1033757A3 (en) * | 1999-02-04 | 2002-03-06 | Hitachi, Ltd. | Insulated gate bipolar transistor |
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