JPH0526351B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a composite insulated gate field effect semiconductor device and a method for manufacturing the same.

[Conventional technology]

In the structure of conventional insulated gate field effect semiconductor devices, channels are generally formed laterally.

In this case, a source and a drain are arranged laterally parallel to the surface of the substrate, and a lateral current flowing between the source and drain is controlled by a gate provided therebetween.

However, using the plasma vapor phase method (using glow or arc discharge), the
When forming a semiconductor using a vapor phase method (hereinafter simply referred to as PCVD) that forms a non-single crystal semiconductor at low temperatures, the semiconductor layer is stacked above the substrate, so channels are formed in the lateral direction. case,
It was impossible to reduce the channel length to 20 to 40 μm or less.

On the other hand, in semiconductors made by PCVD (generally non-single crystal semiconductors), the mobility of carrier electrons or holes is extremely small, 1/10 to 1/10 of that of single crystals, so it is difficult to improve frequency characteristics. In order to
It was essential that the channel length be 2 μm or less, preferably 0.1 to 1 μm.

Non-single crystal semiconductors made by the PCVD method are amorphous semiconductors, semi-amorphous semiconductors with quantum order or microcrystallinity in the size of 5 to 100 Å, or 5~
It is a micro polycrystal with a crystal size of 200 Å, and contains hydrogen or halogen elements such as fluorine.
It is usually added in an amount of 0.01 to 20 mol%.

Even considering that its formation temperature is 200 to 300°C, its density is not as high as that of a single crystal. For this reason, it has been impossible to create precise PN junctions for devices that require a high withstand voltage of 50V or higher.

Furthermore, since it is a thin film element, it has been difficult to realize an element that can handle large currents.

Furthermore, it has been impossible to create a fast-response, photo-responsive, high-output, high-amplification device that has a photosensor function that utilizes light irradiation from the substrate side.

[Problem to be solved by the invention]

An object of the present invention is to obtain an insulated gate field effect semiconductor device that can handle large currents.

[Means to solve the problem]

The present invention relates to an insulated gate field effect semiconductor device, a compound semiconductor device thereof, and a manufacturing method thereof, which uses non-single-crystal semiconductors formed by laminating layers using a plasma vapor phase method. , and the channel length is 0.1 to 3 μm.

The present invention takes into consideration various characteristics of such non-single crystal semiconductors and proposes an insulated gate field effect semiconductor device in which the source and drain are provided vertically in the so-called stacking direction, and the channel expands laterally when a high voltage is applied. It is in.

With such a structure, even when a non-single crystal semiconductor is used, a high current density does not occur at the interface between the channel forming region and the gate insulating film, so it is not necessary to provide a large current power transistor or its integrated structure. It is something that can be done.

The present invention provides an intrinsic or substantially intrinsic semiconductor having a first semiconductor constituting a drain having one conductivity type provided on a substrate or a conductive layer on the substrate, and a channel forming region provided on the semiconductor. the second of
a third semiconductor constituting a source having the same conductivity type as the first semiconductor, which is provided in a convex shape projecting on the semiconductor, and a channel formed in the semiconductor and the second semiconductor. The gist of the present invention is an insulated gate field effect semiconductor device characterized by having a gate insulating film provided covering a formation region and a gate electrode provided on the gate insulating film. forming a first semiconductor having one conductivity type as a drain on a conductive layer on or on a substrate by a plasma vapor deposition method; and forming an intrinsic or substantially intrinsic second semiconductor having a channel formation region on the semiconductor. a step of stacking semiconductors; a step of forming a third semiconductor of the same conductivity type as the first semiconductor on the second semiconductor in a protruding and convex shape as a source; The gist of the present invention is a method for manufacturing an insulated gate field effect semiconductor device, which comprises a step of forming a gate insulating film and a step of forming a gate electrode on the insulating film.

Example 1 An example will be shown below, and the features and technical idea of the present invention will be illustrated with reference to the drawings.

FIG. 1 shows the manufacturing process of a stacked insulated gate field effect semiconductor device using the present invention.

In FIG. 1A, a conductive layer 2 with a thickness of 0.1 to 1 μm is shown on an insulating substrate 1, such as alumina, glass, or glazed ceramics.

In the case of a device that detects light, in order to irradiate and detect optical signals from the substrate side, the substrate should be transparent (glass), and if the conductive layer needs to be transparent, ITO (indium oxide, A tin oxide mixture), tin oxide, or a multilayer film thereof may be used.

Also, in order to make it a so-called power transistor,
Since heat resistance is important, the conductive layer may be formed of heat-resistant chromium, nickel, molybdenum, or the like by a printing method or sputtering method, and stainless steel, aluminum, or other heat-resistant metal may be used as the substrate.

Thereafter, an N ⁺ or P ⁺ type non-single crystal semiconductor 3 was formed on this upper surface by PCVD to a thickness of 0.01 to 1 μm. In this PCVD method, the substrate is placed in a reactor under a pressure of 0.01 to 1 torr, heated from room temperature to 500°C, typically 150 to 350°C, and high-frequency energy is applied using a capacitance or inductive method. It generates plasma glow or arc discharge.

In this way, the semiconductor gases introduced into the reactor, such as silicide gases such as silicon fluoride and silane, decompose and bond, and the recombination centers, which are dangling bonds, are neutralized by hydrogen or halogen elements such as fluorine. A semiconductor layer of a non-single crystal semiconductor is formed. At this time, if 0.01 to 2 mol % of phosphin is added at the same time, an N-type silicon semiconductor layer is obtained, and if diborane is added, a P-type silicon semiconductor layer is obtained.

That is, by adding a gas containing an impurity that imparts a conductivity type to the silicide gas, the conductivity type can be controlled without using thermal diffusion or ion implantation of the impurity.

In this way, N or P non-single crystal semiconductors can be
The first non-single crystal semiconductor layer 3 was formed to a thickness of 1 μm.

Further, on this upper surface, a semiconductor layer 4 having a substantially intrinsic conductivity type and having only so-called background level impurities added with N or P type impurities removed was formed to a thickness of 0.1 to 3 .mu.m.

Although this semiconductor layer is genuine, it is generally N ^- type, so in order to neutralize it, 1 to 10 PPM of B, which is an impurity that imparts P ^- type, is added, making it a so-called intrinsic conductivity type semiconductor. Good too.

Furthermore, this semiconductor is made into a so-called essentially intrinsic semiconductor layer that does not have any impurities added to it.
A P-type semiconductor layer with a thickness of 0.1 to 3 μm is provided on top of the P-type semiconductor layer with a thickness of 0.1 to 3 μm, and a substantially intrinsic semiconductor layer of 0.1 to 1 μm is sandwiched between the P-type semiconductor layers. It may be an intrinsic semiconductor layer containing a semiconductor layer of a conductivity type opposite to that of the first semiconductor layer (that is, in this case, the first semiconductor layer is N type) in the form of an intermediate layer of the second semiconductor. Furthermore, in order to obtain high voltage resistance, if this semiconductor is made of silicon carbide instead of silicon, the voltage resistance can be further improved to 5 to 30V.

Furthermore, a portion of this semiconductor layer close to the first semiconductor layer is made into a substantially intrinsic conductivity type or N ^- layer,
A method of forming a semiconductor layer of an intrinsic conductivity type or a substantially intrinsic conductivity type on its upper surface with electrical conductivity varying in the thickness direction to improve breakdown voltage when the first semiconductor layer 3 is used as a drain. may also be used.

In this way, the second non-single-crystal semiconductor layer 4 having a channel formation region was laminated on the first non-single-crystal semiconductor layer 3.

Furthermore, a third non-single crystal semiconductor 5 was formed on this upper surface in the same manner as the first semiconductor 3, to obtain the state shown in FIG. 1A. This third non-single crystal semiconductor 5
The conductivity type was the same as that of the non-single crystal semiconductor 3.

Thereafter, the third semiconductor was selectively removed, and a gate insulator 8 was further formed on the second and third semiconductors. In this way, the state shown in FIG. 1B was obtained.

FIG. 1B shows such a longitudinal section. In the drawing, the corner portion 15 is slightly deep-etched into the second semiconductor. The gate insulator 8 is made of silicon nitride through a PCVD reaction with silane ammonia.
It is formed with a thickness of 100 to 1000 Å. In addition, the surface of the substrate is heated to 200 to 500°C in an atmosphere containing a halogen element such as chlorine, and oxygen, nitrogen, or ammonia is excited with electromagnetic energy at a frequency of ~3 GHz to plasma oxidize these surfaces. Alternatively, plasma nitridation may be performed.

In addition, the surface of silicon oxide formed after oxidation is
It may be transformed into silicon nitride to a thickness of 50 Å.

100 to carry out such a solid-gas phase plasma reaction.
Since a temperature of ~500°C is required, in such a case, instead of using hydrogen to neutralize the recombination centers of 3, 4, and 5 of the non-single crystal semiconductor, it is better to use fluorine from the viewpoint of heat resistance. I liked it. In this way, the gate insulator 8 was formed to a thickness of 100 to 1500 Å.

Furthermore, semiconductor clusters or thin films may be selectively included in the gate insulator to form a nonvolatile memory.

Furthermore, after forming a window 18 for contact with the third semiconductor 5, a semiconductor layer having the same conductivity type as the source and drain is formed by covering these with a metal such as aluminum by vacuum evaporation or by PCVD. , a gate electrode 9. As a result, as shown in FIG. 1C, a gate insulating film 8 is provided under the gate electrode 9, and a channel forming region 10 is formed thereunder.

Thus, for example, if the third semiconductor 5 is the source and the first semiconductor 3 is the drain, the current flows as indicated by the arrow 1.
1, the current spreads outward once, and then the current flows vertically. Therefore, current does not concentrate at the interface between the gate insulator and the semiconductor, and as a result, even with a non-single-crystal semiconductor having an amorphous or semi-amorphous structure, the interface can be reduced to 0.1~ It is possible to obtain a transistor that can flow a large current of 20A.

Example 2 FIG. 2 shows another embodiment of the invention.

In the drawings, the substrate 1 is a metal substrate made of stainless steel, nickel, molybdenum, or the like. Furthermore, a non-single crystal of N or P type was provided as the first semiconductor layer 3 in ohmic contact with this upper surface. This first semiconductor layer was provided by the same method as the N or P type non-single crystal semiconductor layer (3 in FIG. 1) in Example 1.

Furthermore, a second semiconductor layer 4 constituting a channel formation region was formed on the upper surface to a thickness of 0.1 to 3 μm.

In this embodiment, as shown in the drawings, the first semiconductor layer 3 is an N ⁺ layer, the second semiconductor layer 4 is an N or N ^- layer 25, and an N ^- or I layer. It was constructed as a two-layer structure with a certain 24.

Furthermore, a third semiconductor 5 having the same conductivity type as the first semiconductor 3 was laminated on this upper surface by the PCVD method.

After this, molybdenum, tungsten,
Metal conductive film 6 such as tungsten silicide with a thickness of 0.1 to 1 μm
A silicon oxide insulating film 7 is formed on the film to a thickness of
The layers were laminated to a thickness of 0.3 to 2 μm.

Thereafter, as shown in FIG. 2B, the third semiconductor 5, the conductive layer 6, and the insulator 7 were removed to approximately the same shape by lithography, and the gate insulating film 8 was further formed by the PCVD method.

After obtaining the state shown in FIG. 2B, a hole 18 for an electrode was formed, and a gate electrode 9 made of a metal such as Al or a semiconductor of N ⁺ or P ⁺ was formed.

Then, as shown in FIG. 2C, a gate insulator 8 is formed directly below the gate electrode, and a channel forming region 10 is formed in the second semiconductor layer 4 thereunder.

The current flows from the drain 3 below the source e.g.
, it flows diagonally horizontally as shown at 11.

As is clear from the drawing, a first non-single crystal semiconductor 3 is provided on a conductive substrate 1 in ohmic contact, and a conductive layer 6 is formed on a third semiconductor 5 to reduce its sheet resistance. has been done.

Other manufacturing steps such as the gate insulating film 8 are the same as in Example 1 shown in FIG.

Embodiment 3 FIG. 3 shows an example of the structure of a power transistor using the insulated gate field effect semiconductor device of the present invention.

In the drawings, B is a plan view, and A is a plan view of FIG.
FIG. Numbers and relative positions are shown in correspondence.

In FIG. 3A, a first non-single crystal semiconductor layer 3 of N or P type on a conductive substrate 1 is here used as a drain, and a channel forming region 10 is formed in a second non-single crystal semiconductor 4; A gate insulating film 8 is provided on the upper surface. Further, a third semiconductor 5 and a conductive layer 6 constituting the source are stacked and have the same shape, and a gate electrode 9 is formed to cover the source and the channel forming region.

As is clear from the drawings, the gate electrode is connected to the external lead electrode 19, and the source 5 is connected to the conductive layer 6 and connected to the external lead electrode 21 through the electrode hole 14.

Since this example is a power transistor,
A large current of 0.1 to 10A flows between the source and drain. Therefore, two wires are bonded as shown at 21 in FIG. 3B. This connection may be a face-down bond method.

By adopting such a structure, 20 to 40% of the surface of the non-single crystal semiconductor constitutes the source region, and 60 to 40% of the surface constitutes the source region.
% constitutes the channel forming area, and approximately 20% can constitute the external extraction electrode and surrounding area and scribe line area. For example, a large current of 1 to 20 A at maximum can be extracted from a 5 to 10 mm square element. We were able to obtain an insulated gate field effect semiconductor device that can perform the following steps.

Furthermore, by controlling the thickness of the intrinsic or substantially intrinsic semiconductor 4 and its conductivity,
We were able to obtain a drain breakdown voltage of 200V.

As described above, an insulated gate field effect semiconductor device is provided using a non-single crystal semiconductor, which is stacked on a conductive substrate or conductor layer, instead of using a conventionally known single crystal semiconductor. I was able to get

In addition, by using fluorine as a recombination center neutralizing agent for non-single crystal semiconductors, we were able to raise the upper limit of the process temperature of 300°C, which is the upper limit when hydrogen is used, to 500°C.

Furthermore, when used for optical signal detection from the substrate side, the first semiconductor of the non-single crystal semiconductors is
It is also useful to use silicon carbide having a voltage of ~2.5 eV and to control the wavelength dependence of incident light by using silicon or silicon carbide as the second semiconductor.

In this case, the first semiconductor is SixC _1-X (0<X<
1), it has high voltage resistance against specific waves, and in addition, the second semiconductor
SixGe _1-X (0<X<1) was configured as an infrared sensor.

In addition, using a semi-amorphous semiconductor having microcrystallinity of 5 to 100 Å as a non-single crystal,
In N ⁺ or P ⁺ type semiconductors, the conductivity can be increased to 1 to 100 (Ωcm) ^-1 0.1 to 10 (Ωcm) ^-1 , which is 10 to 10 ³ times higher than that of amorphous semiconductors, which helps reduce sheet resistance. This is extremely preferable. Also, for intrinsic and substantially intrinsic semiconductors,
By suppressing the concentration of oxygen, which is an amorphous agent, to below 10 ¹⁵ cm ^-3 , it is possible to
It is possible to create a so-called semi-amorphous semiconductor in which the crystalline position, which indicates spatial ordering of molecules, changes spatially, with microcrystallinity of ~100 Å. Such a semiconductor exhibits a dark conductivity of 10 ^-8 to 10 ^-4 (Ωcm) ^-1 and an electric conductivity of AM1 (100 mW/
cm ² ), the carrier mobility is ^1/2 to 9×10 ^-2 (Ωcm) ^-1 of single crystal silicon.
This could be improved to 1/30, and the use of the insulated gate field effect semiconductor device of the present invention was extremely effective.

In addition, in this embodiment, the first semiconductor layer is an N ⁺ type as a drain, and the second semiconductor layer on the upper surface thereof is a stacked layer of an N ^- type semiconductor and an I type semiconductor, or an I layer-P ^- layer-I layer. By using a three-layer structure, we were able to reduce reverse leakage and achieve a high breakdown voltage of 50V or more.

〔Effect of the invention〕

By adopting the configuration of the present invention, a configuration in which current does not concentrate at the interface between the channel forming region and the source can be obtained, and an insulated gate field effect semiconductor device that can flow a large current can be obtained. .

[Brief explanation of the drawing]

FIGS. 1 and 2 are longitudinal cross-sections showing the manufacturing process of the insulated gate field effect semiconductor device of the present invention. FIG. 3 shows a longitudinal sectional view and a plan view of a power transistor in which a plurality of semiconductor devices of the present invention are provided on the same substrate.

Claims (1)

[Claims] 1. A first semiconductor constituting a drain having one conductivity type provided on a substrate or a conductive layer on the substrate, and an intrinsic or substantial semiconductor having a channel forming region provided on the semiconductor. a second semiconductor which is essentially intrinsic; a third semiconductor constituting a source having the same conductivity type as the first semiconductor and which is provided in a convex shape protruding above the semiconductor; An insulated gate field effect semiconductor device comprising a gate insulating film provided to cover a channel forming region formed in a semiconductor, and a gate electrode provided on the gate insulating film. 2. A step of forming a first semiconductor having one conductivity type as a drain on the substrate or a conductive layer on the substrate by a plasma vapor phase method, and forming an intrinsic or substantially intrinsic first semiconductor having a channel formation region on the semiconductor. a step of stacking a second semiconductor, a step of forming a third semiconductor of the same conductivity type as the first semiconductor on the second semiconductor in a protruding shape as a source, and a step of stacking the semiconductor and the second semiconductor. 1. A method for manufacturing an insulated gate field effect semiconductor device, comprising the steps of forming a gate insulating film thereon, and forming a gate electrode on the insulating film.