JPH05264659A - Control circuit of delay time generation - Google Patents

Abstract

(57) [Abstract] [Purpose] A high-precision, small delay time that has a small delay time resolution and does not cause deterioration of accuracy or a large increase in the number of elements used even when controlling a large delay time. An object is to provide a generation control circuit. A first delay time generating means 2 having a first delay time resolution including a signal input means S _IN and a restartable oscillator 7 having an adjustable oscillation period, and a second delay smaller than the first delay time resolution. A delay time generation control circuit comprising a second delay time generating means 3 having a time resolution and a delay signal output means DS _OUT for outputting a signal having a predetermined delay time with respect to an input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay time generation control circuit, and more particularly to a delay time generation control circuit used in a semiconductor integrated circuit tester such as an electron beam device or an optical beam sampling device. As described above, the present invention relates to a delay time generation control circuit for generating an output that is a programmable delay of a trigger signal input from the outside.

[0002]

2. Description of the Related Art Conventionally, a delay time generating section of a semiconductor integrated circuit testing apparatus such as an electron beam apparatus or an optical beam sampling apparatus uses a one-shot circuit for generating an analog ramp waveform and an analog comparator, or A method is used in which a plurality of delay lines having different delay times are connected in parallel and a predetermined delay time is obtained by selecting which delay line a signal passes through,
Furthermore, in such a conventional system in which these delay time generation circuits are continuously connected and used as needed,
If the resolution of the delay time is reduced and a large delay time is attempted to be controlled, the accuracy is deteriorated, and the physical size is increased due to the increase in the number of elements used.

[0003]

SUMMARY OF THE INVENTION The object of the present invention is to solve the problems in the prior art, to reduce the resolution of the delay time, and even when controlling the large delay time, the accuracy is deteriorated or the element used is used. An object of the present invention is to provide a highly accurate and small delay time generation control circuit which does not cause a large increase in the number.

[0004]

In order to achieve the above-mentioned object, the present invention adopts the technical constitution as described below. That is, a first delay time generating means having a first delay time resolution including a signal input means and a restartable oscillator having an adjustable oscillation period, and a second delay time resolution having a second delay time resolution smaller than the first delay time resolution. Two
And a delay signal output means for outputting a signal having a predetermined delay time with respect to the input signal.

[0005]

That is, since the delay time generation control circuit according to the present invention adopts the technical configuration as described above, first, the delay time having a relatively large resolution, that is, the rough delay time (first 1 delay time), and then
By generating a short delay time having a resolution smaller than that of the first delay time, that is, a fine delay time in the rough delay time, a delay with a high precision and a fine interval can be efficiently provided. The time can be easily obtained with a simple circuit configuration.

Further, in the delay time generation control circuit according to the present invention, the first delay time generating means for generating the first delay time is the same as the first delay time generating means. The delay time generated is extremely accurate because it has a calibration system that monitors the oscillation cycle of the oscillating circuit to be borne and calibrates the oscillation cycle so that the oscillation cycle is fixed to a predetermined cycle. is there.

The configuration of the present invention will be described more specifically.
For example, a delay time generation control method is used in which a rough delay time is generated using a restartable oscillator and a counter that include a variable voltage delay element in the loop, and a fine delay time generation unit is added in the subsequent stage. The oscillation cycle of thetable oscillator is monitored by a highly accurate cycle measuring device such as a frequency counter, and the variable voltage delay element in the loop of the restartable oscillator is maintained at a predetermined cycle based on the monitoring result. It is possible to generate a stable and highly accurate delay time in a wide delay range.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of the delay time generation control circuit according to the present invention will be described in detail below with reference to the drawings. Figure 1
3 is a block diagram showing a configuration of a specific example of a delay time generation control circuit according to the present invention, in which a first delay time including a signal input means S _IN and a restartable oscillator 7 whose oscillation cycle is adjustable, A first delay time generating means 2 having a resolution and a second delay time smaller than the first delay time resolution
The delay time generation control circuit 1 is composed of the second delay time generation means 3 having the delay time resolution and the delay signal output means DS _OUT for outputting a signal having a predetermined delay time with respect to the input signal. It is shown.

The restartable oscillator 7 used in the present invention is also called a retriggerable oscillator. Normally, a test trigger is input to the restartable oscillator 7 so that The provided oscillating device continues to oscillate and outputs a pulse signal of a predetermined cycle. However, an external device is connected to the delay time generation control circuit 1, and the delay time generation control is performed from the external device. When an external trigger is input to the circuit 1, the first delay time generation means 2 temporarily stops the pulse signal that has been generated until then, and responds to the external trigger to change the phase of the external trigger pulse. It is preferable to have a function of starting re-oscillation with a synchronized phase.

Therefore, in the specific example according to the present invention,
After the signal input means S _IN , there is provided a trigger selection circuit 5 for selectively taking in a test trigger (TEST) output from the arithmetic control circuit 4 and an external trigger into the delay time generation control circuit 1. The trigger selection circuit 5 receives an appropriate command from the arithmetic control circuit 4 and selects a predetermined trigger pulse.

Further, in a specific example of the present invention, a trigger pulse signal set to a predetermined width in response to an external trigger input is provided between the trigger selection circuit 5 and the restartable oscillator 7. The pulse width limiting means 6 for generating is provided. The trigger pulse generated by the pulse width limiting means 6 temporarily stops the pulse having a predetermined cycle generated in the restartable oscillator, and the pulse is reset in synchronization with the external trigger. It is desirable that the width is set so that you can start.

The pulse width limiting circuit 6 is a trigger selection circuit 5
This is a part where the trigger signal sent from the device has a constant pulse width. This pulse width is determined to be a constant value larger than the oscillation cycle of the restartable oscillator 7 in the next stage. The restartable oscillator 7 constituting the first delay time generating means 2 according to the present invention preferably has a voltage variable type oscillating means, for example, a voltage variable type delay element, inside thereof. The cycle is adjusted to a predetermined frequency by using the restartable oscillator.

Further, the restartable oscillator 7 of the first delay time generating means 2 according to the present invention further includes a frequency counter 9, a digital / analog converting means 8 and the like, and a cycle calibration circuit for the restartable oscillator. System 2
Forming 0. The calibration circuit system 20 has a possibility that the oscillation cycle of the restartable oscillator 7 may fluctuate due to temperature changes and the like.
Is monitored by the frequency counter 9, and the result is compared with a set frequency provided in a suitable memory of the arithmetic control processing means 4, and the output value of the frequency counter 10 and the set frequency are different from each other. For example, a voltage corresponding to the difference is generated and fed back to the restartable oscillator 7 via the digital / analog conversion means 8.

Further, in the delay time generation control circuit 1 according to the present invention, as described above, the first delay time generating means 2 further counts the output pulses from the restartable oscillator 7. Counter 10 and the counter 10
A first delay composed of a digital comparator or the like, which compares the count value from the counter with a predetermined value and generates a first delay time detection signal when the count value matches the predetermined value. There is provided time detection signal generation means 11 and first delay time setting means 12 for outputting a logical product of the output pulse output from the restartable oscillator 7 in response to the first delay time detection signal. is doing.

Therefore, in the present invention, the first delay time detection signal and the output pulse output from the restartable oscillator 7 are logically ANDed and correspond to the first delay time setting data. Only the pulse delayed by the time is sent to the second delay time generating means 3 which will be described later, and the final delay signal is output with a delay corresponding to the second delay time setting data designated by the arithmetic control circuit. ..

The second delay time generation means 3 used in the delay time generation control circuit according to the present invention is connected to the first delay time generation means 2 and the first delay time is generated. The first delay time generating means 2 has a delay time resolution smaller than the delay time resolution that can be generated by the time generating means 2.
It is preferable that the delay time can be set arbitrarily within the range of the delay time resolution, and the structure is not particularly limited, and any delay time generating means that has been used conventionally can be used. Any structure can be adopted.

According to the present invention, the rough delay time generating section and the fine delay time generating section are divided, and since the rough delay time generating section is composed of the restartable voltage controlled oscillator circuit, the counter and the comparator, a large delay is generated. To obtain the time, it suffices to increase the number of digits of the counter, and when trying to obtain the same large delay time, the physical size can be made significantly smaller than the conventional one.

A more detailed circuit configuration of the delay time generation control circuit according to the present invention will be described below with reference to FIG. 2, the same members as those in FIG. 1 are designated by the same reference numerals as those in FIG. The trigger selection circuit 5 is
It is a multiplexer, and the TEST trigger and the external trigger sent from the arithmetic control circuit 4 are input to the trigger selection circuit 5, and which trigger is made valid by switching the trigger selection signal by the arithmetic control circuit 4. You can choose.

When actually measuring with the electron beam device or the optical beam sampling device, an external trigger is selected, and a trigger signal synchronized with the operation of the DUT to be measured is input to this external trigger. As shown in FIG. 2, the pulse width limiting circuit 6 "includes a D-flip-flop FF2,
It is composed of delay lines 61 and 62, an AND gate 64, and a NAND gate 63, and outputs a selected trigger signal with a constant pulse width. This pulse width is a pulse having a constant width slightly larger than the cycle of the oscillation output of the first delay time generating means generated by the restartable oscillator so that the restartable oscillator 7 in the subsequent stage can restart the oscillation in synchronization with the trigger signal. Is output as. In this portion, the NAND gate 63 also simultaneously generates a counter clear signal of the first delay time generation counter.

In the restartable oscillator 7, when a trigger signal having a constant pulse width is input, a delay line 72 and a varicap 71 inserted in a feedback loop.
The oscillation is restarted in synchronization with the trigger signal at a constant cycle controlled by the oscillation cycle control voltage applied to the.
The cycle of the first delay time generating oscillation output is measured by the frequency counter 9, and is controlled to be a predetermined cycle by changing the oscillation cycle control voltage of the varicap 71 through the arithmetic control circuit 4. .. This fixed period is the time resolution of the delay time generated by the first delay time generating means, and the delay below this value is controlled by the second delay time generating means in the subsequent stage.

The operation timing waveforms of the input and output of the restartable oscillator 7 in the delay time generation control circuit according to the present invention are illustrated in FIG. The first delay time generation counter 10 counts the number of pulses of the oscillation output of the first delay time generation means, and when the count value matches the first delay time data preset by the arithmetic control circuit 4, the digital comparator. At 11, a rough delay detection signal corresponding to the first delay time resolution is generated.

The first delay time generation counter 10 according to the present invention is composed of counter elements 91 to 93 as shown in the drawing. This detection signal is the AND gate circuit 12
Is ANDed with the first delay time generating oscillation output means from the restartable oscillator 7 and is input to the second delay time generating circuit 32 and the one-shot circuit 31 constituting the second delay time generating means 3. To be done.

In the present invention, this detection signal is slightly delayed by the oscillation output means for generating the first delay time from the restartable oscillator 7 because the first delay time generation which generated the first delay time detection signal is generated. This is for the purpose of retiming the oscillation output pulse of the counter. Further, the one-shot circuit 31 is for resetting D-FF of the pulse width limiting circuit 6 so that the next trigger signal can be accepted.

The second delay time generating circuit 32 is a part for controlling the delay of the designed oscillation period of the restartable oscillator 7 or less, and the input is delayed by the second delay time data set by the arithmetic control circuit 4. The final delayed output signal is output. The second delay time generation circuit 32 uses a one-shot circuit for generating an analog ramp waveform and an analog comparator as in the conventional case, or a plurality of delay lines having different delay times are connected in parallel, A method of obtaining a predetermined delay time by selecting which delay line a signal passes through is adopted, and these delay time generation circuits are continuously connected in series as necessary.

[0025]

As described above, according to the present invention, the rough delay time generating section is divided into the fine delay time generating section, and the rough delay time generating section is composed of the restartable voltage controlled oscillator circuit, the counter and the comparator. Therefore, in order to obtain a large delay time, it suffices to increase the number of digits of the counter, and when trying to obtain the same large delay time, the physical size can be greatly reduced compared to the conventional case.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a delay time generation control circuit according to the present invention.

FIG. 2 is a block diagram illustrating a detailed circuit configuration of the delay time generation control circuit shown in FIG.

FIG. 3 is a diagram showing an example of a conventional delay time generation circuit.

FIG. 4 is a timing waveform diagram for explaining the input / output operation of the restartable oscillator 7 of the delay time generation control circuit according to the present invention.

[Description of Reference Signs] 1 ... Delay time generation control circuit 2 ... First delay time generation means 3 ... Second delay time generation means 4 ... Calculation control means 5 ... Trigger selection means 6 ... Pulse width limiting means 7 ... Resterable Oscillator 8 ... Analog / digital converter 9 ... Frequency counter 10 ... First delay time generation counter 10 11 ... First delay time detection signal generating means 12 ... First delay time setting means 20 ... Calibration system

Claims (10)

[Claims] 1. A first delay time generating means having a first delay time resolution including a signal input means and a restartable oscillator having an adjustable oscillation period, and a second delay time resolution smaller than the first delay time resolution. And a delay signal output means for outputting a signal having a predetermined delay time with respect to an input signal. 2. The restartable oscillator constituting the first delay time generating means is characterized in that its cycle is adjusted to a predetermined frequency by using a voltage variable type oscillating means. 2. The delay time generation control circuit described in 1. 3. The delay time according to claim 2, wherein the restartable oscillator further includes a frequency counter and a digital / analog conversion means to form a calibration system for the period of the restartable oscillator. Generation control circuit. 4. The restartable oscillator is configured to restart in synchronization with the input of the external trigger signal when an external trigger is input. Delay time generation control circuit. 5. A pulse width limiting means for generating a trigger pulse signal having a predetermined width in response to an input of an external trigger is provided between the signal input means and the restartable oscillator. 5. The delay time generation control circuit according to claim 4. 6. The trigger pulse generated by the pulse width limiting means temporarily stops the pulse having a predetermined cycle generated in the restartable oscillator, and synchronizes with the external trigger. 6. The delay time generation control circuit according to claim 5, wherein the width is set so that the pulse can be restarted. 7. The first delay time generating means further compares a counter for counting output pulses from the restartable oscillator with a count value from the counter, and compares the count value with a predetermined value. A first delay time detection signal is generated when the count value matches the predetermined value.
The delay time detection signal generating means and the first delay time setting means for outputting the output pulse output from the restartable oscillator in response to the first delay time detection signal. The delay time generation control circuit according to any one of claims 1 to 6, which is characterized in that. 8. The second delay time generating means is connected to the first delay time generating means, and has a delay time smaller than a delay time resolution that can be generated by the first delay time generating means. 8. A structure having a resolution, capable of generating a delay time within the range of the delay time resolution of said first delay time generating means, and being capable of arbitrarily setting the delay time. The described delay time generation control circuit. 9. A test trigger for determining the function of the first delay time generating means is input to the signal input means of the first delay time generating means, in addition to the external trigger. The delay time generation control circuit according to claim 1, characterized in that there is one. 10. The signal input means is provided with trigger selection means for selecting the test trigger and the external trigger and supplying them to the first delay time generation means. The delay time generation control circuit according to claim 9.