JPH05266588A - Playback device - Google Patents

Abstract

PURPOSE:To reduce quantization errors at the time of generating a signal from a recording medium and to stabilize an information reproduction by calculating a difference between a detecting signal and a reference value and changing the reference value in accordance with this difference. CONSTITUTION:Output signals from adders, 30a and 30b are supplied to a signal processing circuit 19 at the time of focusing and tracking and image information and address information are reproduced. The circuit 19 is provided with a demodulation circuit 42 for transforming a reproducing signal into a signal level and a 2-7 code or a level synchronous code at the interval between changing points and a demodulation circuit 43 for obtaining the reproducing signal demodulating them. The reproducing signal for the 2-7 code is stably quantized into a multilevel signal by the circuit 42 synchronizing the quantizing level synchronous code at the time of starting a reproduction. That is, even when a reproducing signal modulation is reduced because of dust and flaws on the substrate surface of a recording medium 1 and the reproducing signal modulation is changed because of a change of the recording sense of a recording film, it is quantized into the multi level signal stably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus such as an optical disk apparatus for reproducing information recorded on an optical disk.

[0002]

2. Description of the Related Art Conventionally, when reproducing information recorded on an optical disk as a recording medium, a reference level for quantizing a signal obtained from the optical disk or a magnitude of a gain of a reproduced signal obtained from the optical disk is It is fixed.

Therefore, when dust or scratches are present on the substrate surface of the optical disk, or when the recording film of the optical disk has uneven sensitivity and sufficient recording is not performed under the same recording conditions, a signal is reproduced from the optical disk. When the signal level decreases.

Therefore, since the reference level for quantizing and the gain of the reproduced signal are fixed, there is a problem that quantization error occurs during signal reproduction and an information reproduction error occurs. Therefore, the present invention can reduce quantization errors at the time of signal reproduction and can stably reproduce information.

[0005]

Conventionally, since the reference level for quantizing and the gain of the reproduced signal are fixed, quantization error occurs during signal reproduction, resulting in information reproduction error. There's a problem.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a reproducing apparatus capable of reducing quantization errors when reproducing a signal from a recording medium and stably reproducing information. And

[0007]

The reproducing apparatus of the present invention comprises:
An information signal on a recording medium in which information is reproduced from a recording medium having a level synchronization code recording area in which a level synchronization code of a constant recording level is stored and an information signal recording area in which an information signal is stored. Detection means for detecting the information signal stored in the recording area and the level synchronization code stored in the level synchronization code recording area on the recording medium; reference value generating means for generating a reference value;
First processing means for comparing the detection signal from the detection means with the reference value from the reference value generation means and quantizing the signal according to the comparison result, and the quantization result from the first processing means. Conversion means for converting the detection signal of the detection means into a binarized signal sequence, calculation means for calculating the difference between the detection signal from the detection means and the reference value from the reference value generation means, and this calculation The second processing means changes the value of the reference value generated by the reference value generating means in accordance with the difference calculated by the means.

[0008]

According to the present invention, in reproducing information from a recording medium having a level synchronization code recording area in which a level synchronization code of a constant recording level is stored and an information signal recording area in which an information signal is stored, The detection means detects the information signal stored in the information signal recording area on the recording medium and the level synchronization code stored in the level synchronization code recording area on the recording medium, and generates the detection signal and the reference value. The reference value from the means is compared, the signal is quantized according to the result of the comparison, the detection signal of the detection means is converted into a binary signal sequence according to the result of the quantization, and the detection signal from the detection means is detected. The difference between the signal and the reference value from the reference value generating means is calculated, and the value of the reference value generated from the reference value generating means is changed according to the calculated difference.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a disk device. The recording medium 1 is rotated by a motor 2 at a constant speed, for example. This motor 2 has a motor control circuit 1
Controlled by 8.

The optical head 3 records and reproduces information on and from the recording medium 1. This optical head 3
Is the drive coil 1 that constitutes the movable part of the linear motor 31.
The drive coil 13 is connected to the linear motor control circuit 17.

In the recording medium 1, a level synchronization code recording area is provided at the beginning of each track, each sector, or each block, and an information signal recording area is provided following this level synchronization code recording area. There is. A modulation signal corresponding to a level synchronization code for setting a variable level during reproduction is recorded in the level synchronization code recording area.

Although the recording medium 1 uses a recording film for forming pits by punching,
A recording film using a phase change or a multilayer recording film may be used, or a magneto-optical disk or the like may be used as a recording medium. In the above case, the configurations of the optical head and the like are similarly changed.

A linear motor position detector 26 is connected to the linear motor control circuit 17, and the linear motor position detector 26 detects the position of the position by detecting the optical scale 25 provided on the optical head 3. It is designed to output a signal.

A permanent magnet (not shown) is provided on the fixed portion of the linear motor 31, and the drive coil 13 is provided.
Is excited by the linear motor control circuit 17, the optical head 3 is moved in the radial direction of the recording medium 1.

An objective lens 6 is held on the optical head 3 by a wire or a leaf spring (not shown). The objective lens 6 is moved by a driving coil 5 in the focusing direction (optical axis direction of the lens) and driven. The coil 4 allows movement in the tracking direction (direction orthogonal to the optical axis of the lens).

The laser light generated by the semiconductor laser oscillator 9 driven by the laser control circuit 14 is
The recording medium 1 is irradiated through the collimator lens 11a, the half prism 11b, and the objective lens 6, and the reflected light from this recording medium 1 is the objective lens 6 and the half prism 1.
The light is guided to the photodetector 8 via the lens 1b, the condenser lens 10a, and the cylindrical lens 10b. The photodetector 8
Is composed of four divided photodetection cells 8a, 8b, 8c and 8d.

The output signal of the photodetector cell 8a of the photodetector 8 is supplied to one end of the adders 30a and 30c via the amplifier 12a, and the output signal of the photodetector cell 8b is supplied to the amplifier 1.
2b is supplied to one end of the adders 30b and 30d,
The output signal of the photodetection cell 8c is supplied to the other ends of the adders 30b and 30c via the amplifier 12c, and the photodetection cell 8d
Of the output signal of the adder 30a, 3a through the amplifier 12d.
It is supplied to the other end of 0d.

The output signal of the adder 30a is supplied to the inverting input terminal of the differential amplifier OP1.
The output signal of the adder 30b is supplied to the non-inverting input terminal of. As a result, the differential amplifier OP1 supplies the track difference signal to the tracking control circuit 16 according to the difference between the adders 30a and 30b. The tracking control circuit 16 creates a track drive signal according to the track difference signal supplied from OP1.

The track drive signal output from the tracking control circuit 16 is supplied to the drive coil 4 in the tracking direction. Further, the track difference signal used in the tracking control circuit 16 is supplied to the linear motor control circuit 17.

The output signal of the adder 30c is supplied to the inverting input terminal of the differential amplifier OP2, and the output signal of the adder 30d is supplied to the non-inverting input terminal of the differential amplifier OP2. As a result, the differential amplifier OP2 supplies a signal regarding the focus point to the focusing control circuit 15 according to the difference between the adders 30c and 30d. The output signal of the focusing control circuit 15 is supplied to the focusing drive coil 5 and is controlled so that the laser light is always in perfect focus on the recording medium 1.

Each photodetecting cell 8a of the photodetector 8 in the state where focusing and tracking are performed as described above.
The sum signal of the outputs of 8d, that is, the output signals from the adders 30a and 30b, reflect the change in the reflectance from the pits (recording information) formed on the track. This signal is supplied to the signal processing circuit 19, and this signal processing circuit 1
In 9, the image information and the address information (track number, sector number, etc.) are reproduced.

Further, a recording signal forming circuit 44 is provided in the preceding stage of the laser control circuit 14. The recording signal generation circuit 44 includes a modulation circuit 40 that converts (modulates) the recording signal by the 2-7 code conversion method, and 2-7 from the modulation circuit 40.
A storage buffer 47 for storing a code, a level synchronization code generation circuit 48 for generating a level synchronization code for recording at a constant recording level, and a storage buffer 47
A switching circuit 49 for selectively switching and outputting the 7-code or the level-sync code from the level-sync code generator 48 according to a timing signal from the CPU 23, and the 2-7 code or the level-sync code from the switch circuit 49 is a multi-valued signal. The signal processing circuit 19 has a modulation circuit 41 for changing the interval between the switching of the level and the change of the signal level, and the signal processing circuit 19 provides the reproduction signal with the interval between the switching of the signal level and the switching of the signal level change. 2-7 code or level synchronization code by the demodulation circuit 42, the demodulation circuit 42
It has a demodulation circuit 43 which obtains a reproduction signal by inversely converting (demodulating) the 2-7 code from.

Modulation circuit 4 for the level synchronization code
The modulated signal of No. 1 is recorded in the level synchronization code recording area of the recording medium 1, and the modulation circuit 4 for the 2-7 code is recorded.
The modulated signal of No. 1 is recorded in the information signal recording area of the recording medium 1.

The demodulation circuit 42 synchronizes the quantization level according to the reproduction signal (see the left side of FIG. 2) corresponding to the level synchronization code, which is obtained at the time of starting the reproduction, to thereby obtain the 2-7 code. The reproduced signal (see the right side of FIG. 2) can be stably quantized into a multilevel signal.

That is, even if the substrate surface of the recording medium 1 has dust or scratches and the degree of modulation of the reproduced signal is lowered, or the recording sensitivity of the recording curtain is changed to change the degree of modulation of the reproduced signal,
It is possible to stably quantize into a multilevel signal.

The reproduction signal (reproduction information) reproduced by the signal processing circuit 19 is output to the recording medium control device 46 as an external device through the interface circuit 45.

As described above, the signal processing circuit 19 and the recording signal generating circuit 44 include the modulation circuit 40 and the demodulation circuit 43 for the 1-7 code and the 2-7 code, but this is not always necessary. , Through interface circuit 70 2
The value signal sequence can be directly modulated or demodulated into a multilevel signal.

Further, in this disk device, a focusing control circuit 15, a tracking control circuit 16,
A D / A converter 22 used for exchanging information between the linear motor control circuit 17 and the CPU 23 is provided.

Further, the tracking control circuit 16 is
The objective lens 6 is moved in accordance with the track jump signal supplied from the CPU 23 via the D / A converter 22, and the beam light is moved by one track.

The above laser control circuit 14, focusing control circuit 15, tracking control circuit 16, linear motor control circuit 17, motor control circuit 18, signal processing circuit 1
9. The recording signal generating circuit 44 and the like are controlled by the CPU 23 via the bus line 20, and the CPU 23 is adapted to perform a predetermined operation by a program stored in the memory 24.

The demodulation circuit 42 of the present invention is a multi-level signal from the recording medium 1 as shown in FIG.
2a of the reproduced signal obtained from the outputs from 0a and 30b)
It returns to the binarized signal sequence, and as shown in FIG. 4, the signal waveform conversion unit 51 and the signal level switching timing detection unit 5
2, a multi-level level determination unit 53, and a signal synthesis unit 54. The signal waveform conversion section 51 corrects the signal waveform of the supplied reproduction signal so that signal detection and signal processing can be easily performed. It removes a noise component having a frequency higher than necessary or, conversely, amplifies only a frequency component including a signal component.

The signal level switching timing detector 5
2 detects the switching timing of the signal level of the reproduction signal. The multilevel level determination unit 53 determines the multilevel level of the reproduction signal corrected by the signal waveform conversion unit 51 in accordance with the detection of the switching timing from the signal level switching timing detection unit 52. Is. The signal synthesizing unit 54 synthesizes the binarized signal sequence in accordance with the determination result of the multilevel level determining unit 53.

Further, the modulation circuit 41 for the demodulation circuit 42 has the information of the binarized signal sequence in the signal level or the signal level change amount and the information in the interval of the changeover of the signal level change. The signal is generated in accordance with the information, and as shown in FIG. 5, it is configured by a modulation signal generation unit 61, a signal level switching timing generation unit 62, and a multilevel level value determination unit 63. There is.

The modulated signal creating section 61 divides the information contained in the binarized signal sequence into information to be given to the signal level or the amount of change in the signal level and information to be given to the interval between the changeovers of the signal level. is there. The signal level switching timing creation unit 62 creates the signal level switching timing based on the modulation signal from the modulation signal creation unit 61. The multilevel level value determination unit 63 determines a signal level designating voltage as a multilevel level value based on the modulation signal from the modulation signal generation unit 61 and the switching timing from the signal level switching timing generation unit 62. Is. The laser control circuit 14 is operated by the laser drive signal corresponding to the multi-valued level value from the multi-valued level value determining unit 63.

A modulation method for converting the binarized signal sequence into a multilevel signal by the modulation circuit 42 will be described with reference to FIG. The maximum possible recording density when a 2-7 code signal is recorded on the recording medium 1 is an interval of "2" (1.5T interval).
On the other hand, the wind margin is often relatively wide due to restrictions imposed by how closely the pit pitch interval can be physically recorded on the recording medium 1. Therefore, it is a feature of the embodiment shown in FIG. 3 that the minimum pit pitch relative to the reference period T is widened by utilizing multilevel recording.
In the case of a 2-7 code signal before modulation into a multi-level signal, if the number of “0” s continuing is n (2 ≦ n ≦ 7), then n ≦ 4; Quantized signal level change amount 1 Level change amount Signal level change changeover interval n + 3 When n ≧ 5; Quantized signal level change amount 2 level change amount Multilevel signal with signal level change changeover interval n Convert (modulate).

That is, in the 2-7 code signal, where the interval of "0" is wide, the interval is left as it is, and when the interval of "0" is narrow, the interval of "0" is widened by using the multilevel signal. Further, the number L of levels at this time is set to three values (L = 3) in the embodiment shown in FIG.

With respect to the 2-7 code signal as shown in FIG. 3A, the number of "0" is examined as shown in FIG. 3B, and the quantized signal level changes according to the above rule. The switching interval between the amount and the signal level change is set ((c) in FIG. 3).
In the embodiment of FIG. 3, the amount of change in signal level is used for information.

Therefore, the signal level value after the change is shown in FIG.
It corresponds to the value of the first digit when the cumulative value when the change amounts are sequentially added as shown in (d) is expressed by the L-adic system (the ternary system in FIG. 3). As a result, the reproduced signal (obtained by the outputs of the adders 30a and 30b) when the information is recorded on the recording medium 1 is as shown in FIG.

A configuration example of the modulation circuit 41 for realizing the above-described modulation method will be described with reference to FIG. The modulated signal creating unit 61 includes a RAM 110, an addressing counter 111, shift registers 112 and 122, and a counter 1.
13, 114, inverters 115, 119 and 121, and gate circuits 116, 117, 118 and 120.

The signal level switching timing creation unit 6
2 includes a shift register 122, a gate circuit 123, and a flip-flop circuit 124. The multilevel level value determination unit 63 includes the adders 125, 2
It is composed of a ROM 126 for conversion from hex to ternary and a D / A converter 127.

The point of the modulation circuit 41 having such a configuration is that the multi-level level value determining unit 63 uses the adder 125 to convert the signal information into a signal level change amount, and the modulation signal creating unit 61 uses the shift register 112. There are two points in which the timing of the signal is changed by stopping the reference clock when transferring the signal.

First, the data of the binarized signal sequence (2-7 code) is stored in the RAM 110. The data is sequentially taken out using the shift registers 112 and 122. 2-7
“1” of the code signal sequence is Q of the shift register 122
When it comes to H, it is judged whether or not there is a "1" in the subsequent 5 bits, and if there is, it is "01" (the signal level change amount is 1 and the embodiment of FIG. Then, the signal level addition amount is set to “1” and is input to the adder 125 via the flip-flop circuit 124. Further, when there is no “1” in 5 bits, “10” (the signal level addition amount is 2 ) Is input to the adder 125.

In the adder 125, the state before addition is input to the terminals B1 and B2. The value after addition corresponds to the level number L and is stored in the L-adic number (in the case of FIG. 6, the ternary number) in the ROM.
D / A converter 127 after conversion via 126
Is used to set the recording power.

When "1" of the signal sequence of 2-7 code comes to QH of the shift register 122, if there is no "1" in the subsequent 5 bits, the timing of the signal level switching eye is as it is. Used. On the other hand, when the next "1" comes in the subsequent 5 bits, the data transfer from the RAM 110 is stopped for 3 clocks to widen the interval until the next "1" comes.

The counter 114 normally has QA = QB = “0”.
Has stopped. Envelope terminal EN is "0"
Then, counting is started, and the counting is continued until the state of QA = QB = “0” again.

Next, a configuration example of the demodulation circuit 42 shown in FIG. 4 will be described with reference to FIG. The signal level switching timing detection section 52 is composed of a timing detection amplifier 130 and an absolute value circuit 131. The multilevel level determination unit 53 includes analog switches 132, 13
5, reference signal generator 133, level addition value detection circuit 13
4, a sample hold circuit 136, a mono multivibrator 137, and a shift register 138. The signal synthesizer 54 includes the quantizer 13
9, ROM 140, inverter 141, gate circuit 14
2, 143, 144, timing adjustment counter 14
5, shift register 146, and RAM 147.

The major points of the demodulation circuit 42 having such a configuration are that the amount of change in the reproduced signal after quantization is D, the number of levels is L, and the signal information value due to the signal level change (at the signal level change position during modulation). When the level added value) is Ad, the value of Ad is obtained using the relationship that the value of Ad = “L + D” is the value of the first digit when displayed in the L-adic number system. The shift of the shift register is temporarily stopped in accordance with the obtained Ad value to match the signal timing. There is a place to say.

First, the function of the signal level switching timing detector 52 will be described. Signal waveform converter 5
The signal passing 1 is input to the inverting terminal side 130a of the timing detection amplifier 130, and the signal whose response is slightly delayed is input to the non-inverting terminal 130b. The relationship between the two signal waveforms is as shown in FIG. This Figure 8
As can be seen from (a), the difference between the two values becomes large at the signal level switching point.

If this difference exceeds a certain range, the diode D1 or D2 attached to the timing detection amplifier 130 is short-circuited, and the timing detection amplifier 130 is in a short circuit state.
The gain of suddenly increases. As a result, the output of the timing detection amplifier 130 has a pulse-like shape.

Further, by passing the signal through the absolute value circuit 131, a waveform as shown in FIG. 8B can be obtained. Using this signal, the mono-multivibrator 137 creates a pulse corresponding to one clock of the reference clock. This pulse passes through the shift registers 138 and 146 to RAM1.
Recorded at 47.

Meanwhile, this pulse is transmitted to the shift register 1
When passing through QB of 38, the signal level switching amount is detected by the level addition value detection circuit 134 at the timing of (b) of FIG.
9C, the sample hold circuit 136 samples and holds the signal before the switching for comparison at the next signal level switching at the timing of (c) in FIG. 9A shows the signal waveform immediately after passing through the signal waveform converter 51, and the size of the hatched arrow indicates the level change amount due to the signal level switching.

As is apparent from FIG. 3, when the signal level amount increases, the increase amount directly represents the signal information value (level addition value at the signal level change position during modulation) Ad due to the signal level change. When the signal level amount is decreasing, "3-reduction amount" represents the signal information value Ad. If this relationship is generalized, there is a relationship of Ad = L + D (however, the value of the first digit of the L-adic number) with respect to the level number L and the reproduction signal change amount D. This calculation is performed by the level addition value detection circuit 134.
It's done analogically.

Further, the value of the number of levels L is set to the reference signal generator 1
I am making 33. The output of the quantization circuit 139 is a binary number, which is stored in the ROM 140 as L (3 in FIG. 7).
Converted to the value in the first digit of the base number. When the output is "1", the timing adjustment counter 145 stops the shift of the shift register 146 by 3 clocks of the reference clock and restores the binary 2-7 code signal. A specific circuit configuration of the quantization circuit 139 shown in FIG. 7 will be described with reference to FIG.

The quantizing circuit 139 includes a signal detecting section 151 for detecting the signal from the sample and hold circuit 136, a reference level generating section 152 for generating a plurality of reference levels, a detection signal from the signal detecting section 151 and a reference level generating section. 152
The signal comparison / quantization unit 153 is configured to compare a plurality of reference levels from 1 to 3 and output the comparison result as a quantized signal. The signal detection unit 151 includes an absolute value circuit 15
4 and a comparator 155. The reference level generation unit 152 includes a reference level output unit 156 including an operational amplifier 156a, a signal level comparison unit 157, and a low pass filter 158. The signal comparison / quantization unit 153 includes comparators 159 and 160, an inverter circuit 161, and gate circuits 162 and 163. The signal level comparison unit 157 includes the difference circuit 16
4, 165, 166, and an analog switch 167.

The reference signal level generating section 152 includes the signal obtained from the signal detecting section 151 and the reference signal level generating section 1.
The value of the reference level is changed by comparing inside 52 with the reference level which is the output value.

The deviation amount between the value of the reference level set by the reference level output unit 156 and the value of the signal obtained by the signal detection unit 151 is fed back to the reference level output unit 156 as a difference signal and fed back to the value of the reference level. It

Regarding the changing state of the reference level at this time,
This will be described with reference to FIG. It is assumed that the reference level, which serves as a reference for quantizing the output level change amount of the signal obtained from the signal detection unit 151, now has a value as shown in FIG. When a level change occurs in the signal obtained by the signal detection unit 151 as shown in FIG. 11A, the signal level change shown in FIG. 11C is generated between the change amount of the signal obtained by the signal detection unit 151 and the reference level value. A deviation amount of “ΔL” occurs as shown in FIG. The value after passing through the low-pass filter 158 with respect to the change amount of the shift amount is fed back to the reference level output unit 156 to change the reference level value as shown in (d) of FIG. ..

In the case of the demodulation circuit 42 shown in FIG. 7, the voltage generated from the reference signal generator 133 is always added, so that the signal after passing through the sample hold circuit 136 is always positive. However, in a general demodulation circuit, the level change amount may change negatively. Therefore, a (polarity indicating signal) terminal is provided which indicates whether the amount of change is positive or negative by the output of the comparator 155.

An absolute value circuit 154 is provided so as to detect the absolute value of the signal level change amount as a detection signal for feeding back the reference level value obtained from the signal detecting section 151.

In the portion corresponding to the reference level output unit 156 of FIG. 10, the output voltage of the operational amplifier 156a is resistance-divided to form a reference level, and the upper and lower limit level values at the time of quantization are set. The values of the upper and lower limit level values at the time of quantization and the signal from the signal detection unit 151 are compared by the comparator 1
59 and 160 are compared, and the inverter circuit 16
1. The gate circuits 162 and 163 perform arithmetic operations, and the quantized level value of the signal from the absolute value circuit 154 is output from each output terminal of the signal level comparison unit 157 as a quantized signal. The signal level comparison unit 157 calculates the amount of deviation between each reference level and the signal from the absolute value circuit 154 by the difference circuit 16.
The analog switch 167 selects the difference amount to be calculated and calculated by using 4, 165, and 166.

This difference signal is obtained by changing the signal from each absolute value circuit 154, but the low-pass filter 158 captures only a relatively slow change amount and performs feedback. The output voltage of the operational amplifier 156a is changed by adding the obtained differential signal to the operational amplifier 156a of the reference level output unit 156.

As described above, even if the reproduction signal level from the recording medium is locally reduced due to dust or scratches on the substrate surface of the recording medium or local reduction in recording film sensitivity, Since the reference level for quantizing the signal also changes along with the value, it is possible to quantize stably, and it is possible to secure a very high signal reading rate.

When the information is recorded on the recording medium, the demodulation signal corresponding to the level synchronization code recorded at a constant recording level is recorded prior to the recording of the information. It is possible to set the reference level for quantizing by using the reproduction signal to the optimum value, and it is possible to stably reproduce the recorded information signal and quantize the multi-valued information after that. It is possible to secure a high signal reading rate.

In the above embodiment, the reference level output by the reference level generating unit for generating the reference level for quantizing the signal level is varied by feeding back the signal level obtained from the recording medium. However, the amplitude of the signal obtained from the recording medium may be variable by comparing the reference level with the signal level obtained from the recording medium. A specific circuit configuration of the quantization circuit 139 of this embodiment will be described with reference to FIG.

That is, the quantizing circuit 139 detects the signal from the sample and hold circuit 136.
71, reference level generator 1 for generating a plurality of reference levels
72, a signal comparison / quantization unit 1 that compares the detection signal from the signal detection unit 171 with a plurality of reference levels from the reference level generation unit 172 and outputs the comparison result as a quantized signal
73, a voltage conversion circuit 17 that converts the signal from the signal comparison / quantization unit 173 into a voltage value and outputs the voltage value to the signal detection unit 171.
It is composed of four.

The signal detecting section 171 includes an absolute value circuit 175,
It is composed of a comparator 176, a signal gain adjusting circuit 177, and a photocoupler 178. The signal comparison / quantization unit 173 includes an A / D converter 179, a ROM 18
It is composed of 0s. The changing state of the reference level at this time will be described with reference to FIG. Signal detector 1
The reference level serving as a reference for quantizing the output level change amount of the signal obtained from 71 is now fixed to a value as shown in FIG. When a specific value is given to the gain of the signal gain adjustment circuit 177 in the signal detection unit 171, when the signal obtained from the signal detection unit 171 undergoes a level change as shown in FIG. Signal detector 171
A shift amount of "ΔL" as shown in FIG. 13C occurs between the obtained signal change amount and the reference level value.

The signal detector 171 is fed back to the amount of change in the value of the deviation amount, the gain of the signal gain adjusting circuit 177 is changed, and the amount of change in the signal from the signal detector 171 is shown in FIG. ) Is controlled.

In this case, unlike FIG. 10, in FIG. 12, the quantization of the multilevel signal level and the comparison of the reference level and the reproduced signal are performed digitally. The signal supplied from the absolute value circuit 175 through the signal gain adjusting circuit 177 is converted into a digital signal by the A / D converter 179 and output to the ROM 180. A reference level value for quantizing a multi-valued signal is stored in the ROM 180, and when the signal converted into the digital signal from the A / D converter 179 is supplied, it automatically responds to the level amount. And the quantized multilevel signal level value is output as a quantized signal,
A signal for controlling the gain of the signal from the absolute value circuit 175 is also output.

An analog gain control signal is generated by the voltage conversion circuit 174 for the latter digital signal. The voltage conversion circuit 174 is an addition circuit that weights the output terminal of the ROM 180. The output signal obtained from this adjusts the gain of the signal gain adjusting circuit 177 via the photo coupler 178.

With this arrangement, the substrate surface of the recording medium is dusted or scratched, and the sensitivity of the recording film is locally reduced, so that the reproduction signal level from the recording medium is locally reduced. Also, since the amplitude (amplification factor) of the signal changes along with the value, stable quantization can be performed and a very high signal reading ratio can be secured.

When the information is recorded on the recording medium, the demodulation signal corresponding to the level synchronization code recorded at a constant recording level is recorded prior to the recording of the information. The amplitude (amplification factor) of the reproduction signal can be set to an optimum value by using the reproduction signal for, and the reproduction of the information signal recorded thereafter and the quantization of the multivalued information can be stably performed, A very high signal read rate can be ensured.

[0072]

As described in detail above, according to the present invention,
It is possible to provide a reproducing apparatus that can reduce quantization errors when reproducing a signal from a recording medium and can stably reproduce information.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a disk device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a level synchronization code obtained by the signal processing circuit of FIG. 1 and a reproduction signal for an information signal.

FIG. 3 is a diagram for explaining a modulation system from a binarized signal sequence to a multilevel signal of the modulation circuit in FIG.

FIG. 4 is a block diagram showing a circuit configuration of a demodulation circuit shown in FIG.

5 is a block diagram showing a circuit configuration of the modulation circuit of FIG.

6 is a circuit diagram showing a specific configuration example of the modulation circuit in FIG.

7 is a circuit diagram showing a specific configuration example of the demodulation circuit in FIG.

8 is a diagram for explaining a detection principle of a signal level switching timing detection unit of the demodulation circuit of FIG.

9 is a diagram for explaining the detection principle of the multi-level level determination unit of the demodulation circuit of FIG.

10 is a block diagram showing a circuit configuration of the quantization circuit of FIG.

11 is a diagram showing a changed state of a quantized signal by the quantization circuit of FIG.

12 is a block diagram showing a circuit configuration of the quantization circuit shown in FIG.

13 is a diagram showing a changed state of the amplitude of a signal obtained from a recording medium by the quantization circuit of FIG.

DESCRIPTION OF SYMBOLS 1 ... Recording medium, 9 ... Semiconductor laser oscillator, 19 ... Signal processing circuit, 40, 41 ... Modulation circuit, 42, 43 ... Demodulation circuit, 44 ... Recording signal creating circuit, 47 ... Storage buffer, 4
8 ... Level synchronization code generation circuit, 49 ... Switching circuit, 51
... signal waveform conversion unit, 52 ... signal level switching timing detection unit, 53 ... multi-level level determination unit, 54 ... signal synthesis unit,
61 ... Modulation signal creating unit, 62 ... Timing creating unit, 63
... Multi-value level value determination unit 136 ... Sample hold circuit 139 ... Quantization circuit 151 ... Signal detection unit 152
... reference level generation unit, 153 ... signal comparison / quantization unit, 1
54 ... Absolute value circuit, 155 ... Comparator, 156 ... Reference level output section, 157 ... Analog switch.

Claims (1)

[Claims] 1. A reproducing apparatus for reproducing information from a recording medium having a level synchronization code recording area in which a level synchronization code of a constant recording level is stored and an information signal recording area in which an information signal is stored, Detection means for detecting the information signal stored in the information signal recording area on the recording medium and the level synchronization code stored in the level synchronization code recording area on the recording medium, and a reference value generating means for generating a reference value. Means, first processing means for comparing the detection signal from the detecting means with the reference value from the reference value generating means, and quantizing the signal according to the comparison result, and the first processing means. Conversion means for converting the detection signal of the detection means into a binarized signal sequence in accordance with the quantization result of, and the difference between the detection signal from the detection means and the reference value from the reference value generation means. Calculation means for, reproducing apparatus characterized by comprising a second processing means for changing the value of the reference value generated from the reference value generating means in accordance with the calculated difference by the calculating means.