JPH05267324A - Manufacture of mos semiconductor device - Google Patents

Manufacture of mos semiconductor device

Info

Publication number
JPH05267324A
JPH05267324A JP4058662A JP5866292A JPH05267324A JP H05267324 A JPH05267324 A JP H05267324A JP 4058662 A JP4058662 A JP 4058662A JP 5866292 A JP5866292 A JP 5866292A JP H05267324 A JPH05267324 A JP H05267324A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
type semiconductor
mos type
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4058662A
Other languages
Japanese (ja)
Inventor
Yasunobu Saito
泰信 斎藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP4058662A priority Critical patent/JPH05267324A/en
Publication of JPH05267324A publication Critical patent/JPH05267324A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H10D30/0229—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET forming drain regions and lightly-doped drain [LDD] simultaneously, e.g. using implantation through a T-shaped mask

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

(57)【要約】 【目的】サイドウォールを有するＬＤＤ構造のＭＯＳ型
半導体装置はサイドウォールの応力によりシリコン基板
に結晶欠陥が誘起され易いのを防ぎ、高い歩留でＬＤＤ
のＭＯＳ型半導体装置が得られる製造方法を提供するこ
とにある。 【構成】下層の多結晶シリコン電極４Ａの寸法より上層
のシリサイド電極５Ａの寸法が大きい２層ゲート電極を
形成し、寸法の大きいシリサイド電極５Ａ上から、質量
数の異なる同タイプの不純物イオンを異なる加速エネル
ギーで注入してＬＤＤ構造を形成する。 【効果】本発明によれば、サイドウォールが存在しない
ため、良好な歩留でＬＤＤ構造のＭＯＳ型半導体装置を
生産することができる。 (57) [Summary] [Objective] A MOS type semiconductor device having an LDD structure having a side wall prevents a crystal defect from being easily induced in a silicon substrate due to a stress of the side wall, so that the LDD has a high yield.
Another object of the present invention is to provide a manufacturing method capable of obtaining the MOS type semiconductor device. [Structure] A two-layer gate electrode is formed in which the size of a silicide electrode 5A in an upper layer is larger than that of a polycrystalline silicon electrode 4A in a lower layer, and impurity ions of the same type having different mass numbers are different from the silicide electrode 5A having a large size. The LDD structure is formed by implantation with acceleration energy. According to the present invention, since there is no sidewall, a MOS type semiconductor device having an LDD structure can be produced with a good yield.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はＭＯＳ型半導体装置の製
造方法に関し、特にＬＤＤ構造のＭＯＳ型半導体装置の
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS type semiconductor device, and more particularly to a method for manufacturing a MOS type semiconductor device having an LDD structure.

【０００２】[0002]

【従来の技術】従来のＬＤＤ構造のＭＯＳ型半導体装置
は、図２に示すように、シリコン基板１上に素子分離用
フィールド酸化膜２を形成したのち、下層のゲート電極
となる多結晶シリコン膜及び上層のゲート電極となるタ
ングステンシリサイド膜を形成したのちパターニングし
て下層のポリシリコン電極４Ａ，及び上層のタングステ
ンシリサイド電極５Ａを形成する。2. Description of the Related Art In a conventional MOS type semiconductor device having an LDD structure, as shown in FIG. 2, after a field oxide film 2 for element isolation is formed on a silicon substrate 1, a polycrystalline silicon film serving as a lower gate electrode is formed. Then, a tungsten silicide film serving as an upper gate electrode is formed and then patterned to form a lower polysilicon electrode 4A and an upper tungsten silicide electrode 5A.

【０００３】次いで、低濃度層６をイオン注入により形
成し、酸化シリコン膜を堆積し、ドライエッチングによ
り前記酸化シリコン膜のエッチバックを行ないゲート電
極側面部のみに酸化シリコン膜からなるサイドウォール
８を形成後、高濃度層７をイオン注入により形成してい
た。Next, a low-concentration layer 6 is formed by ion implantation, a silicon oxide film is deposited, and the silicon oxide film is etched back by dry etching to form a sidewall 8 made of the silicon oxide film only on the side surface of the gate electrode. After the formation, the high concentration layer 7 was formed by ion implantation.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、上述し
た従来のＬＤＤ構造のＭＯＳ型半導体装置の製造方法
は、酸化シリコンのサイドウォールの応力によりシリコ
ン基板に結晶欠陥が形成されやすく、歩留が低下する。
それと共に製造工程が長いという欠点があった。However, in the above-described method of manufacturing the MOS type semiconductor device having the LDD structure, the stress of the side wall of silicon oxide easily forms crystal defects in the silicon substrate, which lowers the yield. .
At the same time, there is a drawback that the manufacturing process is long.

【０００５】本発明の目的は、酸化シリコンのサイドウ
ォールの応力によりシリコン基板に発生する結晶欠陥の
形成を防ぎ、高い歩留でＬＤＤ構造のＭＯＳ型半導体装
置が簡易な工程で得られるＭＯＳ型半導体装置の製造方
法を提供することにある。An object of the present invention is to prevent formation of crystal defects generated in a silicon substrate due to the stress of a sidewall of silicon oxide, and to obtain a high-yield MOS type semiconductor device having an LDD structure in a simple process. It is to provide a method of manufacturing a device.

【０００６】[0006]

【課題を解決するための手段】本発明のＭＯＳ型半導体
装置の製造方法は、半導体基板上の酸化シリコン膜上
に、多結晶シリコン膜とシリサイド膜を順次形成したの
ち、パターニングして多結晶シリコンとシリサイド膜の
２層からなるゲート電極を形成するＬＤＤ構造のＭＯＳ
型半導体装置の製造方法であって、前記多結晶シリコン
電極の寸法より、寸法が大きい前記シリサイド電極上方
から質量数の異なる同タイプの不純物イオンを、異なる
加速エネルギーで注入するものである。According to a method of manufacturing a MOS type semiconductor device of the present invention, a polycrystalline silicon film and a silicide film are sequentially formed on a silicon oxide film on a semiconductor substrate and then patterned to form a polycrystalline silicon film. LDD structure MOS that forms a gate electrode consisting of two layers of
A method of manufacturing a type semiconductor device, comprising implanting impurity ions of the same type having different mass numbers from above the silicide electrode having a size larger than that of the polycrystalline silicon electrode at different acceleration energies.

【０００７】[0007]

【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例のＬＤＤ構造のＭＯＳ型半
導体装置の製造方法を説明するために工程順に示した半
導体装置の断面図である。The present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views of a semiconductor device shown in the order of steps for explaining a method of manufacturing a MOS type semiconductor device having an LDD structure according to an embodiment of the present invention.

【０００８】まず、図１（ａ）に示すよに、シリコン基
板１上に厚さ６００ｎｍの素子分離用のフィールド酸化
膜２を形成したのち、ＭＯＳトランジスタを形成する能
動領域にゲート絶縁膜となる酸化シリコン膜３を２５ｎ
ｍの厚さに形成する。First, as shown in FIG. 1A, a field oxide film 2 for element isolation having a thickness of 600 nm is formed on a silicon substrate 1, and then a gate insulating film is formed in an active region for forming a MOS transistor. 25n silicon oxide film 3
It is formed to a thickness of m.

【０００９】次に、図１（ｂ）に示すように、減圧ＣＶ
Ｄ法により下層のゲート電極となる多結晶シリコン膜４
を２００ｎｍの厚さに形成する。Next, as shown in FIG. 1B, the reduced pressure CV
Polycrystalline silicon film 4 to be a lower gate electrode by the D method
To a thickness of 200 nm.

【００１０】次いで、図１（ｃ）に示すように、スパッ
タ方法によりタングステンシリサイド膜５を２３０ｎｍ
の厚さに形成する。Next, as shown in FIG. 1C, a tungsten silicide film 5 is formed to a thickness of 230 nm by a sputtering method.
To the thickness of.

【００１１】次いで、図１（ｄ）に示すように、フォト
リソグラフィー工程により、パターニングし、上層のタ
ングステンシリサイド膜５を、ＳＦ6 のエッチングガス
を用い１２Ｐａの圧力でドライエッチングを行ない上層
のタングステンシリサイド電極５Ａを形成し、前述のタ
ングステンシリサイド電極５Ａの寸法より小さくなる様
に、ＣＣｌ2 Ｆ2 −Ｎ2 系のエッチングガスを用いて１
８Ｐａの圧力で下層の多結晶シリコン膜４をエッチング
して多結晶シリコン電極４Ａを形成する。Next, as shown in FIG. 1D, the upper tungsten silicide film 5 is patterned by a photolithography process, and the upper tungsten silicide film 5 is dry-etched at a pressure of 12 Pa using SF 6 etching gas. The electrode 5A is formed, and a CCl 2 F 2 —N 2 -based etching gas is used to reduce the size of the electrode 5A to a size smaller than that of the tungsten silicide electrode 5A.
The lower polycrystalline silicon film 4 is etched with a pressure of 8 Pa to form a polycrystalline silicon electrode 4A.

【００１２】次いで、タングステンシリサイド電極５Ａ
を通過するが、ポリシリコン電極４Ａを通過しない加速
エネルギー、例えばＢ+ の場合１００ｋｅＶ程度で５×
１０13ａｔｍ／ｃｃのイオンを注入し低濃度層６を形成
する。Then, a tungsten silicide electrode 5A is formed.
Passes through, but the acceleration energy which does not pass through the polysilicon electrode 4A, for example, in the case of B + in about 100 keV 5 ×
Ions of 10 13 atm / cc are implanted to form the low concentration layer 6.

【００１３】次いで、タングステン電極５Ａを通過しな
い加速エネルギー、例えばＢＦ2 の場合３０ｋｅＶ程度
で５×１０15ａｔｍ／ｃｃのイオンを注入し高濃度層７
を形成することにより、ＬＤＤ構造のＭＯＳ型半導体装
置を製造することができる。Then, acceleration energy that does not pass through the tungsten electrode 5A, for example, in the case of BF 2 , ions of 5 × 10 15 atm / cc are implanted at about 30 keV to inject the high concentration layer 7
By forming the, the MOS type semiconductor device having the LDD structure can be manufactured.

【００１４】[0014]

【発明の効果】以上説明したように本発明は多結晶シリ
コン膜とシリサイド膜からなるゲート電極を用いるＬＤ
Ｄ構造のＭＯＳ型半導体装置において、サイドウォール
が存在せず、サイドウォールに起因したシリコン基板に
発生する結晶欠陥が全く無く、良好な歩留を得られると
いう効果を有し、それと共に、サイドウォール形成工程
が不要であり製造工程が短縮され低コストで製造できる
という効果を有する。As described above, according to the present invention, an LD using a gate electrode composed of a polycrystalline silicon film and a silicide film is used.
In the MOS semiconductor device of D structure, there is no side wall, there is no crystal defect generated in the silicon substrate due to the side wall, and there is an effect that a good yield can be obtained. There is an effect that the forming process is unnecessary, the manufacturing process is shortened, and the manufacturing can be performed at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例のＬＤＤ構造のＭＯＳ型半導
体装置の製造方法を説明するために工程順に示した半導
体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device, which is shown in the order of steps for explaining a method for manufacturing a MOS semiconductor device having an LDD structure according to an embodiment of the present invention.

【図２】従来のＬＤＤ構造のＭＯＳ型半導体装置の構造
並に製造方法を説明するためのＬＤＤ構造のＭＯＳ型半
導体装置の断面図である。FIG. 2 is a cross-sectional view of a MOS type semiconductor device having an LDD structure for explaining a structure of a conventional MOS type semiconductor device having an LDD structure and a manufacturing method thereof.

【符号の説明】[Explanation of symbols]

１ シリコン基板 ２ フィールド酸化膜 ３ 酸化シリコン膜 ４ 多結晶シリコン膜 ４Ａ 多結晶シリコン電極 ５ タングステンシリサイド膜 ５Ａ タングステンシリサイド電極 ６ 低濃度層 ７ 高濃度層 ８ サイドウォール 1 silicon substrate 2 field oxide film 3 silicon oxide film 4 polycrystalline silicon film 4A polycrystalline silicon electrode 5 tungsten silicide film 5A tungsten silicide electrode 6 low concentration layer 7 high concentration layer 8 sidewall

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上の酸化シリコン膜上に、多
結晶シリコン膜とシリサイド膜を順次形成したのち、パ
ターニングして多結晶シリコンとシリサイド膜の２層か
らなるゲート電極を形成するＬＤＤ構造のＭＯＳ型半導
体装置の製造方法において、前記２層からなるゲート電
極を下層の多結晶シリコン電極より上層のシリサイド電
極の寸法を大きく形成し、大きい寸法の前記シリサイド
電極上方より質量数の異なる同タイプの不純物イオン
を、異なる加速エネルギーで注入することを特徴とする
ＭＯＳ型半導体装置の製造方法。1. An LDD structure in which a polycrystalline silicon film and a silicide film are sequentially formed on a silicon oxide film on a semiconductor substrate and then patterned to form a gate electrode composed of two layers of polycrystalline silicon and a silicide film. In a method of manufacturing a MOS type semiconductor device, the gate electrode formed of the two layers is formed such that a size of a silicide electrode in an upper layer is larger than that of a polycrystalline silicon electrode in a lower layer, and a mass number is different from that of the silicide electrode above the large size. A method for manufacturing a MOS semiconductor device, which comprises implanting impurity ions at different acceleration energies.
JP4058662A 1992-03-17 1992-03-17 Manufacture of mos semiconductor device Pending JPH05267324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4058662A JPH05267324A (en) 1992-03-17 1992-03-17 Manufacture of mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4058662A JPH05267324A (en) 1992-03-17 1992-03-17 Manufacture of mos semiconductor device

Publications (1)

Publication Number Publication Date
JPH05267324A true JPH05267324A (en) 1993-10-15

Family

ID=13090802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4058662A Pending JPH05267324A (en) 1992-03-17 1992-03-17 Manufacture of mos semiconductor device

Country Status (1)

Country Link
JP (1) JPH05267324A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1004810C2 (en) * 1996-12-04 1998-06-19 United Microelectronics Corp Improved salicide process technology.
FR2758210A1 (en) * 1996-10-16 1998-07-10 United Microelectronics Corp IMPROVED SALICIDE MANUFACTURING TECHNOLOGY
KR100636684B1 (en) * 2005-07-06 2006-10-23 주식회사 하이닉스반도체 Gate structure of cell transistor and manufacturing method of semiconductor memory device having same
JP2007067322A (en) * 2005-09-02 2007-03-15 Denso Corp Manufacturing method of semiconductor device of LDD structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6344767A (en) * 1986-08-12 1988-02-25 Mitsubishi Electric Corp Field effect transistor and manufacture of the same
JPS6344768A (en) * 1986-08-12 1988-02-25 Mitsubishi Electric Corp Field effect transistor and manufacture of the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6344767A (en) * 1986-08-12 1988-02-25 Mitsubishi Electric Corp Field effect transistor and manufacture of the same
JPS6344768A (en) * 1986-08-12 1988-02-25 Mitsubishi Electric Corp Field effect transistor and manufacture of the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2758210A1 (en) * 1996-10-16 1998-07-10 United Microelectronics Corp IMPROVED SALICIDE MANUFACTURING TECHNOLOGY
NL1004810C2 (en) * 1996-12-04 1998-06-19 United Microelectronics Corp Improved salicide process technology.
KR100636684B1 (en) * 2005-07-06 2006-10-23 주식회사 하이닉스반도체 Gate structure of cell transistor and manufacturing method of semiconductor memory device having same
JP2007067322A (en) * 2005-09-02 2007-03-15 Denso Corp Manufacturing method of semiconductor device of LDD structure

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