JPH05267681A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the sectional area of a gate of a select transistor, reduce the resistance of the gate, and increase the reading speed of stored data, by making a side wall spacer formed slenderly on the side part of a gate of a select transistor function as an insulating film for holding electric charges. CONSTITUTION:A P-type well 2 formed on an N-type silicon substrate 1 is isolated according to specified element forming regions by a field oxide film 3. In a channel region between a drain diffusion layer 11 and a source diffusion layer 12, a side wall spacer 7a which is slenderly formed by interposing a tunnel oxide film 6 and functions as an insulating film for holding electric charges is formed in a region in the vicinity of the drain diffusion layer 11. Said sidewall spacer 7a is composed of, e.g. a poly-silicon film. In the channel region, a common gate 10a is formed in the source side region via a gate oxide film 9, so as to stretch as far as the upper region of the side-wall spacer 7a while interposing an insulating film 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an EEPROM (Electr
The present invention relates to a non-volatile semiconductor memory device such as a physically erasable / programmable read only memory.

[0002]

2. Description of the Related Art A typical prior art is shown in FIG. That is, the memory transistor used in this non-volatile semiconductor memory device of the prior art is called a trap type, and an N ⁺ type high-concentration impurity region is formed in a P type semiconductor substrate 61 to form a source diffusion layer 62 and a drain diffusion layer. A layer 63 is provided, an insulating film 64 capable of capturing electrons or holes is formed on the surface of the semiconductor substrate 61 between the layers 63, and a gate 65 is formed on the insulating film 6. The insulating film 64 is a so-called ONO film having a sandwich structure in which a nitride film 64C is sandwiched by a tunnel oxide film 64A and a top oxide film 64B.

In writing data, a write voltage V _P that makes the gate 65 side positive is applied between the gate 65 and the substrate 61, and the tunnel oxide film 64A is transmitted by direct tunneling from the substrate 61. Electrons are injected into the nitride film 64C. In the written state in which the electrons are captured in the nitride film 64C, the threshold voltage for making the memory transistor conductive has a high value.

In erasing data, an erasing voltage V _E that makes the gate 65 side negative is applied between the gate 65 and the substrate 61, whereby direct tunneling causes electrons in the nitride film 64C to tunnel oxide film. After passing through 64A, it is extracted into the substrate 61. In the erased state where electrons are not captured in the nitride film 64C, the threshold voltage for making the memory transistor conductive has a low value.

To read data, a sense voltage having an intermediate voltage value between the two threshold values in the write state and the erase state is applied to gate 65, and the memory transistor is turned on or off. This can be achieved by monitoring what is retained. An EEPROM using such a trap type memory transistor is
A full-future type in which a select transistor is provided for each memory transistor of each cell and information can be written, erased, and read independently for each cell,
There is a flash type in which writing and reading of information is performed for each cell and erasing is performed collectively for all cells.

However, the full-future type is
Since the select transistor is provided for each individual cell, the cell area becomes large and high integration is difficult. For this reason, recently, flash-type devices have been actively developed.

[0007]

However, in order to erase the stored information of all the cells on the substrate all at once, the overall erase time is set to be long in accordance with the cell that requires the longest time to erase the signal charge. There is a need to. Therefore, in a cell in which the signal charge is erased relatively quickly, the signal charge is excessively extracted and positive charge is accumulated in the insulating film 64 of the memory transistor of this cell, which is an excessive erase. When such over-erasure occurs, the threshold value of the transistor varies among cells, and the read operation may become unstable. For example, in a memory transistor of a cell in which over-erase has occurred, even if it is in a non-selected state, a channel is formed due to the positive charge accumulated in the insulating film, and a current flows between the source and the drain. Then, the reading of the stored information from the target cell becomes uncertain.

In order to solve such a problem, FIG.
As shown in simplified form, the floating gate type E
SISOS (SIde, which is proposed to be applied to EPROM
It is possible to adopt the wallSelect-gate On the Source side) structure. In addition, in FIG. 8, portions corresponding to the respective portions shown in FIG. 7 described above are denoted by the same reference numerals.

In this structure, a SWS (side wall spacer) formed in a self-aligned manner on the side wall portion of the gate including the insulating film 64 on the source diffusion layer 62 side is used as the select gate 71 for cell selection. Be done. When reading information, a positive voltage is applied to the selection gate 71,
A channel is formed in the semiconductor substrate 61 immediately below the select gate 71.

According to this structure, the read cell can be surely selected by applying the voltage to the select gate 71.
Even if there is some variation in the threshold value due to overerasure, reading of information from non-selected cells can be prevented,
The reliability of the read operation can be secured. Moreover, since the transistor formation region does not become excessively large, high integration can be favorably performed.

However, in the memory device to which the transistor having the SISOS structure as described above is applied, it is necessary to apply a voltage to the select gate 71 having a relatively small cross-sectional area. result,
There is a problem that speeding up of the read operation is hindered. Increasing the cross-sectional area of the select gate 71 in order to avoid this problem leads to an increase in the substrate area and runs counter to the demand for high integration, which is unacceptable.

Further, in any of the structures of FIG. 7 and FIG. 8, since writing and erasing are performed by direct tunneling from the substrate 61, the tunnel oxide film 64 is formed.
The film thickness of A needs to be made thin to some extent. However, since the thin tunnel oxide film 64A is used as described above, there is a drawback that accumulated charges are easily dissipated and the data retention characteristic is poor.

In order to solve this problem, the tunnel oxide film 64A is formed thick, hot electrons that can pass through the thick oxide film are generated in the vicinity of the drain diffusion layer 63, and this hot electron is injected. It is possible to write data and erase information by a so-called FN tunnel. However, since the charges trapped in the insulating film do not move, electrons are injected only into the region of the nitride film 64C near the drain diffusion layer 63. With such local injection of electrons, the threshold value of the memory transistor cannot be changed so much, and information storage becomes unstable.

Therefore, an object of the present invention is to solve the above-mentioned technical problems, to favorably perform a read operation, to be advantageous in high integration, and to surely store information. A non-volatile semiconductor memory device is provided.

[0015]

A conceptual structure of a nonvolatile semiconductor memory device of the present invention for achieving the above object is shown in FIG. That is, the nonvolatile semiconductor memory device of the present invention selects the memory transistor MTr that performs nonvolatile storage by injecting / releasing charges to / from the charge holding insulating film via the tunnel insulating film 51, and the memory transistor MTr. A first impurity diffusion region 53 and a second impurity diffusion region which are formed on the semiconductor substrate 50 with a channel region interposed therebetween and also serve as drains and sources of the memory transistor MTr and the select transistor STr. 54, a gate 55 of the select transistor STr formed on the channel region of the semiconductor substrate 50, and a sidewall spacer 52 provided on the drain side of the gate 55 and acting as the charge retention insulating film. , Insulation near this sidewall spacer 52 56 disposed through those comprising a control gate 57 of the memory transistor MTr.

[0016]

According to the above configuration, the select transistor S
The gate 55 of the Tr is formed over a relatively wide region of the channel region, and the sidewall spacer 52 formed on the side of the gate 55.
Functions as an insulating film for holding charges. Therefore, since the gate 55 to which the voltage for selecting the memory transistor MTr is applied has a relatively large cross-sectional area, it can have a sufficiently small resistance value, which allows a high-speed read operation. Can be achieved.

On the other hand, since the side wall spacer 52 is thinly formed on the side portion of the gate 55, when hot electrons or hot holes are generated in the vicinity of the first impurity diffusion region 53 corresponding to the drain, this hot electron is generated. Alternatively, hot holes are evenly captured in the sidewall spacers 52. Therefore, the threshold value of the memory transistor can be changed sufficiently large by injecting hot electrons or hot holes. As a result of stable storage by injecting hot electrons or hot holes in this manner, the film thickness of the tunnel insulating film 51 can be increased, whereby dissipation of charges can be effectively prevented and storage can be held well. Can be made.

[0018]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. 2 is a plan view of a memory cell of an EEPROM which is an embodiment of the nonvolatile semiconductor memory device of the present invention, and FIG. 3 is a sectional view taken along the section line AA of FIG. The P-type well 2 formed on the N-type silicon substrate 1 is separated by the field oxide film 3 for each predetermined element formation region. An N ⁺ type drain diffusion layer 11 and an N ⁺ type source diffusion layer 12 are formed in the separated element formation region.

In the channel region between the drain diffusion layer 11 and the source diffusion layer 12, a region near the drain diffusion layer 11 acts as a charge-retaining insulating film formed in a slender shape with the tunnel oxide film 6 interposed. Sidewall spacer 7
a is formed. The sidewall spacer 7a is made of, for example, a polysilicon film. In addition, in the above-mentioned channel region, the gate oxide film 9 is formed in the source side region.
The common gate 10a is formed through the insulating film 8 and the side wall spacer 7 is formed.
It is formed so as to extend to a region above a.

In FIGS. 2 and 3, 14 is a metal wiring electrically connected to the drain diffusion layer 11 and the source diffusion layer 12, 16 is a metal wiring electrically connected to the common gate 10, and 13, Reference numeral 15 is an interlayer insulating film. In this embodiment, one memory cell has a memory transistor and a select transistor in one transistor region. That is, the drain diffusion layer 11 and the source diffusion layer 12 are also used as the drain and the source of both transistors. Further, the gate of the memory transistor is composed of the tunnel oxide film 6, the sidewall spacer 7a, the insulating film 8 and the common gate 10a described above, and one end of the common gate 10a on the drain side serves as a control gate. Further, the gate of the select transistor is composed of the source-side end of the above-described gate oxide film 9 and common gate 10a.

FIG. 4 shows a part of the EEPROM of this embodiment.
It is an electric circuit diagram which shows an equivalent circuit. One memory cell
Is the memory transistor MTr and select transistor described above.
It is composed of a register STr and each memory cell is a matrix.
It is arranged like a stripe. Both transistors MTr, STr
The common gate 10a of the
_n, W_{n + 1}, W_{n + 2}Connected to the memory transistor M
The drain (drain diffusion layer 11) of Tr is a bit line
B_m, B_{m + 1}Connected to the select transistor STr
Source (source diffusion layer 12) is the source line S_m, S
_{m + 1}It is connected to the. Word line W_n, W_{n + 1}, W
_{n + 2}Is selected by the X decoder 20 and the source line S
_m, S_{m + 1}Are selected by the Y decoder 21.

Data writing to the memory cell (n, m) is performed as follows. That is, the write voltage V _P is applied to the bit line B _m , the word line W _{n is set} to the H level, and the source line S _m is grounded. The memory cell (n, m + 1) commonly connected to the word line W _n together with the memory cell (n, m) is opened or grounded by opening the bit line B _{m + 1} and the source line S _{m + 1} . Writing is prohibited. In the other memory cells (n + 1, m) and (n + 1, m + 1), by setting the word line W _{n + 1} to the ground or the L level, the select transistor STr is turned off and writing can be prohibited.

In the selected memory cell (n, m), hot electrons are injected into the side wall spacer 7a as follows. That is, in the drain diffusion layer 11,
When the write voltage V _P is applied, the source diffusion layer 12 is grounded, and the common gate 10a becomes H level, a channel is formed from the source diffusion layer 12 toward the drain diffusion layer 11. By properly setting the write voltage V _P , this channel is passed over the lower portion of the select transistor STr (that is, immediately below the gate oxide film 9 on the right side of the common gate 10a in FIG. 3) and at the drain diffusion layer 11. Extend to a position that does not reach. Then, the side wall spacer 7
The electric field concentrates just below a and a large number of hot electrons are generated. A part of the hot electrons flows into the drain diffusion layer 11, but a part of the hot electrons is accelerated by the electric field of the common gate 10a, passes through the tunnel oxide film 6, and is injected into the sidewall spacer 7a to be captured. In this way, writing of data is achieved. In this written state, the threshold value for making the memory transistor MTr conductive has a high value.

Erasing the data in the memory cell (n, m)
This is done as follows. That is, the word line W _n
Is set to the L level, and the erase voltage V _E is applied to the bit line B _m and the source line S _m . The memory cell (n, m + 1) commonly connected to the word line W _n together with the memory cell (n, m) has a bit line B _{m +.
1} and the source line S _{m + 1} are grounded or open, and erasing is prohibited. In addition, other memory cells (n
+ 1, m) and (n + 1, m + 1) are word lines W
Erase can be prohibited by setting _{n + 1} to the H level. When the common gate 10a of the memory cell (n, m) is set to the L level and the erase voltage V _E is applied to the drain diffusion layer 11, the electrons captured by the sidewall spacer 7a pass through the tunnel oxide film 6. And is pulled out to the drain diffusion layer 11 to erase the stored data. In this erased state, the threshold value for making the memory transistor MTr conductive has a low value.

The reading of the storage data of the memory cell (n, m) is performed as follows. That is, the source line S _m is grounded and the sense voltage V _{SENSE is} applied to the word line W _n.
It applies a applies a voltage Vcc via a resistor to the bit line B _m, the bit line B _m, for detecting the presence or absence of the potential drop. That is, the memory cell (n, m)
If data is written in the memory transistor M,
Since Tr is turned off, no voltage drop occurs,
That is, the data “1” is read. On the other hand, when the data is written in the memory cell (n, m), the memory transistor MTr is turned on, so that the voltage drop occurs, that is, the data “0” is read.
The sense voltage V _SENSE is a voltage having an intermediate value between the threshold values of the memory transistor MTr in the written state and the erased state.

As described above, in this embodiment, the sidewall spacer 7a formed on the side of the gate of the select transistor STr is used as the charge retention insulating film, and the common gate 10a has a relatively wide region on the channel region. The source-side portion having a large cross-sectional area formed over the area is used as the gate of the select transistor STr. Therefore, the gate of the select transistor STr can have a sufficiently small resistance, so that the select transistor STr can be driven well. As a result, the read operation can be performed at high speed.

On the other hand, since the thin sidewall spacer 7a is used as the charge retention insulating film of the memory transistor MTr, hot electrons locally generated at the boundary of the drain diffusion layer 11 are uniformly distributed over the sidewall spacer 7a. Can be captured. Therefore, the threshold value for making the memory transistor MTr conductive can be largely changed, and as a result, stable storage is possible. Also,
Since the writing is performed by the injection of hot electrons, the tunnel oxide film 6 can be formed thickly, which effectively prevents the charge trapped by the side wall spacers 7a from being dissipated and retains a good memory. Can be done.

Moreover, since the two transistors of the memory transistor MTr and the select transistor are formed in one transistor formation region, the area of the memory cell does not increase excessively, and high integration can be favorably achieved. It can be carried out. Hereinafter, a method of manufacturing the EEPROM of this embodiment will be described with reference to FIGS.
The manufacturing method can be variously modified, and the memory device of the present invention is not limited to the one manufactured by this method.

First, as shown in FIG. 5 (a), a P-type well 2 is formed on an N-type silicon substrate 1, an oxide film 4 is then formed on the surface, and a field oxide film 3 for element isolation is further formed. Can be selectively grown. Then, as shown in FIG. 5B, the oxide film 5 is formed by CVD (Chemical Vapor Deposit).
ion deposition) and then anisotropically etching to selectively remove the oxide film 5 in the region where the memory transistor and the select transistor are to be formed.

From this state, in order to smooth the surface of the substrate, the surface of the substrate is re-oxidized and then the oxide film is removed by wet etching. Then, in the element formation region,
After forming the tunnel oxide film 6, a polysilicon film 7 is deposited. This state is shown in FIG. 5 (c). next,
As shown in FIG. 5D, the polysilicon film 7 on the oxide film 5 is
Etch back until all are removed. This allows
A sidewall of polysilicon is formed on the end surface of the window portion of the oxide film 5. The left sidewall serves as the sidewall spacer 7a of the memory transistor MTr described above. The width of the sidewall spacer 7a in the gate length direction is determined by the oxide film 5
By changing the thickness and etching conditions, it is possible to control the size within the design rule.

Next, refer to FIG. 6 (e). In this step, the sidewall spacer 7a, which is the left sidewall shown in FIG. 5D, and a part of the oxide film 5 are masked with a photoresist, and the right sidewall and the rest of the oxide film 5 are etched. To remove. Then, after removing the photoresist, thermal oxidation is performed to form an insulating film (silicon oxide film) 8 on the surface of the sidewall spacer 7a. Further, the oxide film in the select transistor region is removed by wet etching, then the gate oxide film 9 is formed, and then the polysilicon film 10 is formed.

Next, as shown in FIG. 6 (f), the transistor region is masked with a photoresist, and the remaining polysilicon film 10 and oxide film 5 are removed by anisotropic etching. As a result, the common gate 10a which is also used as the control gate of the memory transistor and the gate of the select transistor is formed. After removing the oxide film 9 in the drain and source regions, N type impurities such as phosphorus and arsenic are ion-implanted to form the drain diffusion layer 11 and the source diffusion layer 12.

Further, as shown in FIG. 6G, thermal oxidation is performed again to form an oxide film on the surface. And phosphorus glass (P
After depositing an interlayer insulating film 13 such as SG), contact holes are formed in the drain and source regions, and Al--S
Deposit a metal such as i. This metal film is patterned by photoetching to form metal wirings electrically connected to the drain diffusion layer 11 and the source diffusion layer 12.

Then, as shown in FIG. 6H, after depositing the interlayer insulating film 15, a contact hole is formed in the gate region and a metal layer is deposited. By patterning this metal layer, the metal wiring 16 connected to the common gate 10a is formed. In this way, FIG. 2 and FIG.
The EEPROM shown in FIG. The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the N-channel type EEPROM has been described as an example, but the present invention is a P-channel type EEPROM.
Of course, it can also be applied to.

Further, the drain diffusion layer 11 and the P-type well 2
A P ⁺ -type diffusion layer for increasing the generation efficiency of hot electrons may be provided between and. Furthermore, in order to improve the breakdown voltage, an N ⁻ diffusion layer may be provided between the source diffusion layer 12 and the P-type well 2. Further, in the above-mentioned embodiment, the control gate of the memory transistor and the gate of the select transistor are constituted by one common gate 10a, but these gates are two insulated from each other as in the constitution of FIG. It may be configured by a gate.

In addition, various design changes can be made without departing from the spirit of the present invention.

[0037]

As described above, according to the nonvolatile semiconductor memory device of the present invention, since the side wall spacers thinly formed on the side portions of the gates of the select transistors function as the charge retaining insulating film, The gate of the select transistor formed on the region may have a sufficiently large cross-sectional area. Therefore, since the gate of the select transistor can have a sufficiently low resistance value, the stored information can be read at high speed.

Moreover, in one transistor formation region,
Since the two transistors of the memory transistor and the select transistor are formed, they can be formed in a small area, which is advantageous for high integration. In addition, since the side wall spacer for holding charges is formed thin on the side portion of the gate, stable storage can be performed by injecting hot electrons or hot holes. As a result,
The tunnel insulating film can be formed thick. As a result, it is possible to effectively prevent the dissipation of electric charges and to favorably retain the memory.

[Brief description of drawings]

FIG. 1 is a simplified cross-sectional view showing a basic configuration of a nonvolatile memory device of the present invention.

FIG. 2 is a plan view showing a cell structure of an EEPROM which is an embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a sectional view taken along the section line AA of FIG.

FIG. 4 is an electric circuit diagram showing an equivalent circuit of a part of the memory device of the above embodiment.

FIG. 5 is a cross-sectional view showing the manufacturing process of the memory device of the above embodiment in the order of processes.

FIG. 6 is a cross-sectional view showing the manufacturing process of the memory device of the above embodiment in process order.

FIG. 7 is a sectional view showing a cell structure of an EEPROM having a stack gate structure which has been conventionally used.

FIG. 8 is a cross-sectional view showing an example in which the SISOS structure is applied to a trap type memory transistor.

[Explanation of symbols]

 1 N-type silicon substrate 2 P-type well 6 Tunnel oxide film 7a Side wall spacer 8 Insulating film 9 Gate oxide film 10a Common gate 11 Drain diffusion layer (first impurity diffusion region) 12 Source diffusion layer (second impurity diffusion region) 50 Semiconductor Substrate 51 Tunnel Insulation Film 52 Sidewall Spacer 53 First Impurity Diffusion Region 54 Second Impurity Diffusion Region 55 Select Transistor Gate 56 Insulation Film 57 Memory Transistor Control Gate MTr Memory Transistor STr Select Transistor

Claims (1)

[Claims] 1. A non-volatile semiconductor memory device having a memory transistor for performing nonvolatile storage by injecting / releasing charges to / from an electric charge holding insulating film through a tunnel insulating film, and a select transistor for selecting the memory transistor. A first impurity diffusion region and a second impurity diffusion region which are formed on the semiconductor substrate with a channel region interposed therebetween and also serve as drains and sources of the memory transistor and the select transistor, and formed on the channel region of the semiconductor substrate. A gate of the select transistor, a side wall spacer provided on the drain side of the gate and acting as the insulating film for holding charge, and an insulating film disposed in the vicinity of the side wall spacer,
A nonvolatile semiconductor memory device comprising the control gate of the memory transistor.