JPH05268201A - Clock transfer circuit - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a clock transfer circuit, such as an elastic store circuit, which performs clock transfer of time-division-multiplexed data. The purpose is to provide. [Structure] A multi-sided memory is provided, and the write side uses a write clock to write time-division multiplexed data by sequentially switching these memories for each frame, and the read side uses a read side clock to frame these memories. In a clock transfer circuit that switches clocks by switching in sequence for each time and reading the written data,
A phase monitoring unit 11 that monitors and detects the collision of the write phase and the read phase in the same memory, and the phase monitoring unit 11
When the collision between the write phase and the read phase is detected, the phase control unit 12 is provided which changes the read phase and separates the write phase and the read phase by a predetermined phase difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock transfer circuit such as an elastic store circuit for performing clock transfer of time-division multiplexed data.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional clock transfer circuit. This conventional circuit performs clock transfer on the audio data portion in the time division multiplexed data, separates the audio data from the time division multiplexed data by the demultiplexer 21, and digitalizes this audio data by the D / A converter 22. / Analog conversion, the converted analog voice data is again analog / digital converted by the A / D converter 23, and the converted digital voice data is again multiplexed by the multiplexer 24 to form time division multiplexed data. At the time of this conversion, the demultiplexer 21 and the D / A converter 22 are operated by a write clock (usually a transmission line clock),
By operating the A / D converter 23 and the multiplexer 24 with the read clock (usually the in-station clock), the time division multiplexed data is transferred from the write clock to the read clock.

[0003]

In the conventional clock transfer circuit, time division multiplexed data is D / A converted, and further A / D conversion is performed.
The D / A converter and the A / D converter are necessary because the clock conversion is performed after the D conversion, but the D / A converter and the A / D converter have a problem that the circuit scale is large. ..

The present invention has been made in view of such problems, and an object thereof is to provide a clock transfer circuit having a small circuit scale.

[0005]

FIG. 1 is a diagram illustrating the principle of the present invention. The clock transfer circuit of the present invention comprises a plurality of planes of memory, the write side uses the write clock to write the time division multiplexed data by sequentially switching these memories for each frame, and the read side uses the read side clock. In a clock transfer circuit that switches clocks by sequentially switching these memories for each frame and reading out written data, a phase monitoring unit 11 that monitors and detects the presence or absence of a collision between a write phase and a read phase in the same memory. When the phase monitoring unit 11 detects a collision between the write phase and the read phase, the phase control unit 1 changes the read phase to separate the write phase from the read phase by a predetermined phase difference.
2 is provided.

In the clock transfer circuit of the present invention, the above-mentioned clock transfer circuit has a two-sided memory as a memory, and the phase control unit 11 reads the two-sided memory for reading / non-reading. A read switching signal generator that generates a switching signal, a toggle switch that reverses the polarity of the output signal by the collision detection signal from the phase monitor, a read switching signal from the read switching signal generator, and an output signal from the toggle switch. Is entered,
It can be configured with an exclusive OR gate that outputs a read memory switching signal that designates one of the two side frame memories as the read side.

[0007]

The phase monitoring unit 11 monitors whether or not there is a collision between the write phase and the read phase in the same memory, and when the collision is detected, the phase control unit 12 changes the read phase to change the write phase and the read phase. The phases are separated by a predetermined phase difference to avoid a collision state.

When the memory has a two-sided structure, the phase controller 12 inverts the polarity of the output signal of the toggle switch every time the phase monitor 11 detects a collision, and outputs the output of the toggle switch. A signal can be used to control the polarity of the read switching signal that passes through the exclusive OR gate, and the read memory switching signal can be configured. This causes the memory on the read side to switch instantly from one to the other each time a collision is detected, so that the write and read phases are instantaneously close to one.
It will be 80 degrees apart.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a clock transfer circuit as an embodiment of the present invention. In this embodiment, the voice data contained in a part of the frame of the time division multiplexed data is clock-changed from the write clock (transmission path clock) to the read clock (internal station clock).

In FIG. 2, reference numerals 1 and 2 designate two writable / readable memories, which are alternately switched for each frame of the time division multiplexed data so that the audio data in the time division multiplexed data is a write clock. It is written at a speed and the written data is read at a read clock speed. Data of n-bit parallel time-division multiplexed data are input to the memories 1 and 2, respectively. The write-side control signal is the write clock CLK _w generated by the write clock generator 6, and the audio data in the frame. , A write timing signal (d) corresponding to the position of (1) and a write memory switching signal (c) for putting one of the memories into a write enable state are input, and a read clock generator 40 is used as a read side control signal. The read clock CLK _R , the read timing signal (h), and the read memory switching signal (l) for putting one of the memories into the read enable state are input.

Reference numeral 3 denotes a write memory switching signal generator 3 for generating a write memory switching signal (c) for switching one of the memories 1 and 2 to a write enable state. The signal is input to the system memory 1 and the system memory 2 via the inverter, so that when one memory is in the write enable state, the other memory is in the write disable state. This write memory switching signal is also input to the write / read phase monitoring unit 42 described later.

Reference numeral 4 denotes a phase monitoring control unit, which monitors the presence or absence of a collision between the write phase and the read phase in the same memory, and when the collision is detected, the read phase is changed to change both phases. Operate to be separated by 180 degrees. That is, the phase monitoring control unit 4 supplies the read memory switching signal (l) to the system memory 1 and the system memory 2 via the inverter, and the write phase and the read phase collide in one memory. In this case, by inverting the polarity of the read memory switching signal, the memory in the read enabled state is instantaneously switched from one memory to the other memory, whereby the write phase and the read phase are separated by 180 degrees. There is.

The phase monitoring controller 4 includes a read clock generator 40 for generating a read clock CLK _R , a read switching signal generator 41 for generating a read switching signal (g), and a collision between a write phase and a read phase. It includes a write / read phase monitoring unit 42 for monitoring, a toggle flip-flop 43 as a toggle switch, an exclusive OR (XOR) gate 44, and the like.

The read switching signal generator 41 receives the read clock CLK _R and the read frame pulse (f) and generates a read switching signal (g) that determines the read enable / disable period of the memories 1 and 2. To do. This read switching signal (g) is supplied to the memories 1 and 2 as a read memory switching signal (l) by passing through the XOR gate 44.

The write / read phase monitor 42 receives the write memory switching signal (c), the write timing signal (d), the read memory switching signal (l) and the read timing signal (h), and based on them. It detects a collision between a write phase and a read phase in the same memory, and its detailed configuration is shown in FIG. That is,
AND gates 421 and 422 and a flip-flop 425 for detecting a collision of both phases in the system memory 1, AND gates 423 and 424 and a flip-flop 426 for detecting a collision of both phases in the system memory 2, It consists of an OR gate 427 that superimposes both detection signals.

Here, the AND gate 421 has a write memory switching signal (c) and a write timing signal (d).
Is input and the AND output signal (e) is input to the data input terminal of the flip-flop 425, and the AND gate
The read memory switching signal (l) and the read timing signal (h) are input to 422, and the phase collision detection clock (i), which is the AND output, is input to the flip-flop 42.
5 is input to the clock input terminal. Therefore, when the read timing signal (h) is input while the write timing signal (d) is input in the system memory 1, the output signal (j) of the flip-flop 425 is "H".
, And that state continues until both timings separate. This output signal (j) is sent as a collision detection signal to the toggle flip-flop 43 at the subsequent stage through the OR gate 427.

Also in the collision monitoring circuit for the system memory 2, the write memory switching signal (c) and the read memory switching signal (l) are polarity-inverted by the respective inverters and input to the AND gates 423 and 424. Except for this, the circuit configuration is the same.

The toggle flip-flop 43 inverts the polarity of its output signal (k) every time the collision detection signal of "H" is input from the write / read phase monitor 42. This output signal (k) is input to the XOR gate 44,
Therefore, each time the output signal (k) of the toggle flip-flop 43 is inverted (hence, whenever a collision between the write phase and the read phase occurs), it is based on the read switching signal (g) from the write / read phase monitor 42. The polarity of the read memory switching signal (1) is inverted, and the memory in the read enabled state is instantaneously switched from one to the other.
That is, the writing phase and the reading phase are instantaneously separated by 180 degrees.

Reference numeral 5 denotes a read switching unit, which is used for each memory 1,
The AND gate 5 to which the voice data read from 2 is input and whose opening and closing is controlled by the read memory switching signal (l)
1, 52, an OR gate 53 for superimposing the output signals of the AND gates 51, 52, a flip-flop 54 for correcting the read audio data, and the like. The read switching unit 5 is a circuit that selects the audio data read from the memory switched to the read enable state by the read memory switching signal (1) and outputs it as time division multiplexed data to the inside of the station.

The operation of this embodiment circuit will be described below with reference to the time chart of FIG. FIG. 4 is a time chart of signals at various parts of the embodiment circuit. In this FIG.
(A) is time division multiplexed data on the input side, (b) is a frame pulse on the writing side, (c) is a memory switching signal for writing,
(D) is a write timing signal, (e) is an AND signal of the write memory switching signal and the write timing signal (that is, an output signal of the AND gate 421 in the write / read phase monitor 42), and (f) is a read side frame pulse. , (G) is a read switching signal, (h) is a read timing signal, and (i) is a collision detection clock (that is, the AND gate 4 in the write / read phase monitoring unit 42).
22 output signal), (j) is the output signal of the flip-flop 425 in the write / read phase monitoring unit 42,
(K) is the output signal of the toggle flip-flop 43,
(L) is a read memory switching signal output from the phase monitoring controller 4.

First, the write operation of the memories 1 and 2 will be described. The write memory switching signal (c) is switched between "H" and "L" in synchronization with the frame cycle of the time division multiplexed data (a). When the write memory switching signal (c) is "H", System memory 1 is in write mode,
When it is "L", the system memory 2 is in the write mode. Then, at the timing when the write timing signal (d) is input, the time division multiplexed data (a) is written to the memory in the write mode. Here, the audio data in the time division multiplexed data (the hatched portion in FIG. 3A) is written in the memory.

Next, the read operation from the memories 1 and 2 will be described. When the read memory switching signal (l) output from the phase monitoring controller 4 is "H", the system memory 1
Becomes the read mode, and when it is "L", the system memory 2 becomes the read mode and the read timing signal (h)
Is input, the audio data is read from the memory on the side in the read mode and sent to the subsequent circuit via the read switching unit 5.

Now, it is assumed that the writing phase and the reading phase collide with each other in the system memory 1. That is, as shown near the center of the time chart of FIG. 4, it is assumed that the phase collision state is detected because the signal (e) and the signal (i) overlap each other. As a result, the write / read phase monitoring unit 42
The output signal (j) of the flip-flop 425 becomes "H", and the polarity of the output signal (k) of the toggle flip-flop 43 is inverted from "L" to "H". As a result, the read memory switching signal (l) is also inverted in polarity, and the memory in the read mode is switched from the system memory 1 to the system memory 2. As a result, the writing phase and the reading phase are instantaneously separated by 180 degrees, and the collision state of both phases can be eliminated.

The manner of reading the audio data at the time of this collision will be described below with reference to FIG. In the figure,
(A) is read clock C from write clock CLK _w
When LK _R is faster, (B) is when the write clock CLK _w is faster than the read clock CLK _R.

First, the case (a) where the read clock is fast will be described. Now, every time a frame of time division multiplexed data arrives in the memory 1, the audio data a, c,
It is assumed that the data is written in the order of e, g, i ... And the audio data is written in the memory 2 in the order of b, d, f, h. Reading is performed at the point of the arrow in the figure. That is, the voice data a of the memory 1 is read first, the voice data b of the memory 2 is read next, and so on. It is assumed that the write phase and the read phase collide when the audio data e in the memory 1 is about to be read. Then, the clock transfer circuit of the present embodiment switches the memory in the read mode from the memory 1 to the memory 2 by the above-described operation, reads the audio data f from the memory 2, and thereafter repeats the normal read operation. As a result, the read audio data is a, b, c, d,
f, g, h ... and the audio data e is skipped. As described above, in the circuit of this embodiment, read data is discarded when a bit overflows.

Next, the case where the write clock (b) is fast will be described. Memory 1 as above
Every time a frame of time-division multiplexed data arrives, the audio data is stored in the memory 2 in the order of a, c, e, g, i ... Written in order. It is assumed that the voice data a in the memory 1 is read first, the voice data b in the memory 2 is read next, the voice data e is read, and so on, and then the voice data f in the memory 2 is read. It is assumed that a collision between the writing phase and the reading phase occurs when an attempt is made to read. At this time, the memory in the read mode is switched from the memory 2 to the memory 1, and the voice data e in the memory 1 is read again,
Next, the audio data f is read from the memory 2. As a result, the read audio data is a, b, c, d,
e, e, f, g, h ..., The audio data e is read twice. As described above, in the circuit of this embodiment, the read data is repeatedly read when a bit loss occurs.

When a bit loss occurs in the bit write / read phase collision as described above, the data of the previous frame is repeatedly transmitted, and when the bit overflows, the data is discarded, but when the data to be handled is voice data. Since the voice data has a strong correlation with the preceding and following data, there is an advantage in that the sense of noise in the auditory sense can be reduced as compared with inserting dummy data at the positions where the bits are missing / overflowed.

Various modifications are possible in carrying out the present invention. For example, in the above-described embodiment, two memories are provided as the memory for writing the time-division multiplexed data. However, three memories may be provided, and the time-division multiplexed data may be sequentially written in or read from them.

[0029]

As described above, according to the present invention, clock transfer can be performed without using a D / A converter or an A / D converter, so that the circuit scale of the clock transfer circuit can be reduced. it can. Further, when changing the clock of the audio data, it is possible to reduce the feeling of noise even if there is a write / read phase collision.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a clock transfer circuit as an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of a write / read phase monitoring unit in the embodiment circuit.

FIG. 4 is a time chart of an example circuit.

FIG. 5 is a diagram for explaining a state of read data at the time of write / read phase collision in the embodiment circuit.

FIG. 6 is a diagram showing a conventional example of a clock transfer circuit.

[Explanation of symbols]

 1, 2 memory 3 write memory switching signal generation unit 4 phase monitoring control unit 5 read switching unit 6 write clock generator 21 demultiplexer 22 D / A converter 23 A / D converter 24 multiplexer 40 read clock generator 41 read Switching signal generator 42 write / read phase monitor 43 toggle flip-flop 44 XOR gate 51, 52 AND gate 53 OR gate 54 flip-flop 421-424 AND gate 425, 426 flip-flop 427 OR gate

Claims (2)

[Claims] 1. A memory comprising a plurality of planes, wherein the write side uses a write clock to write time division multiplexed data by sequentially switching these memories for each frame, and the read side uses a read side clock to write these memories. In a clock transfer circuit that switches clocks by sequentially switching for each frame and reading out written data, a phase monitoring unit (11) that monitors and detects the collision of the write phase and the read phase in the same memory, A clock comprising a phase controller (12) for changing the read phase and separating the write phase and the read phase by a predetermined phase when the phase monitor detects a collision between the write phase and the read phase. Transfer circuit. 2. A two-sided memory as the memory, wherein the phase control section generates a read-out switching signal for switching between reading and non-reading of the two-sided memory, and the phase control section. The toggle switch whose polarity of the output signal is inverted by the collision detection signal from the monitoring unit, the read switching signal from the read switching signal generating unit and the output signal from the toggle switch are input, and the two-sided frame memory 2. The clock transfer circuit according to claim 1, comprising an exclusive OR gate for outputting a read memory switching signal designating one of the two as a read side.