JPH0526970A - Waveform generator - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a waveform generator that can efficiently output a waveform with arbitrary time resolution at high speed regardless of the memory hardware. A plurality of memories for output waveform data, a storage circuit control means for controlling the operation of the memories, an output switching means for switching a data signal of the memory, and an operation of the storage circuit control means and the output switching means. An operation speed control means for converting speed is provided, and the time resolution of an output waveform does not depend on the number of memories.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform generator, and more particularly to a memory reading method for outputting high speed waveform data.

[0002]

2. Description of the Related Art A conventional high-speed waveform output method of a waveform generator is to read waveform data from a plurality of (N in this case) waveform memories at the same time, sequentially switch the N data by a multiplexer, and perform DA conversion. It is output. (In the current high-speed waveform generation technology, since the access time of the memory is the most important problem, the speed can be increased by reading the data from the memory all at once.) For example, as shown in FIG. One repetitive waveform for (N + N
Consider the case of outputting based on ′) pieces of data. In the conventional example, N pieces of data are collectively output, and therefore, as shown in FIG. 4B, one repetitive waveform is (N + N
′) Is the least common multiple of N, data that has been repeated several times (here, i times) is stored in the memory, and this (N
+ N ′) × i data were output and dealt with.

[0003]

Therefore, there is a problem that a large amount of memory capacity is required. The present invention has been made to solve such a problem, and an object of the present invention is to show a waveform generator which outputs a waveform having an arbitrary time resolution at high speed.

[0004]

According to the present invention, a plurality of storage circuits in which data of output waveforms are stored, storage circuit control means for controlling the operation of the plurality of storage circuits, and a plurality of storage circuits are provided. The output switching means for switching the data signal of the output waveform data and the operation speed control means for converting the speed of the operation of the storage circuit control means and the output switching means are provided to generate a waveform composed of arbitrary digital data. It is a characteristic waveform generator.

[0005]

The output waveform having an arbitrary time resolution can be obtained by making the memory read cycle variable so that the memory read speed is variable.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a basic hardware configuration diagram of the present invention.

Reference numeral 1 denotes a storage circuit control means, which outputs a read address of the storage circuits 31 to 3n corresponding to a memory. Two
Is an operation speed control means for converting the operation speed of the memory circuit control means 1 and the output switching means 4, that is, for outputting a clock of a speed corresponding to the reading of the waveform of the data. Three
Is a storage means and comprises storage circuits 31 to 3n, which are memories in which waveform data are stored. Reference numeral 4 is an output switching means for switching and outputting the waveform data, which is a storage circuit 31.
The waveform data from ~ 3n is once held and sequentially output.

With such a configuration, when it is attempted to output a waveform for one cycle with (N + N ') number of data as shown in FIG. 4A, the output switching means outputs the data per one. Memory circuit 31 to be used without changing the speed
The read time of the memory circuits 31 to 3n is changed according to the number of 3n. This is set in the operating speed control means 2 and outputs a signal according to the setting to the memory circuit control means 1.
The memory circuit control means 1 reads the data from the memory circuits 31 to 3n at the read time based on the signal.

FIG. 2 shows an embodiment of the present invention. In the figure, the same parts as those in FIG. An address generator 11 outputs the address s2 to the waveform memories 31 to 3n in synchronization with the memory control clock from the frequency divider 2.
A clock switching memory 12 stores the access time setting of the waveform memory based on the control signal from the CPU 6. A counter 13 counts the memory control clock from the frequency divider 2, resets the count by setting from the clock switching memory 12, and starts counting. At the time of resetting, the memory circuit control means 1 in FIG. 1 is composed of these address generator 11, clock switching memory 12 and counter 13. Reference numerals 41 to 4N are registers for simultaneously storing the waveform data output from the waveform memories 31 to 3n. This is not limited to the case where the respective data of the waveform memories 31 to 3n are stored in the registers 41 to 4N, respectively.
It also includes the case of being input corresponding to each bit of 1 to 4N. Reference numeral 40 denotes a multiplexer, which outputs the data from the registers 41 to 4N to the output clock from the frequency divider 2 and the counter 1
Based on the signal s1 indicating the frequency of the control clock from 3, the signals s3 are sequentially output from the registers 41 to 4N. Further, the waveform data is written in advance in the waveform memories 31 to 3n via the multiplexer 7 which operates under the control of the CPU 6.

The operation of such a configuration will be described with reference to the time chart shown in FIG. At this time, the waveform memories 31 to ... Use 10 8-bit ones, and the registers 41 to ... Use 8 10-bit ones. The output data from the waveform memory 31 is the first bit of the registers 41 to 48, the output data from the waveform memory 32 is the second bit of the registers 41 to 48, and the output from the waveform memory 33 is the same. The data is used by the method of the third bit of the registers 41 to 48. The operation will be specifically described when the waveform in FIG. 4A is output as 52 pieces of data. In this case, the data from the registers 41 to 48 may be output three times and the data from the registers 41 to 47 may be output four times. That is, from the signal s3, there are eight, eight, eight, seven data in one cycle of the waveform.
The output will be 7 pieces, 7 pieces, 7 pieces, and 7 pieces. In addition, the clock switching memory 12 in FIG.
The information that the data from 48 to 3 is output three times and the data from the registers 41 to 47 is output four times is set. In FIG. 3, the read address is given to the waveform memory of the waveform generator having such a structure at any timing, and the multiplexer 40
Indicates whether the data is output from. First, since the frequency-divided signal s1 is set to output as the signal s3 by one access to the waveform memory, the frequency divider 2
Then, the cycle of the internal clock divided by 8 (1 / the internal clock
The read address s2 is output at a frequency of 8). The data read during this period is output as a signal s3 via the registers 41 to 48 and the multiplexer 40. The counter 13 counts the number of times the frequency-divided signal is output, and changes the frequency-divided signal s1 so as to output the data from the registers 41 to 47 when the signal is output three times as set. The frequency divider 2 receives the frequency-divided signal s1 and divides the internal clock by 7 to obtain a cycle (1 / the internal clock).
The read address s2 is output at the frequency of 7). Since the counter 13 is reset when the frequency-divided signal s1 changes, it counts how many times this cycle divided by 7 (frequency of 1/7 of the internal clock) is output, and is output four times as set. By the way, the divided signal s1 is again registered in the register 41.
Change to output data from ~ 48. In this example, the read cycle of the memory is three times with the signal divided by eight,
The signal divided by 7 is set to 4 times, but it depends on how many data the waveform is output.

As described in the above operation, the access time for reading the waveform memory is synchronized with the internal clock divided by 8 or 7 based on the setting, and the output switching setting of the multiplexer is changed. The limitation due to the fixed access time for reading the waveform memory as described above has been eliminated. Further, here, the reading of the memory is performed by the frequency divider 2
Although two types of clocks, that is, 8 and 7 are used, it is not limited to 8 or 7 and it is easy to design arbitrarily. The frequency divider 2 may be designed and the clock switching memory 12 may be set so that the number of data for one cycle of the waveform is obtained.

[0012]

According to the present invention, a waveform of an arbitrary number of data can be efficiently output at high speed regardless of the hardware of the memory.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the present invention.

FIG. 4 is an explanatory diagram of waveform output.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Storage circuit control means, 2 ... Operating speed control means (frequency divider), 3 ... Storage means, 4 ... Output switching means, 5 ... DAC, 6 ... CPU, 7, 40 ... Multiplexer, 11 ... Address generator, 12 ... Clock switching memory, 13 ... Counter, 31-3n ... Storage circuit (memory), 41-4N ... Register.

Claims (1)

Claim: What is claimed is: 1. A plurality of storage circuits in which data of output waveforms are stored, storage circuit control means for controlling the operation of the plurality of storage circuits, and outputs from the plurality of storage circuits. An output switching means for switching the signal of the waveform data and an operation speed control means for converting the speed of the operation of the memory circuit control means and the output switching means are provided to generate a waveform composed of arbitrary digital data. Waveform generator.