JPH0527193B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor storage devices such as RAM (random access memory). The present invention relates to a technique that is effective for use in a semiconductor memory device that is capable of detecting whether or not data with the same bit pattern exists therein and outputting the result.

[Background technology]

According to studies conducted by the present inventor, a semiconductor memory device (hereinafter referred to as a semiconductor memory) is configured such that data at an address corresponding to an externally applied address signal is read out. Therefore,
In a computer system using such semiconductor memory, when performing a large-scale information search, the addresses in the memory are accessed one by one and the corresponding data is read out to the outside, and the search data and the given search data are read out. It must be determined whether the bit patterns match.

However, since semiconductor memory requires a relatively long time to read data externally, the present inventors have found that there is a problem in that the larger the data, the longer the time required to search it becomes. It was revealed that

[Purpose of the invention]

This invention was made against the above-mentioned background, and has a function that detects whether or not data with the same bit pattern as that given from the outside exists internally, and outputs the result. It is an object of the present invention to provide a semiconductor memory that allows large-scale information searches and the like to be performed in a short time by incorporating a semiconductor memory.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, this invention has a comparison pattern register in the memory that temporarily holds a bit pattern given from the outside, and compares and matches the data read from the memory array in correspondence with the address. By providing a comparator circuit that detects whether the data is present or not and outputs an appropriate signal, it is possible to detect the same data without having to read out the data in the memory and detect whether it matches the given comparison bit pattern. It is possible to determine whether or not the data of the bit pattern exists in the memory, thereby making it possible to perform data matching determination and large-scale information retrieval in a short time.

The present invention will be specifically explained below using the drawings.

〔Example〕

FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to a dynamic RAM.

The circuit blocks shown in the figure are all formed on a single semiconductor substrate such as silicon by known semiconductor integrated circuit manufacturing techniques.

In the figure, 1 is a well-known 1MOS consisting of an information charge storage capacitor and a switch MOSFET.
This is a memory array in which type memory cells are arranged in a matrix. Although this memory array 1 is not particularly limited, for example, in a 64k bit RAM, it is arranged in a 256 x 256 bit matrix.

2a receives the X-system address signals supplied from external terminals A ₀ to _{A 7} and outputs internal address signals axi,
This is an X address buffer circuit that forms axi.
Further, 2b is a Y address buffer circuit which similarly receives Y-system address signals supplied from external terminals _A8 to _A15 and forms an internal address signal ayi.

Next, 3a is the X address buffer circuit 2a.
This is an X decoder circuit which receives an internal address signal axi outputted from the memory array 1 and sets a corresponding word line in the memory array 1 to a selection level. 3b is the Y address buffer circuit 2
This is a Y decoder circuit for receiving an internal address signal ayi outputted from the memory array 1 and selecting a corresponding data line in the memory array 1.

On one side of the memory array 1, each latch line is connected so that the data of all 256 memory cells connected to the word line set to the selected level by the X decoder circuit 2a can be read and latched. A readout circuit 4 consisting of 256 sense amplifiers is provided. Further, on the other side of the memory array 1, each data line in the memory array 1 is connected to a common data line to send data read out by the sense amplifier to the input/output circuit 5. A column switch circuit 6 consisting of 256 switches is provided. This column switch circuit 6 includes the Y decoder circuit 3b.
When a corresponding switch is turned on by an output signal from the input/output circuit 5, one bit of data on the selected data line is sent to the input/output circuit 5.
The signal is amplified by the main amplifier and output to the outside from the output terminal D _put .

On the other hand, when writing data, the data input from the input terminal D _io is sent to the X, Y decoder circuit 3 by the write driver in the input/output circuit 5.
The data is written into the memory cell selected by a and 3b.

The configuration up to this point is similar to that of a conventional general dynamic memory.

Therefore, in this embodiment, in addition to the above circuit block, there is also a comparison pattern register for temporarily holding a bit pattern given from the outside, and a comparison pattern register 7 that holds the bit pattern held in the comparison pattern register 7 and the memory array 1. A comparison circuit 8 is provided for comparing the bit pattern of data read out from within and held in the readout circuit 4.

Furthermore, in this embodiment, among the bit patterns held in the comparison pattern register 7,
A masking register 9 is provided for specifying the bits to be compared with the data read from the memory array 1 and for preventing data of other bits from being compared. Like the comparison pattern register 7, this mask register 9 can also be set by an externally applied signal.

The registers 7 and 9 are constituted by a kind of static RAM using a known flip-flop, and for example, this can be designated by the Y decoder 3b to input data from the outside to each bit. can. Furthermore, by combining appropriate logic gate circuits, for example, the comparator circuit 8 takes in only the data of the bits of the comparison pattern register 7 corresponding to the bits set to "1" in the mask register 9, and sends the data to the readout circuit. Compare with the data latched within 4 and output a match signal only when both bit patterns match.
Configured to output P _C.

Therefore, when a RAM like the above embodiment is used, in a microcomputer system, data (bit patterns) can be read out one by one from the memory, and the data can be checked to see if it matches a comparison bit pattern or not. Matching etc. can be done in a short time.

Further, by using the RAM of the above embodiment, it can be applied to the following large-scale information search using a computer.

That is, in each row in the memory array 1 of the RAM, a code serving as an index is attached to the beginning, and data having binary data indicating address information is stored afterward. The address information is information indicating a position (address) in another main memory where information organized by the index is stored. On the other hand, the comparison pattern register 7 stores the bit pattern of the data (index code) to be searched.
Further, "1" is written in the mask register 9 only for the bits corresponding to the number of bits of the index code.

Next, the memory array 1 is accessed row by row, and the data of the first row is read out to the reading circuit 4. Then, the comparator circuit 8 compares the code portion serving as an index of the data read from the memory array 1 with the search bit pattern held in the comparison pattern register 7. At this time, if the bit patterns do not match, the comparison circuit 8 will not output a match signal _P access the row. In this way, the data is read out line by line and compared with the search bit pattern one after another, and when the index code part and the search bit pattern match, the comparison circuit 8
The coincidence signal P _C is outputted to the outside. When the computer receives this match signal P _C , it drives the Y decoder circuit 3b to output the address information after the index code among the data held in the read circuit 4 to the outside.

If a computer reads the desired information from the main memory, which stores a large amount of information, using the addresses retrieved from the memory in this way, the necessary information can be obtained in a very short time.

When attempting to perform the above search using conventional semiconductor memory, the data to be searched must be read out from the memory one by one, and the computer itself must determine whether or not the pattern matches the search data. Nakatsuta. However, since reading from the memory to the outside requires a number of cycles equal to the number of bits of the data to be read, the time required for the match determination becomes extremely long. On the other hand, in a memory like the embodiment, the data to be searched is not read out bit by bit to the outside, but the pattern match or mismatch of all bits is determined at once inside the memory and the result is output. . Therefore, the time spent reading data to the outside is significantly reduced, and it becomes possible to search large-scale information at high speed.

Moreover, recent large-capacity memories adopt a configuration in which the X decoder circuit 3a reads one row of data to a sense amplifier, so a sense amplifier (readout circuit 4) that reads and holds one row of data is used. There is no need to create a new one, and the excellent functions described above can be added by adding a relatively simple circuit.

Note that the memory of the above embodiment is provided with a masking register 9 for specifying bits to be compared among one row of data read out by the readout circuit 4, but the number of bits to be compared ( If the number of bits of the index code is fixed or if all bit patterns are to be compared, it is possible to omit the masking register.

In addition, the comparison circuit 8 and the comparison pattern register 7
The masking register 9 is not limited to the configuration of the above embodiment.

〔effect〕

As explained above, the present invention has a comparison pattern register in the memory that temporarily holds a bit pattern given from the outside, and a comparison pattern that compares data read out from the memory array in correspondence with an address with the comparison pattern. The device is equipped with a comparison circuit that detects whether or not there is a match and outputs an appropriate signal (match signal), so the data in the memory is read out to the outside one by one and matches the given comparison bit pattern. It is possible to determine whether or not data with the same bit pattern exists in memory without having to detect whether or not the same bit pattern exists. This has the effect of making it possible to do so.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

[Application field]

In the above embodiment, the present invention is applied to a dynamic RAM, but the present invention is not limited to this and can be used in ROM (read-on memory) and other semiconductor storage devices in general.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory to which the present invention is applied. DESCRIPTION OF SYMBOLS 1...Memory array, 3a...Selection circuit (X decoder circuit), 4...Reading circuit, 7...Register for comparison pattern, 8...Comparison circuit.

Claims (1)

[Claims] 1 A plurality of 1MOS type memory cells are arranged in a matrix, and a code serving as an index is attached to the beginning of the memory cell in each row of the matrix, and then data having binary data indicating address information is input. a selection circuit that selects one row of memory cells in the memory array based on an address signal supplied from the outside; and data of one row of memory cells selected by the selection circuit. a readout circuit consisting of a sense amplifier configured to read and latch the data at once, a comparison pattern register that temporarily holds an externally applied bit pattern, and a register for the index specified by the selection circuit. A masking register configured so that first level data is input only for bits corresponding to the number of bits of the code, and a bit pattern read out to the readout circuit and a bit pattern of the comparison pattern register. and a comparison circuit that detects whether or not they match and outputs it to the outside, and the comparison circuit detects the bits of the comparison pattern register corresponding to the first level data held in the mask register. A semiconductor memory device characterized in that only data is fetched and compared with data latched in the readout circuit, and a match signal is output only when both bit patterns match.