JPH0527345B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an inverter that obtains variable voltage and variable frequency output, and particularly relates to an inverter control device that is effective when a control section circuit is integrated into an integrated circuit.

[Technical background of the invention]

For example, when controlling the rotation speed of an AC motor to perform constant torque operation, it is possible to use a variable voltage, variable frequency power supply to control the motor speed while keeping the ratio of motor terminal voltage and frequency constant. It is done. In this case, an inverter is the most common variable voltage, variable frequency power source.

FIG. 1 shows the configuration of a typical three-phase bridge inverter main circuit 1. As shown in FIG. In this case, a transistor is used as the switching element,
Each arm of the three-phase bridge is connected to a transistor Tr ₁ ,
It consists of transistors Tr ₂ , Tr ₃ , Tr ₄ , Tr ₅ and Tr ₆ , and a flywheel diode D is connected between the collector and emitter of each of these transistors Tr ₁ to Tr ₆ . And transistors Tr ₁ and Tr ₄ ,
The interconnection points of Tr ₂ and Tr ₅ and Tr ₃ and Tr ₆ are respectively output terminals T _U , _TV , and _TW , and these output terminals
A three-phase AC motor is connected as a load to T _U , _TV , and _TW . Furthermore, power is supplied to the inverter main circuit 1 with this configuration from the DC power supply 2, and the transistor Tr ₁
By switching Tr ₆ using the pulse width modulation method (hereinafter simply referred to as PWM method), three-phase AC output is obtained from the output terminals T _U , _TV , and T _W , and the frequency is determined by each transistor.
It can be adjusted by changing the switching period of Tr ₁ to Tr ₆ . Note that 3 is a capacitor for smoothing DC power.

FIG. 2 shows a conventional inverter control circuit. To simplify the explanation, only one phase will be described. In Fig. 2, 4 is a frequency setting circuit that outputs a frequency setting signal _S1 for setting the output frequency of the inverter main circuit 1, and this frequency setting signal S ₁ is applied to a rate multiplier 6 and a storage element, ie, a ROM (read only memory) 8. 5 is a clock that determines the output frequency
This is an oscillator for generating _S2 . The rate multiplier 6 is the output voltage V of the inverter main circuit 1.
This is to control the clock signal S2 so that it has a predetermined ratio relationship with the set frequency, and outputs a new clock signal _S2a by changing the frequency of the clock signal _S2 at a division ratio according to the frequency setting signal _S1 . do. 7 is a binary counter for forming a readout circuit that counts the clock signal S ₂ a output from the rate multiplier 6. The ROM 8 is adapted to receive the output from the binary counter 7 and the frequency setting signal _S1 from the frequency setting circuit 4.
ROM8 contains the setting frequency ₁ of the inverter main circuit 1.
In this example, a predetermined logic pattern for obtaining a voltage corresponding to n from D0 is stored for 180° every 30°, and the binary counter 7 reads out the stored contents of the ROM 8, with each 30° minute being _one cycle. ~ _D5
The output terminals have electrical angles of 0° to 30°, 30° to 60°, respectively.
60°~90°, 90°~120°, 120°~150°, 150°~180
Output the data signal _S4 of ゜ minutes. A hex counter 9 receives a carry signal S ₃ from the binary counter 7 and outputs a selector signal S ₅ for causing the data selector 10 for the storage element to select the data signal S ₄ from the ROM 8. In this way, the data selector 10 outputs a signal _S6 corresponding to 0° to 180° electrical angle at a frequency corresponding to the output of the frequency setting circuit 4, that is, the set speed. 11 is an inverting circuit, which obtains a signal S ₇ conjugate with the signal S ₆ , and the transistor Tr ₁ of the inverter main circuit 1
S ₆ is given for Tr 4, S ₇ is given for Tr ₄ , etc., while S ₆ and S ₇ are given as Tr ₄ and S 7, respectively.
For Tr ₁ , it is a signal with an electrical angle of 180° to 360°. [Problems in the Background Art] Conventionally, in the case of such a circuit configuration, a fixed frequency oscillator such as a crystal oscillator or a ceramic oscillator is used as the oscillator 5. For example, the maximum frequency is 512 Hz and 2 Hz When trying to obtain pitch frequency steps, the data signal for 30° is
If the number of words in _S4 is 256, an oscillator with an oscillation frequency of 256×12×255/256×512=1566720 (Hz) is required.

If, for example, the control section within the two-dot chain line in FIG. 2 is to be integrated into an integrated circuit due to equipment downsizing or economical demands, it is difficult to integrate the oscillator 5 with the same circuit configuration. Since the maximum frequency and frequency pitch are uniquely determined, for example, if a plurality of frequency specifications are required for one inverter device, it is necessary to change the external oscillator 5 itself.

On the other hand, the 30° worth of data stored in ROM8 is
As shown in FIG. 3, the pulse train M ₀ obtained by comparing the sine wave Sa and the triangular wave Sb is quantized and applied to a predetermined number of words (256 words in this example). For this reason, for example, if you want to change the word count by half due to cost considerations,
If the oscillator 5 were used as is, the output frequency would double. Therefore, in this case, countermeasures such as changing the frequency of the oscillator of the oscillator 5 would be required, and the basic circuit This results in the disadvantage that standardization of parts becomes uneconomical.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object thereof is to provide an inverter control device that has effects such as being able to obtain a plurality of frequency specifications without changing the oscillator.

[Summary of the invention]

The inverter control device of the present invention controls on/off switching elements of an inverter main circuit using data stored in a storage element in a voltage pattern corresponding to each set frequency, thereby establishing a predetermined ratio relationship between frequency and voltage. In an inverter configured to obtain a variable frequency variable voltage that maintains a constant frequency, a frequency dividing circuit is provided that divides a clock signal from an oscillator and outputs a plurality of types of frequency-divided clock signals, and selects the frequency-divided clock signal. The readout frequency of the voltage pattern from the memory element can be changed by

[Embodiments of the invention]

Next, regarding one embodiment of the present invention, FIGS.
Referring to FIG. 5 and FIG. 5, only one phase will be described here to simplify the explanation. In FIG. 4, the circuit configuration is similar to that of the conventional example, but in this embodiment, the clock signal _S8 from the oscillator 12 is counted by a 4-bit binary counter 13, which is a frequency dividing circuit. The output terminal Q ₀ of this binary counter 13,
From Q ₁ , Q ₂ , and Q ₃ , the clock signal S ₈ is divided by 2 and 4
Divided, divided by 8, and divided by 16 clock signals
S ₉ , S ₁₀ , S ₁₁ , and S ₁₂ are output, respectively. Also, 1
Reference numeral 4 designates a data selector for a frequency dividing circuit which receives frequency divided clock signals S ₉ , S ₁₀ , S ₁₁ and S ₁₂ , and its specific configuration is shown in FIG. That is,
The frequency dividing circuit data selector 14 is constructed by connecting NAND gates 15, 16, 17, 18, 19 and inverters 20, 21 as shown. Therefore, when the instruction signals S ₁₃ and S ₁₄ inputted to the selector terminals 22 and 23 respectively have logical values "0, 0", only the NAND gate 15 is opened and the divided clock from the binary counter 13 is output. A signal _S9 is output from the NAND gate 19 as a signal for determining the output frequency. Similarly, when the instruction signals S ₁₃ and S ₁₄ have logical values of "1, 0" respectively,
A divided clock signal _S10 is output from the NAND gate 19 via the NAND gate 16, and an instruction signal
If S ₁₃ and S ₁₄ are logical values “0, 1” respectively,
The divided clock signal _S11 is output from the NAND gate 19 via the NAND gate 17, and the instruction signal
If S ₁₃ and S ₁₄ have logical values “1, 1” respectively,
A divided clock signal S ₁₂ is output from the NAND gate 19 via the NAND gate 18 . The above-mentioned components are different from the conventional ones, and the other frequency setting circuit 4, rate multiplier 6, binary counter 7, ROM 8, hexadecimal counter 9, memory element data selector 10, and inversion circuit 11 are different from the conventional ones. Similar configurations apply.

The operation of the circuit shown in FIG. 4 constructed as above will be explained. That is, the clock signal _S8 output from the oscillator 12 is frequency-divided by 2, 4, 8, and 16 by the binary counter 13. ₉ , _S10 ,
S ₁₁ and S ₁₂ are input to the frequency divider circuit data selector 14. In this case, an instruction signal having a logical value of "1, 0", for example, is sent to the select terminals 22 and 23, respectively.
When S ₁₃ and S ₁₄ are input, the divided clock signal S ₁₀ (that is, the signal obtained by dividing the clock signal S ₈ by 4) is output from the frequency dividing circuit data selector 14 and sent to the rate multiplier 6. is input. On the other hand, the frequency setting signal S ₁ from the frequency setting circuit 4 is given to the rate multiplier 6 and the ROM 8 . The rate multiplier 6 changes the frequency of the divided clock signal _S10 at a division ratio according to the frequency setting signal S1 so that the output voltage V of the inverter main circuit ₁ has a predetermined ratio relationship with the set frequency. and outputs a new clock signal _S10a . The clock signal _S10a is input to a binary counter 7, which outputs a binary signal. By the binary signal output in this way
Each address in ROM8 is repeatedly addressed and the ROM
8 output terminals _D0 to _D5 respectively electrical angle 0° to 30°, 30° to 60°, 60° to 90°, 90° to 120°, 120° to 150°, 150°
゜～
A 180° data signal _S4 is output. On the other hand, the carry signal S ₃ from the most significant digit of the binary counter 7
is input to the hexadecimal counter 9, and the corresponding 6
The select signal _S5 outputted from the advance counter 9 causes the storage element data selector 10 to select and pass the data signal _S4 from the ROM 8. In this way, the memory element data selector 1
A signal S ₆ ranging from 0 to 180 degrees in electrical angle is output at a frequency matching the frequency setting signal S ₁ (ie, the set speed). Then, in the inverting circuit 11, a signal S ₇ conjugate with the signal S ₆ is obtained, and these signals S ₆ and S ₇
As a result, transistors Tr ₁ and Tr ₄ in the inverter main circuit 1 shown in FIG. 1 are driven.

As described above, when the instruction signals S ₁₃ and S ₁₄ have logical values of "1, 0", and the oscillation frequency of the oscillator 12 is, for example, 1566720 Hz, the maximum frequency max obtained by the inverter main circuit 1 is max =1566720×256/255×1/12×1/256×1/4 =128Hz, and the frequency pitch is 0.5Hz.

Furthermore, when the instruction signals S ₁₃ and S ₁₄ are respectively "0, 0" (that is, the divided clock signal S ₉ obtained by dividing the clock signal S ₈ by 2 is applied to the rate multiplier 6), the inverter main circuit The maximum frequency obtained by 1 is 256Hz, and the frequency pitch is 1Hz.
become. Similarly, the instruction signals S ₁₃ and S ₁₄ are respectively “0,
1" (i.e., the state where the frequency clock signal _S11 obtained by dividing the clock signal _S3 by 8 is given to the rate multiplier 6), the maximum frequency max is 64.
Hz, the frequency pitch is 0.25Hz, and the instruction signal S ₁₃ ,
When _S14 are respectively "1, 1" (that is, the divided clock signal _S12 obtained by dividing the clock signal by 16 is applied to the rate multiplier 6), the maximum frequency max is 32Hz and the frequency pitch is 0.125Hz. become.

According to the above configuration, when the control section 24 in the inverter, for example, shown by the two-dot chain line in FIG. It is not uniquely determined, and four types of maximum frequency and frequency pitch can be obtained. Therefore, the maximum frequency that matches the quality of characteristics and quality of rotation of the motor operated by one inverter can be obtained. It is economically advantageous because the frequency can be selected.

In addition, although the example described the case of three phases,
It goes without saying that the single-phase case can also be realized by using the signal for one phase.
Furthermore, the frequency division ratio of the binary counter 13 may be changed, or the number of frequency-divided clock signals may be more varied, and the number of inputs to the frequency-dividing circuit data selector 14 may be increased accordingly.

〔Effect of the invention〕

As explained above, the present invention provides a frequency dividing circuit that divides the frequency of a clock signal from an oscillator and outputs a plurality of types of frequency-divided clock signals, and selects the frequency-divided clock signal to generate a clock signal from a storage element. Since the readout frequency of the voltage pattern can be changed, it is possible to change the readout frequency of the voltage pattern.
With one inverter device, multiple frequency specifications can be obtained without making any changes to the oscillator.
An inverter control device with a good balance between cost and performance can be realized.

[Brief explanation of drawings]

Fig. 1 is a wiring diagram showing the conventional inverter main circuit configuration, Fig. 2 is a block diagram showing the control circuit of the conventional inverter main circuit, Fig. 3 is a diagram showing a method for determining the contents to be stored in ROM, FIG. 4 is a block diagram showing one embodiment of the present invention, and FIG. 5 is an explanatory diagram of the main parts. In the figure, 4 is a frequency setting circuit, 6 is a rate multiplier, 7 is a binary counter, and 8 is a ROM
(storage element), 9 is a hexadecimal counter, 10 is a data selector for the storage element, 12 is an oscillator, 13 is a binary counter (frequency dividing circuit), and 14 is a data selector for the frequency dividing circuit.

Claims (1)

[Claims] 1: an oscillator that generates a clock signal with a constant period; a frequency divider circuit that divides the frequency of the clock signal and outputs multiple types of divided clock signals as signals for frequency determination; a rate multiplier which is provided to be selectively inputted via a data selector and which changes the frequency by dividing the frequency-divided clock signal by a division ratio according to the frequency setting signal; A memory element that stores the on/off timing of the switching element of the inverter to obtain a corresponding voltage pattern; a binary counter that receives the output clock signal of the rate multiplier and addresses the memory element at a constant cycle; and the binary counter. An inverter control device comprising: a counter that counts the output of the storage element; and a storage element data selector that uses the output of the storage element as data and the output of the counter as a select signal.