JPH0528034A - Memory capacity setting method - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] The memory capacity can be set easily and surely, and even if there is an unmounted part, crosstalk and signal delay do not occur. [Structure] The memory control unit 1 is provided with a memory capacity setting circuit 18 for supplying a signal for determining mounting or non-mounting of a memory element for each memory bank, and the memory capacity setting circuit 18 has two resistors R1 and R2 when the memory element is mounted. The first logical level signal determined by the voltage division is output, and when not mounted, the second logical level signal determined by removing either one of the resistors R1 and R2 is output. Further, a 3-state type buffer element is used for the buffer element section 2, and when the memory element is mounted, it is enabled by the first logic level signal from the memory capacity setting circuit 18, and when it is mounted in the emergency state, it is buffered by the second logic level signal. The output is placed in a disable state that maintains high impedance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory capacity setting method for a memory system that enables module boards for a plurality of documents having different memory capacities by limiting the mounting capacity for each bank. There are various memory capacities of a memory system mounted on a computer device or the like, and a module board is created for each general memory capacity.

However, when a module board is manufactured for each memory capacity, it is necessary to replace the module itself in order to increase the memory capacity, and the module board used up to that point is wasted. Therefore, the maximum mounting capacity of the module board is determined, and the actual mounting capacity is reduced in bank units within the range of the maximum mounting capacity so that a plurality of types of memory capacities can be obtained.

However, the memory capacity setting in this case is as follows.
For example, a dip switch is used, but the reliability is extremely low, the mounting space is large, and the cost is disadvantageous. Furthermore, when only the memory element is not mounted, the buffer element that drives the memory element is in an unloaded state, which causes a problem of signal delay due to crosstalk to the mounting side and a change in capacitance. It is necessary to set the memory capacity that solves this point.

[0004]

2. Description of the Related Art Conventionally, when setting a memory capacity in a memory system using module boards of the same function having different memory capacities, the module boards themselves are made different for each memory capacity. However, when the memory capacity is set differently for each module, the number of types of module boards increases, and manufacturing management becomes complicated.

Further, when it is desired to increase the memory capacity by version upgrade or the like, the module board with a larger memory capacity will be replaced, but the module board with a smaller memory capacity used until then must be discarded. . In order to avoid this waste, it is impossible to increase the memory capacity of the used module board except to increase the capacity per memory element.

In order to solve this problem, the maximum mounting capacity of the module board is determined, and by partially setting the actual mounting capacity of the memory element in bunsk units within the range of the maximum mounting capacity, a plurality of types of memory can be obtained. I am trying to set the capacity. Then, when such partial setting of the memory capacity is performed, a DIP switch is provided on the module board and the memory capacity corresponding to the partial setting is set in the memory control unit (MCU).
An error is returned when an unloaded bank address is accessed.

[0007]

However, although the memory capacity can be easily set using the DIP switch, the DIP switch is extremely unreliable and has a problem such as a malfunction due to a setting error. There is. Further, the memory system in which the memory capacity is partially set has the following problems.

First, when only the memory element is not mounted while the buffer element for controlling the memory element is mounted, the element for receiving on the signal line driven by the buffer element is absent. That is, the buffer element is in an unloaded state. In this case, the undershoot and overshoot at the change point of the signal driven by the buffer element are
Since it becomes larger than when a memory element is mounted (when a load is connected), crosstalk with another adjacent signal system occurs, and a malfunction easily occurs. In order to avoid this, special consideration is required in the pattern design of the printed circuit board.

When both the buffer element and the memory element are not mounted, the memory control unit (MC
The capacitance of the signal line from U) to the buffer element may change, causing a problem such as signal delay. The present invention has been made in view of such conventional problems,
An object of the present invention is to provide a memory capacity setting method for a memory system in which the memory capacity can be set easily and surely, and memory elements that do not cause crosstalk or signal delay due to unimplemented parts can be partially set in bank units. And

[0010]

FIG. 1 is a diagram for explaining the principle of the present invention. First, the present invention relates to a plurality of memory banks each having a certain memory capacity, which are composed of a plurality of memory elements, and a memory control unit (M
CU) 1 and a buffer element unit 2 that buffers the address signal and the memory control signal output from the memory control unit 1 and sends them to the memory element are mounted on the module board, and the number of banks mounted on the module board is always The target is a memory capacity setting method for a memory system that allows multiple kinds of memory capacities by restricting mounting in bank units rather than the maximum number.

In the present invention as a memory capacity setting method for such a Lomori system, a memory capacity setting circuit 18 is provided to the memory control unit 1 for supplying a signal for deciding whether or not to install a memory element for each memory bank. The memory capacity setting circuit 18 is provided to output the first logic level signal determined by the voltage division of the two resistors R1 and R2 when the memory element is mounted, and is determined by removing one of the resistors R1 and R2 when not mounted. The second logic level signal is output.

More specifically, the memory capacity setting circuit 18 includes a first resistor R1 on the ground side and a second resistor R1 on the positive power source side.
By having a series circuit with the resistor R2 and making the first resistor R1 of this series circuit sufficiently smaller than the second resistor (R1
<< R2), the first and second resistors R1 and R2 when mounted
The low level signal determined by the voltage division is output, and the high level signal determined by not mounting the first resistor R1 when not mounted is output.

Further, a 3-state type buffer element is used for the buffer element section 2, and when the memory element is mounted, the first logic level signal from the memory capacity setting circuit 18 is provided in the buffer element section 2 and the enable terminal of the buffer element is provided. To enable the output corresponding to the input,
In the case of emergency mounting, the second logic level signal is applied to the buffer element 3
It is characterized in that the output is always in a high impedance state even if the input level is changed by receiving it at the enable terminal.

[0014]

According to the memory capacity setting system of the present invention having such a configuration, the following effects can be obtained. First, for setting the memory capacity, one resistor R1 of the voltage dividing circuit provided in the memory capacity setting circuit may be mounted when the memory element is mounted and not mounted when the memory element is not mounted. With or without mounting, the memory capacity can be set easily by letting the memory control unit recognize whether or not it is mounted, and reliability is maintained.

Further, the version upgrade from the small memory capacity to the large memory capacity is required only by additionally mounting the resistors for the number of banks together with the memory elements, and the same printed circuit board can be used. On the other hand, since the buffer element is still mounted on the unmounted portion, there is no change in capacitance as in the case where the buffer element is not mounted.

Further, the buffer element of the unmounted portion of the memory element is automatically disabled by a signal from the memory capacity setting circuit, and the output is always kept in the high impedance state even if the buffer input changes, and No crosstalk is exerted on the signal system, malfunctions can be prevented, and no special consideration is required in pattern design.

[0017]

FIG. 2 is a block diagram of an embodiment showing one embodiment of the present invention, showing a state where memory elements are mounted in all memory banks. In FIG. 2, reference numeral 1 denotes a memory control unit (MCU), and the memory control unit 1 is provided with RAMs 4a and 4b.

The RAMs 4a and 4b are composed of, for example, DRAM, and eight DRAMs form one bank. In this embodiment, a RAM 4a composed of 8 DRAMs is provided in a bank # 0,
Two banks, where the RAM 4b is the two banks of the bank # 1, are taken as an example. Of course, the maximum number of bunches can be arbitrarily determined as necessary, and one bank may have eight or more DRAMs.

Here, the bank # 0 is a fixedly mounted bank, while the bank # 1 is a bank that can be mounted or not mounted. RAM4 in banks # 0 and # 1
For a and 4b, the RAS / CAS / WE line 12 is used as a control line for horizontally controlling the address line 10 and the memory.
Is provided.

The address line 10 is connected to each address pin of the memory elements in the RAMs 4a and 4b as indicated by black circles. In this embodiment, the number of address lines 10 is two in order to simplify the description, but the number of address lines corresponding to the memory capacity per bank is provided, for example, 1M.
10 x 4M x 1bit DRAM, 4M x 1bit D
In the RAM, 11 address lines are provided.

The RAS / CAS / WE line 12 is RA
They are connected to the RAS / CAS / WE pins in M4a and 4b as indicated by black circles. Actually, WE line (write enable line), RAS line (row control line) and C
Although three AS lines (column control lines) are provided, they are shown as one RAS / CAS / WE line 12 to simplify the description.

Further, eight data lines 14 are taken out from the memory control unit 1 to be used in the RAMs 4a and 4b.
In the vertical direction, and bit b0 of banks # 0 and # 1
To b7 are connected to the data pins of the RAMs 2a and 2b at the same position. Address lines 8 and 10 and RAS / CAS / WE lines 9 and 12 from the memory control unit 1
Are connected to the buffer elements 3 in the buffer element portions 2a and 2b provided corresponding to the banks # 0 and # 1. The buffer element 3 is a three-state buffer element having an enable terminal, and is in an enable state when the signal level of the enable terminal is L level, and outputs a signal corresponding to the logical level of an input address signal to the address line 12, for example. . Further, when the signal level of the enable terminal is set to the H level, it becomes the disable state, and the output is held in the high impedance state even if the input address signal changes.

Further, a memory capacity setting circuit 18 is provided for the memory control unit 1. The memory capacity setting circuit 18 is provided corresponding to the memory bank # 1 that can be mounted or not mounted.
In the mounted state, the series circuit of the first resistor R1 and the second resistor R2 is connected between the ground side and the positive power source + Vcc, and the divided voltage is output as the memory capacity setting signal 15.

Here, the relation of R1 << R2 is set between the resistors R1 and R2. Therefore, the memory capacity setting signal 15 as the divided voltage of the resistors R1 and R2 is logically set to the L level below the threshold level of the memory control unit 1 and the buffer element 3.

Therefore, when the memory capacity setting signal 15 is at the L level, the memory control unit 1 determines that the RAMs 4a and 4b for two banks are mounted.
Further, the memory capacity setting signal 15 is brought into an enable state by setting the enable terminal of the buffer element 3 on the bank # 1 side to the L level, and the address line 10 and CAS / RAS /
The WE line 12 is brought into a drive state.

The enable terminal of the buffer element 3 on the bank # 0 side is fixed to the drive state by being grounded. The memory operation by the memory control unit 1 is as follows. The memory control unit 1 determines the access address to the memory system from the system bus 17, and the access destination is the RAM of the bank # 0.
4a, bank # 0 together with address lines 8 and 10.
RAS / CAS / WE lines 9 and 12 for
Access to bank # 0.

At this time, the address line 10 of the bank # 1 also changes completely in synchronization with the address line 10 of the bank # 0, but the RAS / CAS / WE line 12 for the bank # 1 does not change, so the bank # 1 The RAM 4b of No. 1 keeps its output in a high impedance state, and writing is not performed. FIG. 3 is a block diagram of an embodiment in which the RAM 24 of the bank # 1 of FIG. 2 is not mounted.

When the eight RAMs 4a of bank # 1 are not mounted in FIG. 2, the ground-side resistor R1 of the memory capacity setting circuit 18 is not mounted. Since the resistor R1 is not mounted, the memory capacitance setting circuit 18 has only the resistor R2 as a pull-up resistor, and the memory capacitance setting signal 15 becomes an H level signal, contrary to the case of FIG. When the memory capacity setting signal 15 is at the H level, the memory control unit 1 determines that the bank # 1 is not mounted, and if the address corresponding to the bank # 1 is accessed from the system bus 17, the unmounted area is Returns an error indicating that it was accessed.

At the same time, since the input to the enable terminal of the buffer element 3 on the bank # 1 side also becomes H level, the buffer element 3 is disabled. Therefore, the output of the buffer element 3 becomes high impedance, and the bank # 1
The address line 10 and the RAS / CAS / WE line 12 are not driven. In the above embodiment, the memory capacity setting circuit outputs the memory capacity setting signal 15 which becomes L level when the bank is mounted and becomes H level when the bank is not mounted.
The logic levels may be opposite. In this case, the memory capacity setting signal 15 is inverted and then supplied to the buffer element of bank # 1.

In the above embodiment, the bank which can be mounted or not mounted is selected as one of the banks # 1. However, a bank which can be appropriately registered and unregistered can be selected as required. May be increased, and in this case, the memory capacity setting circuit 18 is also increased.

[0031]

As described above, according to the present invention, it is possible to easily set different memory capacities by using the same module board by selecting mounting and non-mounting in bank units. The setting can be easily decided by mounting or not mounting one resistor corresponding to the bank, and the reliability can be guaranteed.

Further, it is possible to select mounting or non-mounting of only the memory element, and it is possible to automatically disable the buffer element corresponding to the unmounted bank by the memory capacity setting signal to keep the output at high impedance. , It is possible to prevent malfunction due to crosstalk and signal delay due to electrostatic capacity, which is particularly effective when a high-speed memory element is used.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention when memory elements are mounted in all banks.

FIG. 3 is a configuration diagram of an embodiment of the present invention when bank # 1 is not mounted.

[Explanation of symbols]

1: Memory control unit (MCU) 2, 2a, 2b: buffer element section 3: Buffer element 4a, 4b: RAM (DRAM) 10: Address line 12: RAS / CAS / WE line 14: Data line 15: Memory capacity setting signal 17: System bus 18: Memory capacity setting circuit

Claims (3)

[Claims] 1. A plurality of memory banks each having a fixed memory capacity composed of a plurality of memory elements, a memory control unit 1 for controlling the memory elements, and an address signal and a memory output from the memory control unit 1. A plurality of buffer elements are provided by mounting a buffer element section 2 for buffering a control signal and sending the same to the memory element on a module board, and the number of banks mounted on the module board is not always the maximum number, but by mounting restrictions on a bank-by-bank basis. In a memory capacity setting method of a memory system capable of taking various kinds of memory capacities, a memory capacity setting circuit for supplying a signal for determining mounting or non-mounting of a memory element for each memory bank to the memory control unit 1. 18 is provided, and the memory capacity setting circuit 18 has two resistors when a memory element is mounted. The first logic level signal determined by the voltage division of the anti-R1 and R2 is output, and the second logic level signal determined by removing one of the resistors R1 and R2 when not mounted is output. Memory capacity setting method. 2. The memory capacity setting system according to claim 1, wherein the memory capacity setting circuit 18 comprises a ground-side first resistor R1.
And a second resistor R2 on the positive power source side in series, and by making the first resistor R1 of the series circuit sufficiently smaller than the second resistor, the first and second resistors R1, R when mounted
A memory capacity setting method, which outputs a low level signal determined by a voltage division of 2, and outputs a high level signal determined by not mounting the first resistor R1 when not mounted. 3. The memory capacity setting method according to claim 1, wherein a buffer element of 3-state type is used in said buffer element section 2, and when the memory element is mounted, the first logic from said memory capacity setting circuit 18 is used. A level signal is received by the enable terminal of the buffer element provided in the buffer element section 2 to generate an output corresponding to the input, and in the emergency mounting, the second logic level signal is received by the enable terminal of the buffer element 3. The memory capacity setting method is characterized in that the output is always in a high-impedance state even if the input level changes.