JPH0528094A - Dma data transfer device - Google Patents

Abstract

PURPOSE:To shorten the DMA data transfer time by performing the transfer operation in parallel and transferring data without temporary storage operation. CONSTITUTION:When data DA10 is transferred from a data transfer source 61 connected to a bus 51 to a data transfer destination 62 connected to a bus 52, control signals CS11a and CS11b and addresses AD11a and AD11b are outputted from control signal and address generating circuits 42-1 and 42-2 to the data transfer source 61 and the data transfer destination 62 in parallel. Busses 51 and 52 are mutually connected by a bus connecting circuit 43. Data DA10 read out from the data transfer source 61 is sent to the data transfer destination 62 through the bus 51, the bus control circuit 43, and the bus 52.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a central processing unit (CP
Dual address type that performs data transfer from multiple data transfer sources to multiple data transfer destinations or from multiple data transfer sources connected to the same bus to other data transfer destinations in parallel without U) Such as DMA (direct mem
ory access) The present invention relates to a data transfer device.

[0002]

2. Description of the Related Art Conventionally, in this type of DMA data transfer device, for example, there are those shown in FIGS. The configuration will be described below with reference to the drawings.

FIG. 2 shows a conventional dual address DMA.
It is a block diagram of a data transfer device.

The DMA data transfer device 10 is a device for performing a dual address DMA transfer between two buses 21 and 22. A data transfer source 31 such as a memory or a controller is connected to one bus 21 and the other bus 22
Also, a data transfer destination 32 such as a memory or a controller is connected.

DMA connected between the buses 21 and 22
The operation of the data transfer device 10 is controlled by a CPU (not shown), and outputs a control signal CSla and an address ADla to the data transfer source 31 and a control signal CSlb and an address A to the data transfer destination 32.
It has a function of outputting Dlb, and further has a data transfer source 31
The read data DA from is temporarily stored and the data transfer destination 3
A memory 11 for outputting to 2 is provided.

FIG. 3 is a diagram showing the lapse of time in the operation of FIG. 2, and the data transfer operation of FIG. 2 will be described with reference to this figure.

In dual address DMA transfer, D
In the MA data transfer device 10, when accessing the data transfer source 31 and the data transfer destination 32, it is necessary to output the addresses ADla and ADlb to them.

When the data DA is transferred from the data transfer source 31 to the data transfer destination 32, as shown in FIG.
The DMA data transfer device 10 outputs the control signal CSla and the address ADla of the data transfer source 31 on the bus 21 side. In the data transfer source 31, as shown in FIG. 3B, the read operation is performed by the control signal CSla, the data DA of the input address ADla is output to the bus 21, and the data DA is stored in the DMA data transfer device 10. Is temporarily stored in the memory 11.

Next, in the DMA data transfer device 10, as shown in FIG. 3C, the data transfer destination 32 on the bus 22 side is shown.
The control signal CSlb and the address ADlb are output.
Then, the data transfer destination 32 starts its operation by the control signal CSlb, and as shown in FIG. 3D, when the storage data DA is output from the memory 11 to the bus 22, the data DA receives the address ADlb of the data transfer destination 32. Stored in.

FIG. 4 shows another conventional dual address type D.
It is a block diagram of a configuration of an MA data transfer device.

The DMA data transfer device 10A has a function of performing a dual address DMA transfer from a data transfer source 31 connected to one bus 21 to a data transfer destination 32 under the control of a CPU (not shown). Signal CS
The memory 11A has a function of outputting la, CSlb and addresses ADla, ADlb, and includes a memory 11A for temporarily storing data DA.

FIG. 5 is a diagram showing the lapse of time in the operation of FIG. 4, and the data transfer operation of FIG. 4 will be described with reference to this figure.

When performing a dual address DMA transfer from the data transfer source 31 to the data transfer destination 32, in the DMA data transfer device 10A, as shown in FIG. 5A, the control signal CSla and the address ADla of the data transfer source 31 are transferred.
Is output. In the data transfer source 31, as shown in FIG. 5B, the operation is started by the control signal CSla, and the data DA of the address ADla is output to the bus 21.

The data DA on the bus 21 is temporarily stored in the memory 11A in the DMA data transfer device 10A. D
The MA data transfer device 10A outputs the control signal CSlb and the address CSla of the data transfer destination 32, as shown in FIG. Then, as shown in FIG. 5 (4), the data transfer destination 32 starts operating, and the data DA stored in the memory 11A is stored in the address ADlb of the data transfer destination 32 via the bus 21.

[0015]

However, the conventional device has the following problems.

(A) In the conventional DMA data transfer apparatus 10 of FIG. 2, at the time of data transfer, the control signal CSla and the address ADl of the data transfer source 31 are sent to the bus 21.
a is output, and the data DA output from the data transfer source 31 is temporarily stored in the memory 11. The DMA data transfer device 10 then transfers the data transfer destination 32 to the bus 22.
The control signal CSlb and the address ADlb are output, the data DA temporarily stored in the memory 11 is output in series, and the temporary data DA is stored. Therefore, there is a problem that the data transfer time becomes long.

(B) DMA data transfer device 10A of FIG.
Then, as in FIG. 2, the data transfer source 3
The control signal CSla of 1 and the address ADla are output,
The data DA output from the data transfer source 31 is temporarily stored in the memory 11A. Then, the DMA data transfer device 10A outputs the control signal CSlb and the address ADlb of the data transfer destination 32, outputs the data DA temporarily stored in the memory 11A, and performs the operation such that the data DA is temporarily stored in the memory 11A. The action of remembering is necessary. Therefore, as in the case of (a), there is a problem that the data transfer time becomes long.

The present invention provides a DMA data transfer device which solves the problem that the prior art has, that the transfer operation is performed in series and the data transfer time becomes long because the transfer data is temporarily stored. To do.

[0019]

In order to solve the above-mentioned problems, the first invention is a DM for transferring data between a plurality of buses.
In the data transfer device A, a control signal / address generating circuit that outputs a control signal and an address in parallel to a data transfer source and a data transfer destination on each bus side at the time of data transfer, and the plurality of buses are connected to each other, and And a bus connection circuit for performing data transfer from the data transfer source side bus to the data transfer destination side bus. The second invention is
In a DMA data transfer device for transferring data from a data transfer source connected to a bus to a data transfer destination, a control signal / address for outputting a control signal and an address in parallel to the data transfer source and the data transfer destination, respectively, at the time of data transfer. A generation circuit; and a bus division / connection circuit that divides the bus between the data transfer source and the data transfer destination at the time of outputting the control signal and the address, and connects the divided buses at the time of the data transfer. Is equipped with.

[0020]

According to the first aspect of the present invention, since the DMA data transfer device is configured as described above, the control signal / address generating circuit transmits the control signal and the address in parallel to the data transfer source and the data transfer destination, respectively. Output. Then,
Data is read from the data transfer source, transferred to the data transfer destination via the bus connection circuit connecting the buses, and stored therein.

According to the second invention, when data is transferred from the data transfer source to the data transfer destination, the bus is divided into the data transfer source side and the data transfer destination side by the bus dividing / connecting circuit, and then the control signal is transmitted. -The address generation circuit outputs control signals and addresses in parallel to the data transfer source and the data transfer destination, respectively. Then, the data read from the data transfer source is directly transferred to the data transfer destination via the bus dividing / connecting circuit that connects the bus dividing points, and is stored there. Therefore, the above problem can be solved.

[0022]

1 is a block diagram showing the configuration of a dual address type DMA data transfer device according to a first embodiment of the present invention.

The DMA data transfer device 40 is a device for performing a dual address DMA transfer between two buses 51 and 52, and each of the buses 51 and 52 has data such as a memory and a controller which are distinguished by an address. Transfer source 61
And the data transfer destination 62 are connected to each other.

The operation of the DMA data transfer device 40 is controlled by a CPU (not shown), and a control section 41 for controlling the entire apparatus and a control signal / address generation circuit 42-1 controlled by the control section 41. , 42-2 and a bus connection circuit 43.

One control signal / address generation circuit 42-
Reference numeral 1 is a circuit for outputting the control signal CSlla and the address ADlla to the data transfer source 61 at a predetermined timing, and similarly the other control signal / address generating circuit 4
2-2 indicates a control signal CSll to the data transfer destination 62.
It is a circuit that outputs b and address ADllb. The bus connection circuit 43 is a circuit that connects the buses 51 and 52 at a predetermined timing, and is a circuit that transfers the data DA10 of the data transfer source 61 read onto the bus 51 to the bus 52.

FIG. 6 is a diagram showing the lapse of time in the operation of FIG. 1, and the data transfer operation of FIG. 1 will be described with reference to this figure.

When performing dual address DMA transfer,
In the DMA data transfer device 40, in order to access the data transfer source 61 and the data transfer destination 62, the address ADl
It is necessary to output la and ADllb. When the data DA10 is transferred from the data transfer source 61 to the data transfer destination 62, the control signal / address generation circuits 42-1 and 42-2 in the DMA data transfer device 40, as shown in FIG. The control signal CSl is parallel to the data transfer source 61 on the 51 side and the data transfer destination 62 on the bus 52 side.
la, CSllb and address ADlla, ADllb
Are output respectively.

Then, as shown in FIG. 6B, the data transfer source 61 is operated by the control signal CSlla, and the data DA10 in the data transfer source 61 designated by the address ADlla is read onto the bus 51. Further, the data transfer destination 62 starts its operation by the control signal CSllb. Then, the bus connection circuit 43 causes the buses 51 and 52
The data DA10 read from the data transfer source 61 to the bus 51 is transferred to the bus 52 via the bus control circuit 43, and the data DA10 on the bus 52 is
It is stored in the address ADllb of the data transfer destination 62.

As described above, in the first embodiment, the control signals CSlla, CSllb and the address are transmitted in parallel from the control signal / address generation circuits 42-1 and 42-2 to the data transfer source 61 and the data transfer destination 62. ADlla,
After outputting ADllb, the buses 51 and 52 are connected by the bus connection circuit 43. Therefore, the data transfer source 61
And the data transfer destination 62 simultaneously start operation, and the bus connection circuit 43 is transferred from the data transfer source 61 to the data transfer destination 62.
The data DA10 is transferred via. Therefore, the time for dual address DMA data transfer between the buses 51 and 52 can be shortened. FIG. 7 is a configuration block diagram of a dual address type DMA data transfer device showing a second embodiment of the present invention, and elements common to those in FIG. 1 are designated by common reference numerals.

The DMA data transfer device 70 is a device which is controlled by a CPU (not shown) and performs a dual address DMA transfer from a data transfer source 61 connected to one bus 51 to a data transfer destination 62. That is, this D
The MA data transfer device 70 includes a control unit 71 which is controlled by a CPU (not shown) and which controls the operation of the entire device, and a control unit 7
It is provided with two control signal / address generation circuits 72-1 and 72-2 and a bus division / connection circuit 73 which are controlled by 1.

One control signal / address generating circuit 72-
Reference numeral 1 is a circuit for outputting the control signal CSlla and the address ADlla to the data transfer source 61, and the other control signal / address generating circuit 72-2 is also the data transfer destination 62.
Is a circuit that outputs a control signal CSllb and an address ADllb to The bus dividing / connecting circuit 73 is provided between the data transfer source 61 side and the data transfer destination 62 side of the bus 51, and has a function of dividing the bus 51 and connecting it at a predetermined timing.

FIG. 8 is a diagram showing the lapse of time in the operation of FIG. 7, and the data transfer operation of FIG. 7 will be described with reference to this figure.

When the data DA10 is transferred from the data transfer source 61 to the data transfer destination 62, the bus division / connection circuit 73 transfers data to the data transfer source 61 side of the bus 51 as shown in FIG. 8 (1). It is divided into the front 62 side and separated. Then, the control signal / address generating circuits 72-1 and 7-2
2-2 sends a control signal CS11 to the data transfer source 61.
a and the address ADlla are output, the control signal CSllb and the address AD are output to the data transfer destination 62.
Output llb. As a result, the operations of the data transfer source 61 and the data transfer destination 62 start.

Then, the bus division / connection circuit 73 connects the data transfer source 61 side and the data transfer destination 62 side of the bus 51 to each other. Then, the data DA10 is read to the bus 51 from the address ADlla of the data transfer source 61, and the data DA10 on the bus 51 is transferred to the bus 51 on the data transfer destination 62 side via the bus division / connection circuit 73. . The data DA10 on the bus 51 is stored in the address ADllb of the data transfer destination 62.

As described above, according to the second embodiment, the control signal / address generating circuits 72-1 and 72-2 to the data transfer source 61 and the data transfer destination 62 control signals CSlla, CSllb and Address ADlla,
Since ADllb is output in parallel, and the data transfer source 61 side and the data transfer destination 62 side of the bus 51 are divided and connected by the bus dividing / connecting circuit 73, the data read from the data transfer source 61. The DA 10 can be directly transferred to the data transfer destination 62 via the bus dividing / connecting circuit 73 without temporarily storing it, thereby shortening the time for dual address DMA data transfer.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications.

(I) In FIG. 1, the DMA data transfer device 40 controls the data transfer between the two buses 51 and 52. However, the DMA data transfer device 40 controls the data transfer between three or more buses. You may make it transfer. At this time, the number of control signal / address generating circuits 42-1 and 42-2 may be increased according to the number of buses. (Ii) In FIG. 7, a data transfer source 61 and a data transfer destination 62 are connected to one bus 51. However, a plurality of data transfer sources 61 and data transfer destinations 62 are connected to this bus 51 to Data transfer between them may be controlled. In this case, the control signal / address generating circuit 72 is generated according to the numbers of the data transfer source 61 and the data transfer destination 62.
-1, 72-2 should be increased.

(Iii) In FIGS. 1 and 7, the control signal / address generating circuits 42-1, 42-2, 72-1, 72-
Although two 2 are provided for each, it is also possible to configure each of them by one circuit block. Other, D
Other functional blocks may be provided in the DMA data transfer devices 40 and 70 in order to improve the transfer accuracy of the MA.

[0039]

As described in detail above, according to the first aspect of the present invention, since the control signal / address generating circuit and the bus connecting circuit are provided, the control signal / address generating circuit transfers the data transfer source and the data transfer source. It is possible to output a control signal and an address to the destination in parallel to operate the data transfer source and the data transfer destination in parallel. Then, the data read from the data transfer destination can be directly transferred to the data transfer destination via the bus connection circuit without temporarily storing the data, whereby the DMA data transfer time can be greatly shortened.

According to the second aspect of the invention, since the control signal / address generating circuit and the bus dividing / connecting circuit are provided, the bus is divided by the bus dividing / connecting circuit and the data is sent from the control signal / address generating circuit. Control signals and addresses can be output in parallel to the transfer source and the data transfer destination. Then, after connecting the buses divided by the bus division / connection circuit, the data read from the data transfer source 61 can be directly transferred to the data transfer destination via the bus division / connection circuit without temporarily storing. Therefore, the time required for DMA data transfer can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a DMA data transfer device showing a first embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional DMA data transfer device.

FIG. 3 is a diagram showing a time course of the operation of FIG.

FIG. 4 is a configuration block diagram of another conventional DMA data transfer device.

5 is a diagram showing a time course of the operation of FIG.

FIG. 6 is a diagram showing a time course of the operation of FIG.

FIG. 7 is a configuration block diagram of a DMA data transfer device showing a second embodiment of the present invention.

FIG. 8 is a diagram showing a time course of the operation of FIG.

[Explanation of symbols]

40, 70 DMA data transfer device 41, 71 control unit 42-1, 42-2, 72-1, 72-2 control signal
Address generation circuit 43 Bus connection circuit 51, 52 Bus 61 Data transfer source 62 Data transfer destination 73 Bus division
Connection circuit

Claims (2)

[Claims] 1. A DMA for transferring data between a plurality of buses
In the data transfer device, a control signal / address generating circuit that outputs a control signal and an address in parallel to the data transfer source and the data transfer destination on each bus side during data transfer, and the data by connecting the plurality of buses. A DMA data transfer device comprising: a bus connection circuit that transfers data from a transfer source side bus to the data transfer destination side bus. 2. A DMA data transfer device for transferring data from a data transfer source connected to a bus to a data transfer destination, wherein a control signal and an address are output in parallel to the data transfer source and the data transfer destination, respectively, at the time of data transfer. A control signal / address generating circuit for dividing the bus between the data transfer source and the data transfer destination at the time of outputting the control signal and address, and connecting the divided buses at the time of the data transfer A DMA data transfer device comprising a dividing / connecting circuit.