JPH05282136A - Information processing equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an information processing device that has a plurality of memory address conversion functions and that accesses a memory according to a plurality of information processing functions [Configuration] The information processing device performs arithmetic processing CPU10
And a memory address conversion circuit A11 for converting the CPU address transmitted from the CPU 10 into the address of each memory.
And the memory address conversion circuit B12 and 2 depending on the processing.
Memory address conversion circuit switching circuit 13 for switching one memory address conversion circuit, and various memories ROM1, ROM
2, a RAM 1, a RAM 2, a ROM 3, a ROM 4, a display RAM, and a logical OR circuit 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a conventional information processing apparatus having a memory address conversion circuit. The information processing device is C
PU (central processing unit) 30, memory address conversion circuit 3
1, and ROM1, ROM2, ROM3, ROM
4, a RAM 1 and a RAM 2 are provided, and normally, a plurality of application software processes can be executed.

For example, a processing program having the processing function A and a processing program having the processing function B are stored in the ROM 1 and the ROM 3 in the same information processing apparatus, respectively, and when processing these, the CPU 30 Access each memory via the common memory address conversion circuit 31.

[0004]

However, a processing program having the processing function A and a processing program having the processing function B are developed in different information processing apparatuses A and B, respectively, and the hardware environment of the information processing apparatus is If they are different, the memory address conversion method is also often different. That is, since each information processing device has a unique memory address conversion circuit corresponding to its function, the processing program developed in each information processing device must be subjected to unique memory address conversion.

On the other hand, in the system having a plurality of processing functions developed by the prior art, since there is only a single and common memory address conversion circuit, the existing software is modified so as to be compatible with the memory address conversion circuit. , Need to change.

Therefore, when developing an information processing apparatus in which a plurality of software can be used, there is a problem that the work required for the development accompanying the modification and change of each software increases.

Therefore, the present invention provides an information processing apparatus having a plurality of memory address conversion functions and accessing a memory according to the plurality of information processing functions.

[0008]

According to the present invention, a plurality of memories, a plurality of means for accessing a part of the plurality of memories, and a memory according to a program to be processed. There is provided an information processing apparatus including means for selecting any one of a plurality of means for accessing the.

[0009]

When the processing program is processed, one access means is selected from a plurality of means for accessing a part of the memories. In particular,
The access means converts an address signal for accessing a memory into a memory select signal for the corresponding memory.

Since a plurality of access means are provided corresponding to a plurality of processing programs in this manner, memory access can be easily performed by selecting the corresponding access means.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic diagram showing an embodiment of an information processing apparatus according to the present invention. 2 is a flow chart showing the information processing function of one embodiment of the information processing apparatus according to the present invention, and FIG. 3 is a memory map showing the correspondence between the CPU addresses of one address memory conversion circuit and various memory spaces.

As shown in FIG. 1, the information processing apparatus includes a CPU 10 for performing arithmetic processing, a memory address conversion circuit A11 for converting an address signal transmitted from the CPU 10, that is, a CPU address into a memory select signal for each memory, and a memory. Address conversion circuit B12, memory address conversion circuit switching circuit 13 that switches between two memory address conversion circuits according to processing, various memories, ROM1, ROM
2, a RAM 1, a RAM 2, a ROM 3, a ROM 4, a display RAM, and a logical OR circuit 20.

A processing program having a specific processing function can be stored in each ROM. In addition, each RAM stores data and the like to be processed by each processing program.

The memory address conversion circuit A11 and the memory address conversion circuit B12 have different circuit configurations, and preferably a circuit configuration including a memory address conversion circuit of an existing information processing device (word processor, personal computer, etc.). It has become. Further, as shown in FIG. 1, the memory referred to through these conversion circuits is referred to by a different unique memory and a different memory space between the memory address conversion circuit A11 and the memory address conversion circuit B12. There is a common memory. In the embodiment shown in FIG. 1, R
The OM1 and the ROM2 are referenced only through the memory address conversion circuit A11, and the ROM3, the ROM4 and the display R are used.
AM is referred to only through the memory address conversion circuit A12, and RAM1 and RAM2 are common memories referred to in different memory spaces. The memory address conversion circuit A11 and the memory address conversion circuit B12 respectively correspond to means for accessing a part of the plurality of memories, and in the present embodiment, two means for accessing. Is provided. The means for selecting any one of the plurality of means for accessing the memory according to the program to be processed corresponds to the memory address conversion circuit switching circuit 13.

As the memory select signal for the memory commonly used among various memories, the output signal of the logical OR circuit 20 to which the memory select signals from the address conversion circuits A and B are input is used.

The memory address conversion circuit switching circuit 13 is
By receiving an instruction from the software via the CPU 10, only the designated memory address conversion circuit is enabled and the other memory address conversion circuits are disabled.
The memory address conversion circuit that has been validated is
The U address is converted into a memory select signal according to the memory map. The invalid memory address conversion circuit
No memory select signal is generated regardless of the CPU address (each memory select signal becomes inactive).

That is, the memory address conversion circuit switching circuit 1
Reference numeral 3 is an instruction from software, which selects one memory address conversion circuit designated from the memory address conversion circuits A and B included in the system. Therefore, the memory address conversion circuit can be freely selected according to the processing program to be executed.

Although the present embodiment is provided with two memory address conversion circuits, the number of memory address conversion circuits is not limited to this.
Three or more memory address conversion circuits may be provided depending on the type of software to be processed.

Memory address conversion circuit A of information processing apparatus
The memory map used for the address conversion of 11 is as shown in FIG. 3, for example.

ROM 1 from address 0 to address (a-1) of the CPU address, R from address a to address (b-1)
RAM1, c from OM2, address b to address (c-1)
The RAM 2 is assigned from the address to the address (d-1). In this case, when the CPU outputs addresses from address 0 to address (a-1), the memory address conversion circuit A causes the address space of the ROM 1 (address 0 to address (a-1)) according to the CPU address. Outputs a corresponding memory select signal to the ROM 1. Other ROM2, R
Similarly, for AM1 and RAM2, corresponding memory select signals are output from each memory space according to the CPU address.

Similarly, the memory address conversion circuit B12 also has CPU addresses and various memories ROM3, ROM.
4, RAM1, RAM2, and a memory map in which the address spaces of the display RAM are associated with each other.

Next, the flow of the program for controlling the operation of the memory address conversion circuit switching circuit will be described with reference to FIG.

First, when a processing function is selected in the information processing apparatus to execute various kinds of processing (step S10), it is determined whether the processing function is A (step S1).
1). If the processing function A is selected, a command for switching (a command for enabling the memory address conversion circuit A) is issued to operate the memory address conversion circuit switching circuit 13 to set the memory address conversion in the memory address conversion circuit A. (Step S12). In this case, if the memory address conversion circuit A is already set, this is maintained and
If the memory address conversion time B is set, the instruction to switch to the memory address conversion circuit A may be executed.

When the memory address conversion circuit A is set, the processing is shifted to the program of the processing function A and the operation control processing of the memory address conversion circuit switching circuit 13 is finished (step S13).

In step S11, if a process other than the processing function A is selected, that is, if the processing function B is selected, an instruction to switch (memory address conversion circuit B
Is issued) to activate the memory address conversion circuit switching circuit 13 to set the memory address conversion in the memory address conversion circuit B (step S14). In this case, if the memory address conversion circuit B has already been set, this may be maintained, and if the memory address conversion time A has been set, an instruction to switch to the memory address conversion circuit B may be executed. ..

Therefore, since the information processing apparatus according to the above-described embodiment includes the plurality of memory address conversion circuits and the memory address conversion circuit switching circuit, the information on which each software was developed without changing the existing software. The software can be used efficiently as well as the processing device. As a result, the work of developing software that integrates a plurality of information processing functions can be reduced, and development efficiency can be improved.

[0028]

As described in detail above, the information processing apparatus according to the present invention comprises a plurality of memories and a plurality of means for accessing a part of the memories.
Since a means for selecting any one of a plurality of means for accessing a plurality of memories according to a program to be processed is provided, without modifying the existing individual software that has been conventionally developed, Can be used. Therefore, when developing software that integrates a plurality of information processing functions, the efficiency of software development can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram schematically showing an embodiment of an information processing apparatus according to the present invention.

FIG. 2 is a flowchart showing operation control of a memory address conversion circuit switching circuit of an embodiment of the information processing apparatus according to the present invention.

FIG. 3 is a memory map showing a correspondence between a CPU address of one address memory conversion circuit and each memory space in the embodiment of the information processing apparatus according to the present invention.

FIG. 4 is a configuration diagram schematically showing a conventional information processing device.

[Explanation of symbols]

 10 CPU 11, 12 Memory Address Conversion Circuit 13 Memory Address Conversion Circuit Switching Circuit 20 Logical OR Circuit

Claims (1)

[Claims] 1. A plurality of memories, and a plurality of means for respectively accessing a part of the plurality of memories,
An information processing apparatus comprising: a means for selecting any one of the plurality of means for accessing the memory according to a program to be processed.