JPH05282145A - Branch instruction processing system - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to use software between computers with different branch instruction delay slots. [Arrangement] The same instruction sequence is overlapped at the branch source delay slot of the branch instruction and the branch destination, and the branch destination address defined by the instruction code is changed according to the number of delay slots peculiar to the computer. As a result, the same execution result is obtained regardless of the number of delay slots.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch instruction processing system for a computer.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a conventional branch instruction processing system. In the figure, 1 is a main memory, 2 is a branch instruction, 3 and 4 are instructions subsequent to a branch instruction 2, and 9 is a branch instruction. Instruction 2 is a branch destination instruction of instruction 2, and 10 is an instruction following instruction 5. FIG. 7 is a diagram showing a pipeline configuration in a conventional branch instruction processing system, in which 12 is an instruction fetch device, 1
3 is a decoding device, 14 is an address calculation device, 15 is a pipeline processing stage following the address calculation device 14, 16 is a pipeline processing stage following 15
Reference numeral 17 is a signal line between the address calculation device 14 and the instruction fetch device 12, and 40 is the entire computer. FIG. 8 is a diagram showing an operation in a conventional branch instruction processing system, which is 19 to 2
Reference numeral 7 indicates the clock cycle of the computer.

Next, the operation will be described. In this example, it is assumed that the number of delay slots is 2, the instructions 3 and 4 following the branch instruction 2 are included in the delay slot, and the branch instruction 2 is continuously executed.

The branch instruction 2 is processed by the instruction fetch unit 12 in the clock cycle 19. In clock cycle 20, branch instruction 2 is processed by decoding device 13, and at the same time, instruction 3 following the branch instruction is fetched from main memory device 1 and processed by instruction fetch device 12. In the clock cycle 21, the branch instruction 2 calculates the branch destination address uniquely determined from the instruction code by the address calculation device 14 and sends it to the instruction fetch device 12 through the calculated address signal line 17. Further, in the clock cycle 21, the instruction 3 is processed by the decoding device 13, and the instruction 4 is processed by the main memory device 1.
And processed by the instruction fetch unit 12. In the clock cycle 22, the instruction fetch unit 12 fetches the branch destination instruction 10 of the branch instruction 2 from the main memory 1. In the clock cycle 22, the branch instruction 2 is processed by the processing stage 15, the instruction 3 is processed by the address calculator 14, and the instruction 4 is processed by the decoder 13 at the same time. In clock cycle 23, branch instruction 2 is processing stage 16, instruction 3 is processing stage 15, instruction 4 is address calculating device 14, instruction 10 is decoding device 13,
The instruction 11 is processed by the instruction fetch unit 12.

As described above, the instruction 3, the instruction 4, the instruction 9, and the instruction 10 are continuously executed following the branch instruction 2.

[0006]

Since the conventional branch instruction processing system is configured as described above, the instruction following the branch instruction and processed before the instruction at the branch destination (instruction 3 and instruction 3). The number of instructions 4) (the number of delay slots, 2 in this example) is fixed. On the other hand, the optimum number of delay slots is not constant depending on the application of the computer, the element technology used by the computer, or the execution conditions at the time of execution. Therefore, there is a problem that common software cannot be used among computers having different numbers of delay slots.

The present invention has been made to solve the above problems, and an object thereof is to make it possible to use common software among computers having different delay slots.

[0008]

According to a branch instruction processing method of the present invention, the same instruction sequence is redundantly arranged at a branch source delay slot and a branch destination, and instructions are provided according to the number of delay slots peculiar to a computer. By changing the branch destination address defined by the code, the same execution result can be obtained regardless of the number of delay slots.

Further, the same execution result is obtained even though the number of delay slots of the computer is dynamically changed according to the condition at the time of execution.

[0010]

The branch destination address generating device according to the present invention is
By adding or subtracting the increment corresponding to the delay slot number of the computer to the branch destination address specified by the branch instruction, it is possible to maintain software compatibility with computers having different delay slot numbers. ..

[0011]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an example of a branch instruction processing method according to the present invention. In FIG. 1, 1 is a main memory, 2 is a branch instruction, and 3, 4, 5, 6 are executed subsequent to a branch instruction 2. Command, 7 is the same command as command 3, 8 is the same command as command 4, 9 is the same command as command 5, 10 is the same command as command 6, and 11 is the entire command sequence 2-10. .. FIG. 2 is a diagram showing a pipeline configuration of a computer that executes a branch instruction having two delay slots according to the present invention. 12 is an instruction fetch device, 13 is a decoding device, 14 is an address calculation device, and 15 is an address calculation device 14. Is a pipeline processing stage subsequent to 14; 16 is a pipeline processing stage subsequent to 14; 17 is a signal line between the address calculation device 14 and the instruction fetch device 12; and 18 is the entire computer constituted by 12 to 17. FIG. 3 is a diagram showing an example of the operation of the branch instruction processing method in the pipeline configuration of FIG. 2 according to the present invention, and 19 to 27 respectively show clock cycles of the computer. FIG. 4 is a diagram showing a pipeline configuration of a computer that executes a branch instruction having a delay slot number of 0 according to the present invention. In the figure, 28 denotes the entire computer configured by 12 to 17. FIG. 5 is a diagram showing an example of another operation of branch instruction processing in the pipeline configuration of FIG. 4 in the present invention, and 29 to 39 show clock cycles of a computer, respectively.

Next, the operation will be described. It is assumed that the branch instruction 2 is preset to point to the instruction 7 as the branch destination address.

A case of an operation example of the computer 18 of FIG. 2 will be described. The branch instruction 2 is processed by the instruction fetch unit 12 in the clock cycle 19. In the clock cycle 20, the branch instruction 2 is processed by the decoding device 13, and at the same time, the instruction 4 following the branch instruction is processed by the main memory device 1.
And processed by the instruction fetch unit 12. In the clock cycle 21, the branch instruction 2 is processed by the address calculation device 14, and the address of the instruction 7 set as the branch destination address is added with the address of two instructions which is an increment corresponding to the number of instructions in the delay slot. The resulting address is sent to the instruction fetch unit 12 via the signal line 15. Further, in the clock cycle 21, the instruction 3 is transmitted to the decoding device 13, and the instruction 4 is transmitted.
Are fetched from the main memory 1 and the instruction fetch unit 12
Will be processed. In the clock cycle 22, the instruction fetch unit 9 fetches the instruction 9 corresponding to the address sent from the address calculation unit 14 from the main memory unit 1.
In clock cycle 22, at the same time, branch instruction 2
Is the processing stage 15, instruction 3 is the address calculator 14,
The instruction 4 is processed by the decoding device 13. In clock cycle 23, branch instruction 2 is in processing stage 1
6, the instruction 3 is processed by the processing stage 15, the instruction 4 is processed by the address calculation unit 14, the instruction 9 is processed by the decoding unit 13, and the instruction 10 is processed by the instruction fetch unit 12.

As described above, in the computer 18, following the branch instruction 2, instruction 3, instruction 4, instruction 9, instruction 10
Are sequentially executed.

Next, the case of the operation example of the computer 28 of FIG. 4 will be described. The branch instruction 2 is processed by the instruction fetch unit 12 in the clock cycle 29. In the clock cycle 30, the branch instruction 2 is processed by the decoding device 13, detects that the relevant instruction is a branch instruction, and stops decoding the following instructions. Clock cycle 31
, The branch instruction 2 is processed by the address calculator 14, and the address of the instruction 7 set as the branch destination address is sent to the instruction fetch unit 12 through the signal line 15 as it is. In the clock cycle 32, the instruction fetch unit 12 fetches the instruction 7 corresponding to the instruction sent from the address calculation unit 14 from the main memory 1. In clock cycle 32, branch instruction 2 is simultaneously processed in processing stage 15. Clock cycle 3
3, branch instruction 2 is processing stage 16, instruction 7
Is processed by the decoding device 13, and the instruction 8 is processed by the instruction fetch device 12.

As described above, in the computer 28, following the branch instruction 2, instruction 7, instruction 8, instruction 9, and instruction 10
Are sequentially executed.

However, since the same instructions are arranged in the instructions 3 and 7, and the instructions 4 and 8, the execution result of the instruction sequence 11 in the computer 18 and the execution result in the computer 28 are the same. That is, software compatibility can be maintained between the computer 18 and the computer 28, although the number of delay slots is different.

Example 2. In the above embodiment, the computer 18 and the computer 28 may be the same computer, or the number of delay slots may change depending on the execution condition.

Example 3. Further, although the number of delay slots is set to 0 and 2 in the above embodiment, the maximum value of the number of delay slots is appropriately set, and the length of the overlapping instruction sequence is set to the maximum number. The same execution result can be obtained among computers having an arbitrary number of delay slots.

Example 4. Further, in the above embodiment, the number of stages of the pipeline is set to 5, and the instruction fetch device, the instruction decode device, and the address calculation device are included. However, the above embodiment is applied to an arbitrary pipeline configuration having an arbitrary number of stages. Has the same effect as.

Embodiment 5. Further, in the above-described embodiment, the increment according to the number of delay slots is added, but the same effect as in the above-described embodiment can be obtained by reducing the address.

Embodiment 6. Further, in the above-described embodiment, the address according to the number of delay slots is added in the address calculation device, but this address addition or subtraction operation is performed by any component in the computer, such as the instruction fetch device, the decoding device, The same effect as that of the above-described embodiment can be obtained.

Example 7. In the above embodiment, the branch instruction unconditionally branches. However, even if the branch instruction is a conditional branch instruction, the same effect as that in the above embodiment can be obtained by adding the processing when the branch is unsuccessful. You can

Example 8. Further, in the above embodiment, each instruction is processed in one clock cycle in each pipeline stage, but the processing clock cycle in each pipeline stage may take any value, and the same effect as in the above embodiment Can be played.

Example 9. Further, in the above-mentioned embodiment, the instruction is fetched from the main memory every clock cycle, but a plurality of instructions may be fetched from the main memory at the same time by providing a buffer in the instruction fetch unit. The main storage device may include a cache memory or a buffer, and the same effect as that of the above-described embodiment can be obtained.

Example 10. Also, in the above embodiment,
Although it is assumed that the instruction length is fixed, it is possible to obtain the same effect as the above embodiment by adding or subtracting the increment of the branch destination address according to the instruction length in the delay slot in the address calculation device.

Embodiment 11. Also, in the above embodiment,
Although the branch is performed in the forward direction, that is, in the address increasing direction, it may be performed in the backward direction, that is, in the address decreasing direction, and the same effect as that of the above embodiment can be obtained.

[0028]

As described above, according to the present invention, the same instruction string is overlapped at the branch source delay slot and the branch destination, and the instruction code is defined according to the number of delay slots peculiar to the computer. To change the branch destination address
This has the effect of making it possible to use common software among computers having different numbers of delay slots.

[Brief description of drawings]

FIG. 1 is a diagram showing a branch instruction processing system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a computer having a branch instruction processing system according to an embodiment of the present invention and having two delay slots.

FIG. 3 is a diagram showing an operation of a computer having a branch instruction processing system according to an embodiment of the present invention and having two delay slots.

FIG. 4 is a configuration diagram of a computer having a branch instruction processing system according to an embodiment of the present invention and having zero delay slots.

FIG. 5 is a diagram showing an operation of a computer having a branch instruction processing system according to an embodiment of the present invention and having 0 delay slots.

FIG. 6 is a diagram showing an example of a conventional branch instruction processing method.

FIG. 7 is a configuration diagram of an example of a computer having a conventional branch instruction processing system.

FIG. 8 is a diagram showing an operation of an example of a computer having a conventional branch instruction processing system.

[Explanation of symbols]

1 main memory 2 branch instruction 3 instruction following branch instruction 4 instruction following instruction 3 5 instruction following instruction 4 6 instruction following instruction 5 7 instruction same as instruction 8 instruction same as instruction 4 9 Instruction 5 same as instruction 10 instruction 6 same as instruction 11 instruction sequence 2 to 10 12 instruction fetch device 13 decoding device 14 address calculation device 15 pipeline processing stage following address calculation device 14 pipeline processing stage 16 subsequent to pipeline processing stage 15 Pipeline processing stage 17 Signal line 18 Computer 19 Clock cycle 20 Clock cycle 21 Clock cycle 22 Clock cycle 23 Clock cycle 24 Clock cycle 25 Clock cycle 26 Clock cycle 27 Clock cycle 28 Computer 29 Clock cycle 30 Rock Cycle 31 clock cycles 32 clock cycles 33 clock cycles 34 clock cycles 35 clock cycles 36 clock cycles 37 clock cycles

Claims (2)

[Claims] 1. A means for overlappingly placing the same instruction sequence at a branch source delay slot and a branch destination of a branch instruction, and a means for changing a branch destination address defined by an instruction code according to the number of delay slots of the branch instruction. A branch instruction processing method characterized by: 2. The branch instruction processing system according to claim 1, wherein the number of delay slots is dynamically changed at the time of execution.