JPH05283696A - Thin film transistor - Google Patents

Abstract

PURPOSE:To reduce a resistance of source and drain regions and improve the ratio of ON and OFF, by forming the source and drain regions of a thin film transistor into a double layer structure of a silicide and a polycrystalline silicon. CONSTITUTION:After a silicon oxide film 102 is formed on a semiconductor substrate 101, a polycrystalline silicon film is formed. After an ion implantation of phosphorus or boron, a patterning is performed and a gate electrode 103 is formed. Next, while a silicon oxide film is deposited so as to cover the gate electrode 103 and a gate electrode film 104 is formed, a polycrystalline silicon film 105 in which phosphorus is introduced is formed, and p-type regions 106 and 107 are formed by the ion implantation of boron. Then, while a silicon nitride film 108 is patterned, a metal film 109 is grown and the non-reacted metal film is removed by a wet etching. The p-type regions 106 and 107 used as a source region 111 and a drain region 112 are formed into a double layer structure 110 of a silicide and a polycrystalline silicon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly to a structure of a source / drain region of the thin film transistor.

[0002]

2. Description of the Related Art A conventional thin film transistor (Thin F)
ilm Transistor: hereinafter referred to as TFT)
Will be described with reference to FIG.

In FIG. 4, 201 is a silicon semiconductor substrate, and 202 is a film thickness 100 nm deposited by a CVD method.
It is a silicon oxide film of a certain degree. Reference numeral 203 denotes a TFT gate electrode made of polycrystalline silicon having a film thickness of 100 nm to 150 nm which is patterned by using a known means. Reference numeral 204 is a gate insulating film made of a silicon oxide film with a film thickness of about 20 nm deposited by the CVD method so as to cover the gate electrode 203.

For the channel portion of the TFT, a polycrystalline silicon film 205 is formed to a thickness of about 50 nm by the CVD method, and phosphorus is introduced into the entire area by the ion implantation method, for example, in the case of a p-type channel transistor. Next, using a photoresist, boron is introduced into a desired region of the polycrystalline silicon film 205 by an ion implantation method to form a source region 206 and a drain region 207.

When this TFT is used as, for example, a load element of a static RAM, one flip-flop type static R is provided on the main surface of one conductivity type silicon substrate.
N-type MO for two access transistors forming AM
SFET and n-type MOS for two driver transistors
A main surface of a semiconductor substrate having an FET is laminated with an insulating film interposed.

In this case, the polycrystalline silicon film forming the source region of the TFT is used as the power wiring of the static RAM. Further, by forming an interlayer insulating film, a wiring metal film and the like on the upper layer thereof, a static RAM cell using a TFT as a load element is completed.

[0007]

The conventional TFT is described in, for example, "1990 Autumn Proceedings of the Applied Physics Proceedings. 28a-S".
ZM-11 ”, it is known that when the concentration of the impurity introduced into the drain region is reduced, the off current is reduced.
When used as a load element of, it is possible to reduce the data holding current.

However, the resistance of the source / drain region is increased due to the dilution of the concentration of the introduced impurities, and
The on-current of is also reduced. Especially, the TFT is static R
When used as a load element of AM, the polycrystalline silicon forming the source region of the TFT is used as the wiring from the power source, so that the operating current is reduced and the static RAM
It was a problem in operation.

An object of the present invention is to provide a thin film transistor that solves the above problems.

[0010]

In order to achieve the above object, a thin film transistor according to the present invention comprises a gate electrode provided on one main surface of a semiconductor substrate and a gate insulation provided so as to cover the surface of the gate electrode. A film, a polycrystalline silicon film of the first conductivity type provided on the gate insulating film, and a second conductivity type opposite to the first conductivity type provided in the polycrystalline silicon film Regions, and the regions are source / drain regions having a two-layer structure of silicide and polycrystalline silicon.

The concentration of impurities introduced into the region is set to 1 × 10 ¹⁹ atoms / cm ³ or less.

[0012]

The TFT of the present invention is provided with the source region and the drain region composed of the two-layer structure of polycrystalline silicon and silicide, and the concentration of the impurities introduced into the source and drain regions is 1 × 10 ¹⁹ atoms. / Cm ³ or less.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1, 2 and 3 are cross-sectional views showing an embodiment of the present invention in the order of steps. In this example, a case of a p-type channel transistor will be described.

In FIG. 1, a CV is formed on a semiconductor substrate 101.
The silicon oxide film 102 having a thickness of about 100 nm is formed by the D method.
And then depositing a polycrystalline silicon film from 100 nm to 15 nm.
The gate electrode 103 is formed with a film thickness of 0 nm, and by ion implantation, phosphorus is introduced for n-type and boron is introduced for p-type, and patterning is performed by a known means.
To form.

Thereafter, a film thickness of 20 n is formed by the CVD method.
A silicon oxide film of about m is deposited so as to cover the gate electrode 103 to form a gate insulating film 104.

Further, for example, in the case of a p-type channel transistor, the polycrystalline silicon 105 containing phosphorus is added to 5
The polycrystalline silicon film 1 is formed with a film thickness of about 0 nm, and boron ions are implanted using the photoresist as a mask.
The p-type regions 106 and 107 are formed in 05.

Next, as shown in FIG. 2, a silicon nitride film 1 is formed.
08 is patterned, and thereafter, a refractory metal such as titanium is sputtered on the entire surface.
A metal film 109 of about 0 nm is grown. Where 60
When the heat treatment is performed at about 0 ° C., the refractory metal is introduced into the silicon in the p-type regions 106 and 107 where the metal film and the polycrystalline silicon are in contact with each other.

Thereafter, as shown in FIG. 3, when the unreacted metal film is removed by the wet etching method, the p-type regions 106 and 107 become a two-layer structure (salicide) 110 of silicide and polycrystalline silicon, and are nitrided. The metal film on the silicon film 108 is removed as it is.

Finally, when the silicon nitride film 108 is removed by the wet etching method, the shape shown in FIG. 3 having a source region 111 and a drain region 112 having a two-layer structure (salicide) of silicide and polycrystalline silicon is obtained. ..

When this TFT is used as a load element of a static RAM, two n-type MOS transistors for access transistors forming one flip-flop static RAM are formed on the main surface of one conductivity type silicon substrate.
T and n-type MOSFET for two driver transistors
And a main surface of a semiconductor substrate having is laminated with an insulating film interposed. Further, if an interlayer insulating film, a metal film for wiring, etc. are formed on the upper layer, static R using a TFT as a load element is formed.
The AM cell is completed.

Since the source / drain regions of the TFT of this embodiment have a salicide structure, the concentration of boron introduced into polycrystalline silicon is 1 × 10 ¹⁹ atoms /
Even if it is as thin as cm ³ or less, its electrical conductivity can be equal or higher.

Therefore, the salicide structure makes it possible to reduce the off-current by diluting the introduced boron without decreasing the on-current.
An improvement in the on / off ratio of FT can be expected.

In addition, the TFT of this embodiment has a static R
If it is used as a load element of AM, the data holding current can be reduced without reducing the current during operation, and an operational advantage of the static RAM can be expected.

When the present thin film transistor is used as an n-type channel transistor, the same method can be used.

[0025]

As described above, according to the present invention, the TFT
By making the source region and the drain region of the device have a two-layer structure of silicide and polycrystalline silicon, the resistance of the source / drain region is reduced, and the concentration of impurities introduced into the source / drain region is 1 × 10 ^19. atoms / cm
Since it is set to ³ or less, it is possible to increase or increase the OFF current without decreasing the ON current of the TFT, and it is possible to improve ON / OFF of the TFT.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing an embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing an embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a conventional example.

[Explanation of symbols]

Reference Signs List 101 semiconductor substrate 102 silicon oxide film 103 gate electrode 104 gate insulating film 105 polycrystalline silicon film 106 p-type region 107 p-type region 108 silicon nitride film 109 refractory metal film 110 two-layer structure (salicide) of silicide and polycrystalline silicon 111 Source region 112 Drain region

Claims (2)

[Claims] 1. A gate electrode provided on one main surface of a semiconductor substrate, a gate insulating film provided so as to cover the surface of the gate electrode, and a first conductivity type provided on the gate insulating film. A polycrystalline silicon film, and a region of a second conductivity type opposite to the first conductivity type, which is provided in the polycrystalline silicon film, and the region has two layers of silicide and polycrystalline silicon. A thin film transistor having a source / drain region having a structure. 2. The thin film transistor according to claim 1, wherein the concentration of impurities introduced into the region is 1 × 10 ¹⁹ at.
A thin film transistor, characterized in that it has a thickness of oms / cm ³ or less.