JPH0528537B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention was developed by the Consultative Committee for International Telegraph and Telephone (CCITT)
When transmitting and receiving signals between two digital signal systems that both have accurate clock frequencies within ±1 × 10 ^-11 frequency accuracy as specified in Recommendation G.811, the transmission rate of both systems is The present invention relates to a plesiochronous slip control circuit of a plesiochronous matching circuit used for the purpose of correcting a difference.

[Conventional technology]

In general, a plesiochronous matching circuit is a circuit between two digital signal systems in which the expected difference in clock frequency is extremely small, as described above, and where the cumulative difference in transmission bits of both systems is determined under a predetermined condition. This circuit tries to match the data transmission speed between the two systems by discarding or reading the digital signal corresponding to a certain period of time twice.

Figure 3 shows the concept of a plesiochronous matching circuit. The plesiochronous matching circuit can be compared to a memory circuit 1 having a virtual ring-shaped configuration as shown in FIG. 3. Input signals are written into this memory as write data, and read data is taken out as output signals. It will be done. As shown in FIG. 3, this ring-shaped memory 1 has a total of n addresses from address 0 to address (n-1), and the figure shows that the input signal is written to address w as write data, and the output signal indicates that the data is being read from address r as read data.
Further, the order of writing and reading both proceed in a clockwise direction.

When the data transmission speed of the input side system and the data transmission speed of the output side system match, the relative positions of the write address and read address are constant no matter where they are in this ring-shaped memory 1. In order to maintain the distance relationship, data reading is always performed at the address (wr) after the write address, but the data transmission speed of the input side system and the data transmission speed of the output side system are different. If there is a difference, the relative distance between the write address and the read address will change over time, and if the former is faster than the latter, the write address will catch up with the read address, and conversely, if the former is slower than the latter, the relative distance will change over time. The read address will catch up with the write address.
Considering this phenomenon based on the address on the read side, if the data transmission speed of the input side system is faster than that on the output side, the write address advances, and the read address advances in a relative clockwise direction. In the opposite case, the write address lags and approaches the read address relatively counterclockwise.

In this case, the distance between both addresses decreases over time, and if left unchecked, the write and read addresses will eventually overlap and eventually overtake each other, but this means that the write rate is relatively higher. In the former case, data for one round of the ring buffer will be read out, and in the latter case, where the read rate is relatively higher, data that has already been read once and corresponds to one round of the ring buffer will be discarded. Means to be read twice.

Since there is a difference in transmission speed, it is unavoidable that some form of data is discarded or read twice, but there must be no regularity in the range of data that is discarded or read twice. For example, there are many inconveniences in signal processing. The purpose of the plesiochronous matching circuit is to control the unit in which this data is discarded or read twice so that it has a break in accordance with a predetermined law. As this fixed unit, a unit having a fixed periodic character is usually selected, such as a sample unit, a frame unit, or a multi-frame unit in a PCM telephone line digital signal.

In FIG. 3, for example, the unit for discarding a read or reading twice is data at address j, which corresponds to one frame of data, and the threshold for writing and read address approach detection to cause a data slip is set to 2. Use the address difference.

For example, suppose that writing is faster than reading, and the write address approaches the read address clockwise. And the read address is
When the write address is at the last address (r-1) of a certain frame, the write address is at the next address (r-1).
-3) Suppose you approach the street address. Normally, the read address would proceed to address r, but in this case, the plesiochronous slip control moves the read address one frame ahead (r+
j) You will be able to proceed to the next address.

Conversely, assume that writing is slower than reading, and the write address approaches the read address counterclockwise. Then, the read address is the last address (r+j−
1) When the address is reached, the write address is still 2.
Assume that you are at address (r+j+1) before the address.
At this time, normally, the read address that advances to address (r+j) will return to address r, which is the starting address of the original frame, due to plesiochronous slip control.

In this way, when writing and reading addresses approach within a predetermined distance, a predetermined amount of data is discarded or read twice at a predetermined data break. A plesiochronous matching circuit attempts to match the data transmission speeds of two data signal systems that have slightly different transmission speeds by performing this on a regular basis.

The accuracy of the clock frequencies of the two systems that perform plesiochronous matching fluctuates within an allowable range, and the worst case scenario is that the moment a certain slip occurs, the relative relationship between the clock frequencies of the two systems changes completely in the opposite direction. Considering the conditions, in order to keep the minimum time interval between slip occurrences above a certain level, the difference between the write address and read address after a slip is 1 regardless of whether it is measured clockwise or counterclockwise. It must have at least the number of frames, and taking into account the write and read addresses, the capacity of the matching buffer memory is (number of addresses equivalent to 2 frames +
1) More than an address is required. If the threshold value for address difference detection is placed at a location farther away than 1, which corresponds to the adjacent address, for safety reasons, additional memory capacity is required, and when performing slip control, it is necessary to count address differences and It is difficult to perform a slip to an address one frame away from the current address. Therefore, the capacity of the matched buffer memory is usually chosen to exceed two frames and be an integral multiple of the frame capacity in units of slips, so that each address of the matched buffer accommodates a fixed bit of data for each frame. A method is used to facilitate slip control by using a fixed address allocation method such that there is always a break for each slip at a fixed address that is regulated on the matching buffer memory.

FIG. 4 shows a basic embodiment of a plesiochronous matching circuit. In the figure, it is assumed that a digital signal is transmitted from system A, which is a digital system on the transmitting side, to system B, which is a digital system on the receiving side. 10 is an input signal from system A, 15 is a clock extraction circuit for system A, 11 is a clock signal for system A, 1
6 is a frame timing detection circuit for the A system, 12 is a frame timing signal for the A system signal train, 13 is a write address counter, 14 is a write address signal, 20 is an output signal to the B system, 21 is a clock signal for the B system, 22 is a frame timing signal of the B series signal train, 23 is a read address counter,
24 is a read address signal, 30 is a matching buffer memory, 31 is a buffer control circuit, 32 is a memory control signal, 33 is a read discard control signal, 34 is 2
This is the degree reading control signal.

Next, the operation will be explained.

The A-system clock extraction circuit 15 extracts the A-system clock signal 11 from the input signal 10 from the A-system,
This is supplied to the A-system frame timing detection circuit 16 and write address counter 13. A
The system frame timing detection circuit 16 detects frame information from the input signal 10 from the A system based on the A system clock signal 11, and generates a frame timing signal 12 of the A system signal sequence. is the A-system clock signal 11
Based on this, counting is performed in synchronization with the frame timing signal 12 of the A-system signal train, and a write address signal 14 for writing the input signal 10 from the A-system to the matching buffer memory 30 is generated.

On the other hand, the read/output address counter 23 performs counting based on the B-system clock signal 21 in synchronization with the frame timing signal 22 of the B-system signal train, and also receives a read-discard control signal given from a buffer control circuit 31, which will be described later. 33 and twice-read control signal 34 to generate a read address signal 24 for reading out the output signal 20 to the B system from the matching buffer memory 30.

The matching buffer memory 30 is connected to the buffer control circuit 3
Under the control of a memory control signal 32 applied from 1, data is written to a memory address corresponding to a write address signal, and data is read from a memory address corresponding to a read address signal. The buffer control circuit 31 receives the write address signal 14 applied from the write address counter 13 and the read address counter 23.
It compares the read address signal 24 applied from the matching buffer memory 30 and generates a memory control signal 32 that controls writing of data to and reading of data from the memory 30, and detects the difference between the write address and the read address. However, when the difference between the addresses becomes smaller than a preset value, a read discard control signal 33 that instructs to read and discard data according to the relative relationship between both addresses, or a read twice that instructs to read data twice. Control signals 34 are generated and applied to the read address counter 23.

FIG. 5 shows an example of the configuration of the buffer control circuit 31. In the figure, a portion 310 surrounded by a broken line is a plesiochronous slip control circuit, 14 is a write address signal, 24 is a read address signal,
32 is a memory control signal, 33 is a read discard control signal, 34 is a read twice control signal, 311 is a first digital comparison circuit, 312 is a read check address setting circuit, 313 is an address check timing signal, 314 is a latch circuit, 315 is a write address check signal, 316 is a second digital comparison circuit, 317 is a third digital comparison circuit, 318 is a read discard threshold setting circuit, 319 is a twice read threshold setting circuit, 321 is a write address change detection circuit, and 322 is a write address change detection circuit. A read address change detection circuit, 323 a write and read control circuit, 324 a write address change detection signal, 3
25 is a read address change detection signal.

Next, the operation of this buffer control circuit 31 will be explained in more detail.

The write address signal 14 and the read address signal 24 are supplied to the write address change detection circuit 321 and the read address change detection circuit 3, respectively.
22, and the respective circuits 321 and 322 generate pulses of a write address change detection signal 324 and a read address change detection signal 325, respectively, at the rising timing when the respective values change. Write address change detection signal 3
24 and read address change detection signal 325
are both applied to the write and read control circuit 323. Write and read control circuit 323
detects write cycles and read cycles from the write address change detection signal 324 and the read address change detection signal 325, respectively, and writes to and reads from the matching buffer memory 30 at appropriate timing within each cycle. A memory control signal 32 is generated to instruct this.

Here, the plesiochronous slip control circuit 3
10, the proximity of both addresses is detected in advance from the input write address signal 14 and read address signal 24, and the read address is jumped so that the difference between the write and read addresses does not become smaller than a predetermined value. However, since the allowable difference in the clock frequencies of the two systems is extremely small, less than ± ² The decrease in address difference that occurs during a read or write time equivalent to minutes is a very small value compared to the write or read operation time allocated to one address in terms of time, that is, the write cycle time or read cycle time. be. In other words, the time required for the difference between the write address and the read address to decrease by one address is sufficiently longer than the time required to write or read from the matching buffer memory 30 for one round. Since the address difference changes slowly in this way, there is no need to constantly monitor the difference between the write address and the read address. This can be handled by a sampling control method that monitors and controls the difference, and a sampling period that corresponds to one round of the matching buffer memory is sufficient.

In the read check address setting circuit 312, an appropriate address value of the matching buffer memory 30 is set as a read check address value. Each time the value of the read address signal 24 input to the first digital comparison circuit 311 matches the read check address value, the first digital comparison circuit 311 generates an address check timing signal 313. The write address signal 14 input to the latch circuit 314 is latched by the latch circuit 314 at the rise timing of the address check timing signal 313 pulse, and is outputted from the latch circuit 314 as a write address check signal 315. The write address check signal 315 is applied as an input to a second digital comparison circuit 316 and a third digital comparison circuit 317. The read discard threshold setting circuit 318 is set with an address value that is slightly back in time from the read check address value described above, while the read twice threshold setting circuit 319 is set with an address value that is slightly back in time from the read check address value. An address value that is slightly ahead is set as the twice-read threshold. Then, the value of the write address check signal 315, which is the write address signal value sampled at the timing when the read address signal 24 matches the read check address value, is between the twice read threshold and the read discard threshold, counting in the address advancing direction. In some cases, there is no need to perform a plesiochronous slip, but
When the clock frequency of system A, which is the write side, is higher than the clock frequency of system B, which is the read side, the value of the write address check signal 315 approaches the read check address value from the read discard threshold side, so both addresses The second digital comparison circuit 316 generates the read discard control signal 33 before the write address check signal value matches the read discard threshold. This signal is applied to the read address counter 23 in FIG. 4, and after the read address value reaches the last address of the frame, instead of proceeding to the next address which is the start address of the data of the next frame, Skip one frame and jump the address to the start address of the next frame. This implements control to prevent the write address from getting too close to the read address.

Conversely, if the clock frequency of system A is lower than the clock frequency of system B, the write address check signal value approaches the read check address value from the twice-read threshold side, and the write address check signal value approaches twice the read address value. When the read threshold is met, the third digital comparator circuit 317 generates the read twice control signal 34, which also
Applied to the read address counter 23 in the figure,
After the read address value reaches the last address of the frame, instead of proceeding to the next address which is the start address of the data belonging to the next frame, go back one frame and read the start address of the data belonging to the previous frame. Jump the address to. This implements control to prevent the read address from getting too close to the write address.

[Problem that the invention seeks to solve]

The conventional device is configured as described above, and the write address signal 14 is latched at the timing when the address check timing signal 313 is applied from the first digital comparison circuit 311 to the latch circuit 314. A that is
Since the system clock phase and the clock phase of the B system on the reading side change independently, the following problems may occur.

That is, the input signal is latched into the latch circuit 314 by the address check timing signal 313 when the read address signal 24 outputted from the read address counter 23 operated by the B-system clock signal matches the read check address value. When the write address counter 13, which is operating on the A-system clock signal on the writing side, is changing the write address signal 14, which is its output, when controlling Due to the temporal variation called skew that exists between the change timings of individual bits of the write address signal 14 composed of parallel outputs, the latch circuit 314 may cause the latch circuit 314 to The remaining bits may latch the value before the change, and the remaining bits may latch the value after the change. As a result, the write address check signal 315 may be misidentified and the read discard control signal 33 or the read twice control signal 34 may be generated even though there is no need to execute plesiochronous slip control. Conversely, even though discarding or reading twice is necessary, the discard control signal 33 and the read twice control signal 34 may not be generated, resulting in unnecessary data signal disturbance. There was a drawback.

This invention has been made to eliminate the above-mentioned drawbacks of the conventional ones, and provides a plesiochronous slip control circuit that does not recognize erroneous write addresses and does not perform unnecessary slip control. It is something.

[Means for solving problems]

The plesiochronous slip control circuit according to the present invention includes a sample aperture signal generating means for generating a sample aperture signal indicating a signal value uncertain time period when a write address signal value changes, and sampling means for sampling a write address signal value only in a time range in which obtained samples are allowed; detecting a difference between the sample value and a read address signal value at a predetermined timing; and detecting a difference between the sample value and a read address signal value at a predetermined timing; A slip control signal generating means for generating a slip control signal is provided.

[Effect]

In this invention, sampling of the write address signal value is prohibited during a time period when the signal value is uncertain when the write address signal value changes, and sampling is permitted only during the time period when the write address signal is determined. Slip control is performed according to the value.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a buffer control circuit having a plesiochronous slip control circuit according to an embodiment of the present invention. In the figure, the part surrounded by the dashed line is the buffer control circuit 31 shown in FIG.
Applies to. Further, a portion surrounded by a broken line corresponds to the plesiochronous slip control circuit 310.

In the figure, a write address signal 14, a read address signal 24, a memory control signal 32, a read discard control signal 33, a read twice control signal 34, a first digital comparison circuit 311, a read check address setting circuit 312, a latch circuit 314,
Write address check signal 315, second digital comparison circuit 316, third digital comparison circuit 317, read discard threshold setting circuit 318, read twice threshold setting circuit 319, write address change detection circuit 321, read address change detection circuit 322, The write and read control circuit 323, the write address change detection signal 324, and the read address change detection signal 325 each have the same functions as corresponding parts of the conventional circuit.

326 is the write address change detection signal 3
24 is a NOT circuit that inverts the polarity, 327 is a delay circuit, and the NOT circuit 326 and delay circuit 327 generate a sample aperture signal 328 indicating a signal uncertainty time period when the write address signal value changes. An aperture signal generating means is configured. 329 is an AND circuit,
330 is a latch control signal which is the output of the AND circuit 329, and is a latch control signal output from the first digital comparison circuit 3.
11. Read check address setting circuit 31
2, an AND circuit 329, and a latch circuit 314 constitute a sampling means.

Next, the operation will be explained.

The write address signal 14 and the read address signal 24 are input, and the write address change detection circuit 321 and the read address change detection circuit 32
2, the memory control signal 32 is generated from the read control circuit 323, and the read address signal 24 is input, and the same signal is read out in the first digital comparison circuit 311 and the digital signal set in the check address setting circuit 312 is read. The operation of comparing the values and generating the address check timing signal 313 when the two match is the same as in the conventional circuit.

In this embodiment, a signal obtained by inverting the polarity of the write address change detection signal 324 by a NOT circuit 326 is delayed by a delay circuit 327 for a time slightly shorter than the write cycle time to obtain a sampling aperture signal. FIGS. 2a to 2d show time charts from the write address signal 14 to obtaining the sample aperture signal 328. By adjusting the delay time of the delay circuit 327, the sample averter signal 328 is set so that its negative logic time period includes the uncertain time period (the shaded area in FIG. 2a) of the write address signal 14. (See Figure 2 a, d). In Figure 2 e-g and h-j,
Two examples are shown in which the address check timing signal 313 is generated from the read address signal 24 on the same time scale as the sample aperture signal 328 in the upper part of the figure. Note that n in the figure indicates a read check address setting value.

First, in the example shown in FIG. 2 e to g, the address check timing signal 313 is generated in a time period near the center of the write address cycle, that is, in a time period when the value of the write address signal 14 is determined. be. In this case, the logical product of the address check timing signal 313 and the sample aperture signal 328 shown in f and d of the same figure is determined by the AND circuit 32.
9, the latch control signal 330, which is the output signal of the AND circuit 329, has a positive logic pulse portion as shown in g of the figure, and the latch circuit 314 latches the write address signal 14 at the rising edge of the pulse. , and outputs the value as a write address check signal 315. Based on this address check signal 315, the second digital comparison circuit 316 or the third digital comparison circuit 3
The operation of appropriately generating the discard control signal 33 or the read twice control signal 34 in step 17 is the same as in the conventional circuit.

Furthermore, in the examples shown in FIG. 2h to j, the address check timing signal 313 is generated near the turn of the write address cycle, that is, in or near a time period in which the value of the write address signal 14 is uncertain. (See a and i in the same figure)
In the AND circuit 329, the address check timing signal 313 and the sample aperture signal 32
As a result of taking the logical product with In response to a significant latch control signal 330, the latched write address value is taken over as an address check signal 315 and output. As a result, the read discard control signal 33 or the read twice control signal 34 is output from the second digital comparison circuit 316 or the third digital comparison circuit 317.
will never occur.

Here, according to this embodiment, as shown in FIG. 2h to j, the latch circuit 314 does not latch the write address value even though the address check timing signal 313 is generated, so that the preposition There may be cases where chronous slip control is not implemented, but as mentioned earlier,
The difference in clock frequency between the B systems is very small, and therefore the phase difference between the A system's write cycle and the B system's read cycle also shifts little by little as time passes, and the address check timing several cycles later. As in the examples shown in FIGS. 2e to 2g, the signal 313 is generated during the positive logic time period of the sample aperture signal, and plesiochronous slip control is implemented.

In this way, in the device of this embodiment, the signal value uncertainty time period when the write address signal value changes is
Since sampling by the latch circuit 314 is prohibited, slip control is not performed erroneously, and unnecessary data signal disturbances can be prevented.

In the above embodiment, plesiochronous slip control was performed on the reading side, and implemented as read-discard control or twice-read control, but plesiochronous slip control may be performed on the writing side, and in that case, the above implementation is performed. In response to the discard control in the example,
In response to write stop control of one slip unit of input data and double read control, slip control is performed by writing the same input data twice into the memory for two consecutive slip units.

〔Effect of the invention〕

As described above, according to the present invention, the sampling of the write address signal for detecting the necessity of plesiochronous slip control is performed by avoiding the signal value uncertainty time period that occurs when the signal value changes. This has the effect of providing a plesiochronous slip control circuit that does not perform unnecessary plesiochronous control due to incorrect write address recognition.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a buffer control circuit including a plesiochronous slip control circuit according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the plesiochronous slip control circuit, and FIG. The figure shows the concept of a plesiochronous matching circuit, FIG. 4 shows an example of a conventional plesiochronous matching circuit, and FIG. 5 shows an example of a buffer control circuit including a conventional plesiochronous slip control circuit. It is. 13...Write address counter, 14...
Write address signal, 23... Read address counter, 24... Read address signal, 3
0...Matching buffer memory, 31...Buffer control circuit, 32...Memory control signal, 33...Reading discard control signal, 34...Twice reading control signal, 31
0...Plesiochronous slip control circuit, 31
1...First digital comparison circuit, 312...Read check address setting circuit, 313...Address check timing signal, 314...Latch circuit, 315...Write address check signal, 316...Second digital comparison circuit , 31
7... Third digital comparison circuit, 318... Read-out threshold setting circuit, 319... Twice-read threshold setting circuit, 321... Write address change detection circuit, 322... Read address change detection circuit,
323...Writing and reading control circuit, 324
...Write address change detection signal, 325...
Read address change detection signal, 326...
NOT circuit, 327...Delay circuit, 328...Sample aperture signal, 329...AND circuit,
330...Latch control signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A read check address setting circuit that sets a read check address value, and a digital comparison circuit that compares the set read check address value with the actual read address value and outputs a timing signal based on the comparison result. Based on the timing signal of this digital comparison circuit, a latch circuit that holds the write address value of the transmission signal detects the difference between the write address value held in the latch circuit and the read check address value, and calculates the detection result. and slip control means for generating a slip control signal based on a comparison calculation between the slip control signal and a predetermined set value,
In the plesiochronous slip control circuit that corrects the difference in transmission rate when transmitting and receiving transmission signals between independent digital signal threads, a change in the write address value of the transmission signal is detected and the detection result is a detection circuit that outputs a signal value uncertain time period signal of the write address value based on the write address value; a delay means that delays and outputs the signal value uncertain time period signal output from this detection circuit; 1. A plesiochronous slip control circuit comprising: a logic circuit for controlling the timing at which the write address value of the latch circuit is held based on the signal.