JPH0528775A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] To shorten the rewriting time in the case where information stored in a nonvolatile semiconductor memory device capable of electrically writing and erasing information has a portion that is frequently rewritten and a portion that is not rewritten. It is an object. [Structure] The memory array 1 of the flash EEPROM is divided into two, and the memory cells in one sector 1a of the flash EEPROM can be collectively erased, and the memory cells of the other sector 1b cannot be collectively erased. [Effect] By programming the frequently rewritten portion in the batch erasable sector 1a and programming the non-rewritten portion in the batch unerasable sector 1b, it becomes unnecessary to erase the non-rewritten portion and reprogram. Rewriting time is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to improving the function of a non-volatile semiconductor memory device which can be electrically written and erased.

[0002]

2. Description of the Related Art FIG. 2 is an IEEE Journal of
Solid-State Circuits, Vo
l. 23, No. 5, October 1988 1
Flash EEPRO, which is a conventional electrically erasable nonvolatile semiconductor memory device shown in pages 157 to 1163.
3 shows a block diagram of M. FIG. In the figure, 1 is a memory array, 2 is a Y gate, 3 is a source line switch, 4 is an X decoder, 5 is a Y decoder, 6 is an address register, 7 is an input data register, 8 is a sense amplifier, and 9 is an input / output buffer. 10 is a program voltage generating circuit, 11 is a verify voltage generating circuit, 12 is a command register, 13 is a command decoder, and 14 is an input signal buffer. V _CC ,
V _PP and V _SS are voltages supplied from the outside. / WE,
/ OE, / CE control signal, Function A0 to A14 is an address signal, VO ₀ ~VO ₇ is input and output data signals.

A Y gate 2, a source line switch 3, and an X decoder 4 are connected to the memory array 1. Y gate 2
To the Y decoder. An address register 6 is connected to the X decoder 4 and the Y decoder 5, and address signals A0 to A14 input from the outside are input. An input data register (write circuit) 7 and a sense amplifier 8 are connected to the memory cell 1 via a Y gate and an input / output buffer 9. In addition, the program voltage generation circuit 10,
A verify voltage generating circuit 11 is provided, which generates a voltage different from V _CC and V _PP supplied from the outside, and supplies the voltage to the Y gate 2, the X decoder 4, and the like. A command register 12 and a command coder 13 for setting an operation mode based on data input from the outside are provided. Further, an input signal buffer 14 is provided, and control signals / WE, / CE, / OE from the outside are connected.

FIG. 6 is a sectional view of a memory cell forming the memory array shown in FIG. In the figure, 15 is a semiconductor substrate, 16 is a floating gate, 17 is a control gate, 18 is a source, and 19 is a drain.

The memory cell comprises a floating gate 16 and a control gate 1 formed on a semiconductor substrate 15.
7 and the source diffusion region 18 and the drain diffusion region 19. The oxide film between the floating gate 16 and the semiconductor substrate 15 is thin (about 100 Å), and the floating gate 1 utilizing the tunnel phenomenon is used.
It is possible to move the electrons to 6.

The operation of the memory cell is as follows. During programming, a program voltage of about 6.5 V is applied to the drain electrode 19 and V _PP (12
V) is applied and the source 18 is grounded. For this reason,
The memory cell turns on and a current flows. At this time, avalanche breakdown occurs near the drain 19 and electron-hole pairs are generated. The holes flow to the ground potential through the semiconductor substrate 15, and the electrons flow in the channel direction to flow into the source 18. However, some electrons are floating gate 16
It is accelerated by the electric field between the drains 19 and injected into the floating gate 16. Thus, the threshold value of the memory cell is raised. This is defined as storage of information "0". on the other hand,
For erasing, open drain 19 and control gate 1
7 is grounded and V _PP is applied to the source 18. The tunnel phenomenon occurs due to the electric field between the source 18 and the floating gate 16, and the electrons in the floating gate 16 are extracted. Thus, the threshold value of the memory cell is lowered. This is defined as storage of information "1".

FIG. 7 shows a circuit diagram of the write circuit of the memory cell of FIG. In the figure, 2 is a Y gate, 3 is a source line switch, 4 is an X decoder, 5 is a Y decoder, 77 is a write circuit, 8 is a sense amplifier, 24 is a bit line, 2
5 is a word line, 26 is a Y gate transistor, 27 is I
/ O line, 28 is a source line, Y1 to Y3 are Y decoders and Y
A signal line connecting the gates, 29 is one memory cell.
The drain of the memory cell is connected to the bit line 24, and the control gate is connected to the word line 25. The word line 25 is connected to the X decoder 4, and the bit line 2 is connected to the I / O line 27 via the Y gate transistor 26 whose gate receives the output of the Y decoder 5. I /
The O line 27 is connected to the sense amplifier 8 and the write circuit 77, and the source line 28 is grounded to the source line switch 3.

Next, the operation will be described. Description will be made regarding the case where writing is performed in the memory cell surrounded by the dotted line in FIG. The write circuit 77 is activated according to the data input from the outside, and the program voltage is supplied to the I / O line 27. At the same time, the Y-decoder 5,
The Y gate transistor 26 and the word line 25 are selected through the X decoder 4 and V _PP is applied. Source line 28
Is grounded by the source line switch 3 during programming. In this way, current flows only in one cell in the figure, hot electrons are generated, writing is performed,
The threshold voltage of the memory cell becomes high.

Erasing is performed as follows. First, the X decoder 4 and the Y decoder 5 are inactivated, and all the memory cells are deselected. That is, the control gate 17 of each memory cell is grounded and the drain of each memory cell is opened, while the source line 28 is supplied with a high voltage by the source line switch 3. Thus, due to the tunnel phenomenon, the threshold value of the memory cell shifts to the lower side.
Since the source line 28 is common, all memory cells are erased collectively.

Next, the read operation will be described. Similar to writing, reading of the memory cell surrounded by the dotted line in FIG. 4 will be described. First, the address signal is decoded by the Y decoder 5 and the X decoder 4, and selected Y
The signal lines Y1 to Y3 to the gate transistor 26 and the word line 25 become "H". At this time, the source line 28 of the memory cell is grounded by the source line switch 3. If writing is performed in the memory cell and the information is "0", the threshold value of the memory cell is high and the memory cell is turned on even if "H" is given to the control gate of the memory cell by the word line 25. Otherwise, no current flows from the bit line 24 to the source line 28. On the other hand, if the memory cell is erased and the information is "1", the memory cell is turned on, so that a current flows from the bit line 24 to the source line 28. The sense amplifier 8 detects whether or not a current flows through the memory cell to obtain read data "1" or "0".

In the EPROM, erasing is performed by irradiation of ultraviolet rays. Therefore, when the floating gate becomes electrically neutral, electrons are not extracted from the floating gate any more, and the threshold roughness of the memory transistor becomes about 1 V or less. Don't On the other hand, in the extraction of electrons using the tunnel phenomenon, it is possible that electrons are excessively extracted from the floating gate and the floating gate is positively charged. This phenomenon is called overerase (or overerase). When over-erasing occurs, the threshold value of the memory cell becomes negative, which hinders subsequent reading and writing. That is, even if the level of the word line is unselected during reading and is "L" and the level applied to the control gate of the memory cell is "L", current flows from the bit line through the unselected memory cell. Therefore, even if the threshold voltage is high, "1" is read out from the memory cell on the same bit line to be read out. Further, even during writing, a leak current flows through the over-erased memory cell, which deteriorates the writing characteristics and further disables writing. Therefore, read after erasing to check if the erasing was done correctly (called erase verify), and if there is a bit that is not erased, take the method of erasing again, and the extra erase pulse is applied to the memory cell. Measures have been taken to prevent it being applied.

Each step of erasing and program writing will be described with reference to FIGS. 8, 9, 10 and 5.
8 and 9 are flowcharts of erase and program including such a verify operation, and FIG. 10 is a diagram showing timing waveforms of the procedure of FIGS. 8 and 9. In the conventional flash EEPROM, erasing and program writing modes are set by a combination of input data. That is, the mode is set by the input data when / WE rises.

First, the case of program writing will be described. First, V _CC and V _PP are raised, and V _CC = 5
V, V _PP = V _PPH (step S1), then / W
E is lowered and the initial position of the address is given (step S2). After this, at the rising edge of / WE, "P
The input data (40H) which is ROGRAM-SETUP COMMAND "is latched in the command register 12 (step S3). After that, the input data is decoded by the command decoder 13 and the operation mode becomes the program mode. It is turned off again, the address from the outside is latched in the address register 6, and / W
At the rising edge of E, the data (DIN) which is "PROGRAM DATA" is latched by the write circuit 7 (step S4). Next, a program pulse is generated by the program voltage generation circuit 10 and applied to the X decoder 4 and the Y decoder 5. This state continues for 10 μs, and programming is performed on each memory cell as described with reference to FIG. 4 (step S5). Next, / WE is lowered, and at the subsequent / WE rise, "PROGRAM-VERIFY
COMMAND ″ input data (COH) is latched in the command register 12 and the operation mode becomes the program verify mode (step S6). At this time, the verify voltage generating circuit 11 causes the program verify voltage (.about.7. (0 V) is generated and applied to the X decoder 11 and the Y decoder 5 to perform reading (step S7) Since the voltage applied to the control gate of the memory cell is higher than that during normal reading (5 V), writing is insufficient. The memory cell can be easily turned on, and the write failure can be more surely detected.Next, it is determined whether the number of write repetitions has reached 25 times (step S8), and if it has not reached 25 times, The write data is confirmed (step S9). If al to repeated writing. Writing is performed (step S9), and determines whether the last address has been written (step S10), and to increase the address to be a last address (Step S
11) The above operation is repeated. If it is determined in step S10 that the address is the last address, the operation mode is set to the read mode (step S13), V _PP = V _PPL is set (step S14), and the program ends. If the number of write repetitions reaches 25 in step S7, the write data is confirmed (step S12),
If the writing is insufficient, it is determined that the device is defective and the program ends. If the writing is sufficient in step S12, the process proceeds to step S9.

Next, the case of erasing will be described. First, V _CC and V _PP are raised, V _CC = 5 V, V _PP = V
_It becomes _PPH (step S20), then whether or not "0" is written in all the memory cells, that is, all BY
It is determined whether TE is "00H" (step S21).
If all the memory cells are not "0", "0" is written to all the memory cells by using the above-mentioned program flow (step S22). This is because it is over-erased. Next, / WE is lowered to give the first position of the address (step S23), and at the subsequent rise of / WE, the erase command (20H) which is "ERASE-SETUP COMMAND" is input (step S24).
Then, / WE is lowered again, and the erase command (20H) which is "ERASE COMMAND" is input at the subsequent rise of / WE (step S25). At this time, an erase pulse is generated in the chip, and V _PPH is applied to the source of the memory cell through the source line switch 3 until the trailing edge of / WE (step S26). The address is also latched at this falling edge. Subsequently, at the rising edge of / WE, the data (A0H) which is "ERASE-VERIFY COMMAND" is input to enter the erase verify mode (step S27). At this time, an erase verify voltage (up to 3.2 V) is generated by the verify voltage generating circuit 11 and applied to the X decoder 4 and the Y decoder 5. Since the voltage applied to the control gate of the memory cell is lower than that during normal reading (5V), it becomes difficult to turn on the memory cell that is not sufficiently erased, and the erase failure can be detected more reliably. Next, reading is performed (step S28), then it is determined whether or not the number of erase repetitions has reached 1000 times (step S29), and if not 1000 times, erase data is confirmed (step S).
30). At this time, if the erasing is insufficient, the erasing is further repeated. It is determined whether the erased data of the next address has been verified and the verified address is the last address. If it is not the last address (step S31),
Increase the address and proceed to the next address (step S3
2) If the verified address of the erased data of the next address is the last address (step S31), the operation mode is set to the read mode (step S3).
4), V _PP = V _PPL is set (step S33), and the erasing is completed. When it reaches 1000 times in step S29,
The erase data is confirmed (step S33). If the erase is insufficient, it is determined that the device is defective and the erase is terminated.
If the deletion is sufficient in step S33, step S31
Proceed to.

[0015]

Conventional flash EE
Since the PROM is configured as described above, if the information to be stored has a portion that is frequently rewritten and a portion that is not rewritten, in order to rewrite the information portion that is frequently rewritten, the information portion that is not rewritten in the memory array There is a problem that it is necessary to erase all the information and write all the program information again.

The present invention has been made to solve the above problems, and when information to be stored has a portion that is frequently rewritten and a portion that is not rewritten, it is possible to shorten the information rewriting time of the memory array. To aim.

[0017]

An electrically writable / erasable non-volatile semiconductor memory device according to a first aspect of the present invention includes a memory array having a first sector and a second sector, and an external input. Decoded address signal,
An X-decoder and a Y-decoder for selecting row and column directions of the memory array, and a sense amplifier for determining whether information stored in a memory cell forming the memory array is "1" or "0". The memory cells of the first sector are capable of being erased together, and the second sector
The memory cell of the sector is not erasable.

An electrically writable / erasable non-volatile semiconductor memory device according to a second aspect of the present invention stores a memory cell array including a first sector and a second sector and an address signal input from the outside. Decoding and determining whether the information stored in the memory cell forming the memory cell array is "1" or "0", and the X decoder and the Y decoder for selecting the memory cell array in the row and column directions. And a memory cell of at least one of the first sector and the second sector can be collectively erased by one erase operation.

[0019]

Operation: Electrically writing / writing according to claim 1 of the present invention
An erasable non-volatile semiconductor memory device includes a memory array including a first sector and a second sector, and memory cells in the first sector can be collectively erased. Since the cell cannot be erased,
When the information to be stored has a portion that is frequently rewritten and a portion that is not rewritten, the information portion that is frequently rewritten is programmed to the first sector that can be collectively erased, and the information portion that is not rewritten to the second sector that cannot be collectively erased. By programming, erase the information part that is not rewritten,
Eliminates the need to program.

An electrically writable / erasable nonvolatile semiconductor memory device according to a second aspect of the present invention includes a memory cell array including a first sector and a second sector,
In a case where the memory cells of at least one of the first sector and the second sector can be collectively erased by one erase operation, the information to be stored has a portion that is frequently rewritten and a portion that is not rewritten. , An information part that is not rewritten by programming the information part that is frequently rewritten in the first sector, programming the information part that is not frequently rewritten in the second sector, and rewriting only the information in the first sector as needed. Erasing and reprogramming is eliminated.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a flash EEPROM which is an electrically writable / erasable nonvolatile semiconductor memory device according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a writing circuit of the flash EEPROM shown in FIG. In FIGS. 1 and 3, reference numeral 1a denotes a batch erasable sector, and the sources of the respective memory cells are commonly connected to the source line switch 3. 1b is a non-erasable sector, and the source of each memory cell is grounded. The memory array 1 is composed of 1a and 1b. In FIG. 1, the same symbols as those in FIG. 5 indicate the same contents. 3, the same reference numerals as those in FIG. 7 indicate the same contents.

When rewriting the batch erasable sector 1a, the erasing is the same as the conventional process, and the program performs the conventional programming process on the erased batch erasable sector 1a. Therefore, the number of memory cells to be rewritten is reduced as compared with the related art, and the rewriting time can be shortened.

Next, another embodiment of the present invention will be described with reference to FIG.
And FIG. 4 will be described. FIG. 2 is a block diagram of a flash EEPROM which is an electrically writable / erasable nonvolatile semiconductor memory device according to another embodiment of the present invention. FIG. 4 is a circuit diagram of a write circuit of the flash EEPROM shown in FIG. 2 and 4, 3
Reference numerals a and 3b are source line switches. Reference numeral 1c is a batch erasable sector, and the sources of the memory cells are commonly connected to the source line switch 3a. 1d is an erasable sector, and the sources of the memory cells are commonly connected to the source line switch 3b. The memory array 1 is composed of 1c and 1d. 2 that are the same as those in FIG. 5 indicate the same contents. 4, the same symbols as in FIG. 7 indicate the same contents.

1c and 1d can be erased separately,
For example, when rewriting only the batch erasable sector 1c, the erasing is the same as the conventional process, and the program performs the conventional programming process on the erased batch erasable sector 1c. When rewriting only the batch erasable sector 1d, the erasing is the same as the conventional process, and the program performs the conventional programming process on the erased batch erasable sector 1d. Further, it is possible to rewrite 1c and 1d at the same time, the erasing is the same as the conventional process, and the program performs the conventional programming process for the erased batch erasable sectors 1c and 1d.

In each of the above embodiments, the memory array is equally divided into two sectors. For example, when the BIOS information that is not rewritten often and the DIP switch information that is frequently rewritten are stored in the same storage device. Since the respective information is extremely different, the memory capacity of one batch erasable sector may be several bytes to several tens of bytes.

[0026]

As described above, according to the electrically writable / erasable non-volatile semiconductor memory device according to the first aspect of the present invention, the memory array is divided into two sectors, and one of them is erased collectively. When the information to be stored has a portion that is frequently rewritten and a portion that is not rewritten, the information that is frequently rewritten is programmed into a batch erasable sector and information that is not frequently rewritten By programming the part into a sector that cannot be erased collectively, it is not necessary to erase the information part that is not rewritten and reprogrammed, and the rewriting time can be shortened.

According to a second aspect of the present invention, there is provided an electrically writable / erasable nonvolatile semiconductor memory device in which a memory array is divided into two sectors and a memory cell of at least one sector is subjected to one erase operation. Is erasable in batch, therefore, when the information to be stored has a portion that is frequently rewritten and a portion that is not rewritten, the information portion that is frequently rewritten is programmed in the first sector, and the information portion that is not frequently rewritten is By programming the sector and rewriting only the information of the first sector as necessary, it is not necessary to erase the information part that is not rewritten and reprogram, and the rewriting time can be shortened.

[Brief description of drawings]

FIG. 1 is a flash EEPR according to an embodiment of the present invention.
It is a block diagram of OM.

FIG. 2 is a flash EEP according to another embodiment of the present invention.
It is a block diagram of ROM.

FIG. 3 is a circuit diagram of a writing circuit of the flash EEPROM shown in FIG.

FIG. 4 is a circuit diagram of a write circuit of the flash EEPROM shown in FIG.

FIG. 5 is a block diagram of a conventional flash EEPROM.

6 is a cross-sectional view of the memory cell of FIG.

FIG. 7 is a circuit diagram of a write circuit of the memory cell of FIG.

8 is a flowchart of a program including the verify operation of FIG.

9 is a flowchart of erasing including the verify operation of FIG.

10 is a timing waveform chart of FIGS. 9 and 10. FIG.

[Explanation of symbols]

1a Batch erasable sector 1b Non-erasable sector 1 memory array 2 Y gate 3 Source line switch 4 X decoder 5 Y decoder 6 Address register 7 Input data register 8 sense amplifier 9 I / O buffer

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 20, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art FIG . 5 is an IEEE Journal of
Solid-State Circuits, Vo
l. 23, No. 5, October 1988 1
Flash EEPRO, which is a conventional electrically erasable nonvolatile semiconductor memory device shown in pages 157 to 1163.
3 shows a block diagram of M. FIG. In the figure, 1 is a memory array, 2 is a Y gate, 3 is a source line switch, 4 is an X decoder, 5 is a Y decoder, 6 is an address register, 7 is an input data register, 8 is a sense amplifier, and 9 is an input / output buffer. 10 is a program voltage generating circuit, 11 is a verify voltage generating circuit, 12 is a command register, 13 is a command decoder, and 14 is an input signal buffer. V _CC ,
V _PP and V _SS are voltages supplied from the outside. / WE,
/ OE, / CE control signal, Function A0 to A14 is an address signal, VO ₀ ~VO ₇ is input and output data signals.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

Next, the operation will be described. A case of writing data in the memory cell surrounded by the dotted line in FIG. 7 will be described. The write circuit 77 is activated according to the data input from the outside, and the program voltage is supplied to the I / O line 27. At the same time, the Y-decoder 5,
The Y gate transistor 26 and the word line 25 are selected through the X decoder 4 and V _PP is applied. Source line 28
Is grounded by the source line switch 3 during programming. In this way, current flows only in one cell in the figure, hot electrons are generated, writing is performed,
The threshold voltage of the memory cell becomes high.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

Next, the read operation will be described. Similar to writing, reading of the memory cell surrounded by the dotted line in FIG. 7 will be described. First, the address signal is decoded by the Y decoder 5 and the X decoder 4, and selected Y
The signal lines Y1 to Y3 to the gate transistor 26 and the word line 25 become "H". At this time, the source line 28 of the memory cell is grounded by the source line switch 3. If writing is performed in the memory cell and the information is "0", the threshold value of the memory cell is high and the memory cell is turned on even if "H" is given to the control gate of the memory cell by the word line 25. Otherwise, no current flows from the bit line 24 to the source line 28. On the other hand, if the memory cell is erased and the information is "1", the memory cell is turned on, so that a current flows from the bit line 24 to the source line 28. The sense amplifier 8 detects whether or not a current flows through the memory cell to obtain read data "1" or "0".

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

Since erasing is performed by ultraviolet irradiation in EPROM, when the floating gate becomes electrically neutral, electrons are not extracted from the floating gate any more, and the threshold value of the memory transistor becomes about 1 V or less. Don't On the other hand, in the extraction of electrons using the tunnel phenomenon, it is possible that electrons are excessively extracted from the floating gate and the floating gate is positively charged. This phenomenon is called overerase (or overerase). When over-erasing occurs, the threshold value of the memory cell becomes negative, which hinders subsequent reading and writing. In other words, the level of the non-selected word line at the time of reading a is "L", the notes
Even if the level applied to the control gate of the recell is “L”, the current flows from the bit line through the non-selected memory cell, so that the memory cell attempting to read on the same bit line is written. In this state, "1" is read even if the threshold value is high. Further, even during writing, a leak current flows through the over-erased memory cell, which deteriorates the writing characteristics and further disables writing. Therefore, read after erasing to check if the erasing was done correctly (called erase verify), and if there is a bit that is not erased, take the method of erasing again, and the extra erase pulse is applied to the memory cell. Measures have been taken to prevent it being applied.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

First, the case of program writing will be described. First, V _CC and V _PP are raised, and V _CC = 5
V, V _PP = V _PPH (step S1), then / W
E is lowered and the initial position of the address is given (step S2). After this, at the rising edge of / WE, "P
The input data (40H) which is ROGRAM-SETUP COMMAND "is latched in the command register 12 (step S3). After that, the input data is decoded by the command decoder 13 and the operation mode becomes the program mode. It is turned off again, the address from the outside is latched in the address register 6, and / W
At the rising edge of E, the data (DIN) which is "PROGRAM DATA" is latched by the write circuit 7 (step S4). Next, a program pulse is generated by the program voltage generation circuit 10 and applied to the X decoder 4 and the Y decoder 5. This state continues for 10μs .
Program is performed in each memory cell as described with reference to 7 (step S5). Next, / WE is lowered, and at the subsequent / WE rise, "PROGRAM-VERIFY
COMMAND ″ input data (COH) is latched in the command register 12 and the operation mode becomes the program verify mode (step S6). At this time, the verify voltage generating circuit 11 causes the program verify voltage (.about.7. (0 V) is generated and applied to the X decoder 11 and the Y decoder 5 to perform reading (step S7) Since the voltage applied to the control gate of the memory cell is higher than that during normal reading (5 V), writing is insufficient. The memory cell can be easily turned on, and the write failure can be more surely detected.Next, it is determined whether the number of write repetitions has reached 25 times (step S8), and if it has not reached 25 times, The write data is confirmed (step S9). If al to repeated writing. Writing is performed (step S9), and determines whether the last address has been written (step S10), and to increase the address to be a last address (Step S
11) The above operation is repeated. If it is determined in step S10 that the address is the last address, the operation mode is set to the read mode (step S13), V _PP = V _PPL is set (step S14), and the program ends. If step
If the number of write repetitions reaches 25 in step S8 , the write data is confirmed (step S12),
If the writing is insufficient, it is determined that the device is defective and the program ends. If the writing is sufficient in step S12, the process proceeds to step S10 .

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

Next, the case of erasing will be described. First, V _H and V _H are raised, V _H = 5 V, V _H = V
_It becomes _HH (step S20), then whether or not "0" is written in all memory cells, that is, all BY
It is determined whether TE is "00H" (step S21).
If all the memory cells are not "0", "0" is written to all the memory cells by using the above-mentioned program flow (step S22). This is because it is over-erased. Next, / WE is lowered to give the first position of the address (step S23), and at the subsequent rise of / WE, the erase command (20H) which is "ERASE-SETUP COMMAND" is input (step S24).
Then, / WE is lowered again, and the erase command (20H) which is "ERASE COMMAND" is input at the subsequent rise of / WE (step S25). At this time, an erase pulse is generated inside the chip, and V _HH is applied to the source of the memory cell through the source line switch 3 until the trailing edge of / WE continues (step S26). The address is also latched at this falling edge. Subsequently, at the rising edge of / WE, the data (A0H) which is "ERASE-VERIFY COMMAND" is input to enter the erase verify mode (step S27). At this time, a verify voltage generating circuit verify voltage (up to 3.2 V) is generated and applied to the X decoder 4 and the Y decoder 5. The voltage applied to the control gate of the memory cell is (5
Since it is lower than V), it becomes difficult to turn on an insufficiently erased memory cell, and an erase defect can be detected more reliably. Next, reading is performed (step S28), and then
It is judged whether the number of times of erasing repetition has reached 1000 times (step S29), and if it has not reached 1000 times,
The erased data is confirmed (step S30). This time,
If the erasing is insufficient, the erasing is repeated. If it is erased and the verified address of the erased data of the next address is the last address and it is not the last address (step S31), the address is increased and the process proceeds to the next address (step S32). The erased data of the address of the verified address is the last stored
If no (step S31), the operation mode is set to the read mode (step S34), V _PP = V _PPL is set (step S35 ), and the erasing is completed. Step S2
When it reaches 1000 times in 9, the erase data is confirmed (step S33). If the erase is insufficient, it is determined that the device is defective and the erase is terminated. If the deletion is sufficient in step S33, the process proceeds to step S31.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

Next, another embodiment of the present invention will be described with reference to FIG.
And FIG. 4 will be described. FIG. 2 is a block diagram of a flash EEPROM which is an electrically writable / erasable nonvolatile semiconductor memory device according to another embodiment of the present invention. FIG. 4 is a circuit diagram of a write circuit of the flash EEPROM shown in FIG. 2 and 4, 3
Reference numerals a and 3b are source line switches. 1c is a batch erasable sector, saw the source of each memory cell in common
It is connected to the wire switch 3b . 1d is a batch erasable <br/> ability sectors, saw the source of each memory cell in the common
It is connected to the wire switch 3a . The memory array 1 is composed of 1c and 1d. 2 that are the same as those in FIG. 5 indicate the same contents. 4, the same symbols as in FIG. 7 indicate the same contents.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

1c and 1d can be erased separately,
For example, when rewriting only the sector 1c that can be collectively erased, the erase can be performed collectively through the source line switch 3b.
V _PPH is applied to the source of the memory cell in the correct sector 1c
In this manner , the program performs the conventional programming process on the erased batch erasable sector 1c. In addition, when rewriting only the sector 1d that can be collectively erased,
For erasure, use the source line switch 3a to write a memo in sector 1d.
This is done so that V _PPH is applied to the source of the _recell ,
In the programming, the conventional programming process is performed on the erased batch erasable sector 1d. Further, it is possible to rewrite 1c and 1d at the same time, the erasing is the same as the conventional process, and the program performs the conventional programming process for the erased batch erasable sectors 1c and 1d.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 29/792 8225-4M H01L 29/78 371

Claims (2)

[Claims] 1. A memory array comprising a first sector and a second sector, an X decoder and a Y decoder for decoding an address signal input from the outside and selecting in the row and column directions of the memory array. A memory cell of the first sector is provided with a sense amplifier that determines whether the information stored in the memory cells forming the memory array is “1” or “0”, and the memory cells of the first sector can be erased at once. A non-volatile semiconductor memory device that is electrically writable and erasable, characterized in that the memory cell of the second sector is not erasable. 2. A memory cell array composed of a first sector and a second sector, an X decoder and a Y decoder for decoding an address signal input from the outside to select the memory cell array in the row and column directions. A sense amplifier is provided to determine whether the information stored in the memory cells forming the memory cell array is “1” or “0”, and in one erase operation, the first sector and the second sector An electrically writable and erasable non-volatile semiconductor memory device characterized in that memory cells of at least one of the sectors can be collectively erased.