JPH05289902A - Initial diagnostic circuit for memory - Google Patents

Abstract

PURPOSE:To prevent the generation of an operation disabled state by storing data to be written in a defective memory in a stand-by memory when the defective memory is detected at the time of executing the initial diagnosis of a microprogram memory. CONSTITUTION:This memory initial diagnostic circuit has a stand-by memory 21 in addition to microprogram memories 11 to 15 for normally storing microprograms, and when a defective memory is detected at the time of executing the memory diagnosis of these memories 11 to 15, 21, the information of the defective memory is stored in a defective memory information storing circuit 34, a write data selecting circuit 36 and a read data selecting circuit 37 are controlled by a defective memory data repairment control circuit 38 based upon the defective memory information and data to be written in the defective memory are stored in the stand-by memory 21 and driven. Thus even when a defective memory is generated, a central processing unit(CPU) 1 is not disabled and a program can be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an initial diagnosis circuit for a computer memory, and more particularly to a memory initial diagnosis circuit for improving the reliability of a memory for storing microprograms.

[0002]

2. Description of the Related Art Conventionally, this type of memory initial diagnosis circuit is
For performing initial diagnosis of micro program memory
Address generation circuit that generates addresses, data for initial diagnosis
Data generation circuit for generating data, microprogram
Read the value written in memory (expected value when reading)
In the data comparison circuit, the data comparison circuit that compares the created values
As a result of comparing the expected value with the read data,
If there is a problem, the microprogram memory will be defective.
A microprogram that determines that it has occurred and stores mismatch information
It has a defective gram memory circuit and starts up the computer.
When performing diagnostics on hardware such as
The initial diagnosis of the gram memory was performed and it was written in the memory.
Even if the expected value and the value read from memory match
If there is not, notify the outside of the memory failure.
It was supposed to be.

[0003]

In this conventional memory initial diagnosis circuit, when a defect occurs in a part of a plurality of microprogram memories, the correct microprogram cannot be read and the central processing unit cannot operate normally. Since it cannot be guaranteed, there is a problem that when a data mismatch occurs in the initial diagnosis of the microprogram memory, a memory failure is notified and the electronic computer becomes inoperable.

[0004]

SUMMARY OF THE INVENTION A memory initial diagnosis circuit of the present invention comprises a plurality of microprogram memories for storing microprograms, and an address for generating an address for sequentially accessing all areas of the microprogram memory. A generation circuit, a data generation circuit for generating data to be written in the microprogram memory for memory diagnosis and an expected value to be read from the microprogram memory, and whether or not the data read from the microprogram memory matches the expected value. A data comparison circuit that makes a determination, a defective memory information storage circuit that stores a defective microprogram memory based on the determination result of the data comparison circuit, and a defective memory information storage circuit that stores the defective microprogram memory according to the stored information of the defective memory information storage circuit except during memory diagnosis. On behalf of microprogram memory A spare memory used to store the data, a write data selection circuit that divides the data into a plurality of the microprogram memories, and writes the power data to be written in the defective microprogram memory by switching to the spare memory and writing the data. A read data selection circuit that reads data from a plurality of the microprogram memories according to the storage information of the defective memory information storage circuit to make a microprogram, except for the time of memory diagnosis, and reads out the data of the spare memory instead of the defective microprogram memory. have.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a memory initial diagnosis circuit of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a memory initial diagnosis circuit of the present invention.

The central processing unit 1 is a device in which the memory initial diagnosis circuit of this embodiment is incorporated. The central processing unit 2 is a circuit for executing a micro program, the micro program memories 11, 12, 13, 14, 15 are memories for storing a micro program memory for the central processing unit 2 to operate, and the spare memory 21 is a micro program memory 11 , 12, 13, 14, 15 is a memory for storing a micro program instead when a defect occurs.

The address generation circuit 31 is a circuit for generating an address for the memory initial diagnosis of the microprogram memories 11, 12, 13, 14, 15 and the data generation circuit 32 is the microprogram memories 11, 12, 13 ,.
A circuit for generating data for the memory initial diagnosis of 14, 15 and a data comparison circuit 33 are provided with the expected value generated by the data generation circuit 32 and the microprogram memories 11, 1.
2, 13, 14, and 15 are circuits for comparing values read from each other, and the defective memory information storage circuit 34 is a data comparison circuit 33.
If a mismatch is detected as a result of comparing the expected value generated by the data generation circuit 32 with the values read from the micro program memories 11, 12, 13, 14, 15, the micro program memory reading the mismatched data. Is a defective memory and stores which memory is determined as a defective memory.

The initial memory diagnosis control circuit 35 is a control circuit for performing an initial diagnosis of the microprogram memory. The write data selection circuit 36 is the defective memory storage circuit 3
If the number of defective memories stored in 4 is recoverable by the spare memory 21, the read data selection circuit 37 is a circuit for selecting the data to be written to the spare memory 21 and the read data selection circuit 37 is the defective memory. When the number of defective memories stored in the information storage circuit 34 can be recovered by the spare memory 21, it is a circuit that controls so that the data in the spare memory 21 is read instead of the data to be read from the defective memory.

The defective memory data restoration control circuit 38 generates a signal for controlling the write data selection circuit 36 and the read data selection circuit 37 based on the defective memory information stored in the defective memory information storage circuit 34, and the input / output. The buffers 41, 42, 43, 44, 45, 46 are buffers for controlling the input / output of data of the microprogram memories 11, 12, 13, 14, 15 and the defective memory 21. The address bus 51 is the micro program memory 11, 12,
The address buses to 13, 14, 15 and the data write bus 52 are program memories 11, 12, 13, 14, 15
A write data bus to and a data read bus 53 are read data buses from the program memories 11, 12, 13, 14, and 15.

First, it is assumed that the memory is initially diagnosed at the power-on initialization of the electronic computer, that is, at the first stage of startup. There are various methods for initial memory diagnosis, but basically, it is sufficient if all areas of the memory can be tested for "0" and "1" write, read, and compare of all data hits. In this embodiment, when writing data, the same write address as the write address and the inverted write address of all the bits are prepared so that diagnosis of all bits of the memory can be performed. Now, it is assumed that each of the micro program memories 11, 12, 13, 14, 15 and the spare memory 21 can store 4-bit data for each address.

As shown in the example of FIG. 4, the data generation circuit 32
The data to be output by the above may be written with "0" and "1" for all data bits at each address. Here, in the first writing, the data generation circuit 32 is a circuit that outputs the address on the right side based on the address output from the address generation circuit 31 and outputs "0" to the left-side insufficient portion of the data. The address generation circuit 31 displays "0000 ... 0.
From the address "0" to the address "1111, ...
1, 12, 13, 14, 15 and addresses are generated so that the entire area of the spare memory 21 can be accessed.

At the time of diagnosis, the output of the data generation circuit 32 is divided into n pieces every 4 bits from the left end, and the first 4-bit data from the left side is transferred to the microprogram memory 11.
The second 4-bit data is the microprogram memory 1
2 to 3rd 4-bit data to microprogram memory 13, n-2nd 4bit data to microprogram memory 14, n-1st 4bit data to microprogram memory 15, nth 4bit Data is written in the spare memory 21 (FIG. 5).

Referring to the block diagram of FIG. 1, the fact that the initial memory diagnosis control circuit 35 is in the process of initial memory diagnosis is transmitted to the defective memory data restoration control circuit 38, and the defective memory data restoration control circuit 38 writes. A control signal is output to the data selection circuit 36. This control signal is shown in FIG.
As shown in the internal selector configuration diagram of the write data selection circuit 36 shown in FIG. 3, this is a signal for causing the selector 62 for selecting the data to be written to the spare memory 21 to select the spare memory diagnostic data 101 instead of the repair data 102. .. The spare memory diagnostic data 101 is data that is used only during diagnosis and is connected to the data generation circuit 32, but is not connected to the central processing unit 2.

The output of the address generation circuit 31 is "1111".
If it becomes 11 ", the initial memory diagnostic control circuit 35
Is a microprogram memory 11, 12, 13, 14,
15. Control is performed to read data from the spare memory 21. The address generation circuit 31 again returns "0000 ... 0".
The addresses are added by +1 from the address "0" to "1111 ... 11" and output. The data read from the microprogram memories 11, 12, 13, 14, 15 and the memory 21 are input to the read data selection circuit 37. The defective memory data restoration circuit 38 controls the data selectors 71, 72, 73, 74, 75 so that the spare memory read data 103 read from the spare memory 21 is not transmitted to the data read bus 53 during the initial memory diagnosis ( (Fig. 3).

Micro program memory 11, 12, 1
The data read from 3, 14, 15 and the spare memory 21 is input to the data comparison circuit 33 through the read data selection circuit 37, and the data generation circuit 32 is read from the address generated by the address generation circuit 31 to read the data. Generates an expected value of read data and inputs it to the data comparison circuit 33. The data comparison circuit 33 compares the data read from the microprogram memories 11, 12, 13, 14, 15 and the spare memory 21 with the expected value generated by the data generation circuit 32, and if the comparison results in a match, the data is compared. The next data read is considered as normal.

If there is a mismatch, the data is set to 4
Divide it into bit units, and consider that the micro-program memory corresponding to the part where the inconsistency occurred has an incompatibility,
The information of the defective memory is written in the defective memory storage circuit 34.

FIG. 6 is a diagram for explaining defective memory information stored in the defective memory information storage circuit 34. Here, it is assumed that a mismatch occurs at the third position from the left in 4-bit units. The third from the left in 4-bit units is the data corresponding to the microprogram memory 13 as shown in FIG.
"1" is written in the bit storing the defect information of the third micro program memory 13 from the left. The defective memory information storage circuit 34 is all "0" immediately after power-on initialization, and becomes "1" when the data comparison circuit 33 detects a defective memory during memory diagnosis, and once becomes "1", it becomes "0". The information of the defective memory is retained.

When the read access to the micro program memory is completed up to "1111 ... 11", the initial memory diagnostic control circuit 35 next determines the micro program memory 1
1, 2, 13, 14, 15 and the spare memory 21 are now ready for write access. The address generation circuit 31 returns from "0000 ... 00" to "1111 ... 1" again.
The data generation circuit 32 inverts "0" and "1" of all the bits of the address based on the address output from the address generation circuit 31 and then right-shifts to the right. , The left side of the data is controlled so as to output “1.” In this way, the data generation circuit 32 generates the diagnostic data so that the microprogram memories 11, 12, 13, 14, 15 and the spare memory 21 can be stored. All bits in the entire area can be diagnosed, and the data output from the data generation circuit 32 at this time is input to the write data selection circuit 36 through the data write bus 52 and the spare memory diagnostic data 101.

The write data selection circuit 36 receives the control signal from the defective memory data restoration control circuit 38 and divides the data of the data write bus 52 into the micro program memories 11, 12, 13, 14, and 15 by 4 bits from the left end. Output to the selector 62 for the spare memory 21.
Thus, the spare memory diagnostic data 101 is selected and controlled to be output to the spare memory (FIG. 2).

If the address allocation circuit 31 outputs allores up to "1111 ... 11", the initial memory diagnostic control circuit 35 again returns to the microprogram memory 1
1, 12, 13, 14, 15 and the spare memory 21 are controlled to be read-accessed. The address generation circuit 31 adds "+1" from "0000 ... 00" again by one, and the micro program memories 11, 12, 13,
Read access is made to the memory cells 14 and 15 and the spare memory 21. Each micro program memory 11, 12,
The read data output from 13, 14, 15 and the spare memory 21 are input / output buffers 41, 4 of the central processing unit 1.
It is inputted to the read data selection circuit 37 through 2, 43, 44, 45 and 46. In the read data selection circuit 37,
The selectors 71, 72, 73, 7 are arranged to output the data read from the micro program memories 11, 12, 13, 14, 15 onto the data read bus 53 by the control signal output from the defective memory data repair circuit 38.
4, 75 are controlled by the control signal output from the defective memory data restoration control circuit 38, and the data read from the auxiliary memory 21 is output to the auxiliary memory read data 103 (FIG. 3). The data of the data read bus 53 and the spare memory read data 103 is input to the data comparison circuit 33. The data generation circuit 32 is the address generation circuit 31.
The data expected value read from the microprogram memories 11, 12, 13, 14, 15 and the spare memory 21 at that address is generated from the output address of the above, and is input to the data comparison circuit 33.

The data comparison circuit 33 compares the read data input from the read data selection circuit 37 with the expected value input from the data generation circuit 32. If the data matches the expected value, the initial diagnosis control is performed. The circuit 35 proceeds to start accessing the next address. If the data and the expected value do not match, the information of the microprogram memory in which the mismatch has occurred is stored in the defective memory information storage circuit 34, and the initial memory diagnosis control circuit 35 proceeds to access to the next address. The address output from the address generation circuit 31 is “1”.
When the access up to 111 ... 11 "is completed, the initial memory diagnosis of all areas of the microprogram memories 11, 12, 13, 14, 15 and the spare memory 21 is completed.

Here, after the initial memory diagnosis is completed, it is assumed that the defective memory information storage circuit 34 holds information indicating that the microprogram memory 13 is a defective memory (FIG. 6). In this case, the central processing unit 1 regards the microprogram memory 13 as a memory that does not operate normally, and stores 4 bits of the microprogram to be stored in the microprogram memory 13 in the spare memory 21 (FIG. 7).

Taking a microprogram of one address as an example, if the defective memory information storage circuit 34 does not hold the defective memory information and there is no defective memory, the microprogram memory 11 has a hexadecimal number "A". , "B" in hexadecimal for the micro program memory 12, "C" in hexadecimal for the micro program memory 13, "D" in hexadecimal for the micro program memory 14, and "H" in hexadecimal for the micro program 15. It is assumed that it is a microprogram in which E ″ is stored. If the micro program memory 13 is stored in the defective memory information storage circuit 34 as a defective memory, the defective memory data restoration circuit 38 controls the write data selection circuit 36 and the read data selection circuit 37, and the auxiliary memory 21 is It is used instead of the program memory 13 and stores a part of the "C" microprogram in hexadecimal.

When the micro program memory 13 is determined to be a defective memory, the internal signal of the write data selection circuit 36 is controlled as follows. The defective memory data restoration control circuit 38 controls the selector 61 shown in FIG. 2 to output the data to be written in the defective memory 13 to the selector output 102. The selector 62 is controlled to output the selector output 102 to the spare memory 21. The control of the internal signal of the read data selection circuit 37 is as follows.

The defective memory data restoration control circuit 38 controls the selector 71 to output the data read from the microprogram 11 to the data read bus 53, and controls the selector 72 to read the data read from the microprogram 12. To the data read bus 53, for the selector 73, the data read from the auxiliary memory 21 is set to the data read bus 53, for the selector 74, the data read from the microprogram memory 14 is set to the data read bus 53, and to the sector 75. On the other hand, the data read from the micro program memory 15 is controlled to be output to the data read bus 53.

When the defective memory information storage circuit 34 indicates that there is no defective memory, the write data selection circuit 36.
Does not do anything because there is no data to write to the spare memory 21. In the read data selection circuit 37, the data read from the spare memory 21 is transferred to the data read bus 53.
Output to the micro program memory 11, 12, 1
It is assumed that the data read from 3, 14, and 15 are output to the data read bus 53.

If the defective memory information indicated by the defective memory information storage circuit 34 indicates that only the spare memory 21 is a defective memory (FIG. 8), since the spare memory is not used, it is the same as when there is no defective memory. The defective memory data restoration control circuit 38 controls the write data selection circuit 36 and the read data selection circuit 37.

When the number of the micro program memory and the spare memory judged as the defective memory is larger than the total spare memory number when the defective memory information indicated by the defective memory information storage circuit 34 is inputted to the defective memory data restoration circuit 38. The defective memory data repair circuit 38 judges that the microprogram cannot be stored in the microprogram memory and notifies the central processing unit 2 of the microprogram memory error.

[0030]

As described above, the memory initial diagnosis circuit of the present invention performs the memory diagnosis of the micro program memory for storing the micro program by hardware when the apparatus is started up, and when the defective memory is detected, the failure is detected. By the defective memory information storage circuit which stores the memory information and the defective memory information which the defective memory information storage circuit stores when there is a defective memory in the microprogram memory,
A write data selection circuit that controls the flow of write data so that the data to be stored in the defective memory is written to the spare memory, and the data read from the spare memory is returned to the original correct position and passed correctly to the central processing unit as a micro program. Since it has a read data selection circuit that controls the flow of read data, even if a defective memory is detected as a result of the initial memory diagnosis, if the number of defective memories is less than the number of spare memories, the spare memory replaces the defective memory. It uses memory to store microprograms, so
In the case of a small number of memory defects, there is an effect that the electronic computer can operate without becoming inoperable.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a write data selection circuit 36 in FIG.

3 is an internal configuration diagram of a read data selection circuit 37 in FIG.

4 is an explanatory diagram of generation of address / data for initial memory diagnosis in the embodiment shown in FIG. 1. FIG.

FIG. 5 is an explanatory diagram showing in which memory write data is stored during memory diagnosis in the embodiment shown in FIG. 1;

6 is an explanatory diagram of defective memory information storage of a defective memory information storage circuit in FIG. 1. FIG.

FIG. 7 is an explanatory diagram of backup memory storage data when a defective memory occurs in the embodiment shown in FIG.

FIG. 8 is an explanatory diagram of data storage when the spare memory 21 in the embodiment shown in FIG. 1 is defective.

[Explanation of symbols]

1 Central Processing Unit 2 Central Processing Unit 11, 12, 13, 14, 15 Micro Program Memory 21 Spare Memory 31 Address Generation Circuit 32 Data Generation Circuit 33 Data Comparison Circuit 34 Bad Memory Information Storage Circuit 35 Initial Memory Diagnostic Control Circuit 36 Write Data Selection circuit 37 Read data selection circuit 38 Bad memory data repair control circuit 41, 42, 43, 44, 45, 46 Input / output buffer 51 Address bus 52 Data write bus 53 Data read bus 61, 62, 71, 72, 73, 74 , 75 selector 101 spare memory diagnostic data 102 selector output 103 spare memory read data

Claims (1)

[Claims] 1. A plurality of microprogram memories for storing microprograms, an address generation circuit for generating addresses for sequentially accessing all areas of the microprogram memory, and the microprogram memory for memory diagnosis. A data generation circuit that generates data to be written and an expected value to be read from the microprogram memory, a data comparison circuit that determines whether the data read from the microprogram memory and the expected value match, and a data comparison circuit of the data comparison circuit. A defective memory information storage circuit that stores the defective micro program memory based on the determination result, and is used to store data in place of the defective micro program memory according to the stored information of the defective memory information storage circuit except during memory diagnosis. Reserved memory, A write data selection circuit that divides data into a plurality of the microprogram memories and writes to the spare memory the write data that is to be written to the defective microprogram memory, and the storage information of the defective memory information storage circuit except during memory diagnosis And a read data selection circuit for reading data from the spare memory in place of the defective microprogram memory by reading data from the plurality of microprogram memories in accordance with the above.