JPH05291844A - Level shift circuit - Google Patents

Abstract

PURPOSE:To provide a differential amplifier circuit in which two level shift quantities are made equal to each other even when currents from a 1st current source and a 2nd current source differ. CONSTITUTION:A base of a transistor(TR) Q1 connects to an input terminal VIN1 and a base of a TRQ2 connects to an input terminal VIN2, a base of a TRQ3 and a collector of a TRQ4 are connected to an emitter of the TRQ1, a base of the TRQ4 and a collector of the TRQ3 are connected to an emitter of the TRQ2, one terminal of the current source I1 and an output terminal VOUT1 are connected to an emitter of the TRQ3 and one terminal of the current source I2 and an output terminal VOUT2 are connected to an emitter of the TRQ4, and the other terminal of the current sources 11,12 connect to the voltage source V1 and the collectors of the TRs Q1,Q2 connect to the voltage source V2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit which is a front circuit of a differential amplifier.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a structure of a conventional differential amplifier circuit. In the figure, the base of the transistor Q1 is connected to the input terminal V _IN1 , the base of the transistor Q2 is connected to the input terminal V _IN2 , and the voltage source V ₂ is connected to the respective collectors. The emitter and the base of the transistor Q4 are connected to the emitter of the transistor Q1, the collector and base of the transistor Q3 are connected to the emitter of the transistor Q2, and the output terminal V _{OUT2 is connected} to the emitter of the transistor Q3.
And a current source I ₂ are connected. Further, the output terminal V _OUT1 and the current source I ₁ are connected to the emitter of the transistor Q4, and the other ends of the current sources I ₁ and I ₂ are connected to the voltage source V ₁ . The above configuration, the relationship of the input and output _{V OUT1 = V IN1 + V BE} (Q1) + V BE (Q4) = V IN1 +2 · V T l n (I 1 / I s) I s: saturation current V _OUT2 = V _IN2 + 2 · V _T l _n (I ₂ / I _s ), and if V _IN1 = V _IN2 then V _OUT1 −V _OUT2 = 2 · V _T l _n (I ₁ / I ₂ ) and there are two level shift amounts. It can be seen that the error of ₁ depends on I ₁ and I ₂ .

[0003]

However, in the above-mentioned conventional differential amplifier circuit, the first current source and the second current source are used.
There is a disadvantage that the shift amounts of the first level shift circuit and the second level shift circuit do not become the same unless the values of the current sources are the same.

The differential amplifier circuit of the present invention has been made in view of such a problem, and an object thereof is to achieve 2 even if the values of the first current source and the second current source are different. It is to provide a differential amplifier circuit having the same level shift amount.

[0005]

In order to achieve the above-mentioned object, the level shift circuit of the present invention is a first level shift circuit in which two voltage shifters equally shift the voltage by 2 V _BE or more.
The base of the first transistor is connected to the input terminal of the second transistor, and the base of the second transistor is connected to the second input terminal of the first transistor.
The emitter of the third transistor is connected to the base of the third transistor and the collector of the fourth transistor, and the emitter of the second transistor is connected to the collector of the third transistor and the base of the fourth transistor. Is connected to one end of the first current source and the first output terminal, and the emitter of the fourth transistor is connected to one end of the second current source and the second output terminal. The ends are connected to the first voltage source and the collectors of the first and second transistors are connected to the second voltage source.

[0006]

That is, in the level shift circuit of the present invention, the base of the first transistor is connected to the first input terminal,
The base of the second transistor is connected to the second input terminal, the base of the third transistor and the collector of the fourth transistor are connected to the emitter of the first transistor, and
The collector of the third transistor and the base of the fourth transistor are connected to the emitter of the transistor of
One end of the first current source and the first
The output terminal of the second transistor is connected to the emitter of the fourth transistor at one end of the second current source and the second output terminal.
The other end of the current source is connected to the first voltage source, and the collectors of the first and second transistors are connected to the second voltage source. As a result, 2 from the first input terminal to the first output terminal
The collector current flowing through one level shift transistor and the collector current flowing through the two level shift transistors from the second input terminal to the second output terminal are the same.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram showing a first embodiment. This figure shows an example of a level shift circuit for lowering 2V _BE . The input terminal V _IN1 is the base of the transistor Q1, the input terminal V _IN2 is the base of the transistor Q2, and the emitter of the transistor Q1 is the base of the transistor Q3. The collector of the transistor Q4 is connected, the emitter of the transistor Q2 is connected to the base of the transistor Q4, and the collector of the transistor Q3 is connected to the transistor Q3.
The output terminal V _OUT1 and the current source I ₁ are connected to the emitter of the transistor Q4, and the output terminal V _OUT2 and the current source I ₂ are connected to the emitter of the transistor Q4.
Is further connected, the voltage source V ₁ is connected to the other ends of the current sources I ₁ and I ₂ , and the voltage source V ₂ is connected to the collectors of the transistors Q1 and Q2. From the above configuration, the relationship between input and output _{V OUT1 = V IN1 + V BE} (Q1) + V BE (Q3) = V IN1 + V T l n (I 2 / I s) + V T l n (I 1 / I s) _{V OUT2 = V IN2 + V T} l n Therefore _{(I 1 / I s) +} V T l n (I 2 / I s) V OUT1 -V OUT2 = V IN1 -V IN2, V IN1 = if V _IN2 I ₁ ≠ Even for I ₂ , V _OUT1 = V _OUT2 .

FIG. 2 shows a second embodiment, which is 2V _BE.
This is a level shift circuit for lowering. The configuration of this level shift circuit will be described below. In the figure, the input terminal V
The base of the transistor Q11 is connected to the input terminal V _{IN2 at IN1.}
The base of the transistor Q12 is
The base of the transistor Q13 and the collector of the transistor Q14 are connected to the emitter of
The base of the transistor Q14 and the collector of the transistor Q13 are connected to the emitter of the transistor Q14, and the output terminal V _OUT1 and the current source I ₁₂ are connected to the emitter of the transistor Q13.
Output terminal V _OUT2 and the current source I ₁₁ to the emitter 14 is connected, furthermore, a voltage source V ₁₂ to the other end of the current source I _11, I ₁₂ is connected, a voltage source V ₁₁ to the collector of the transistor Q11, Q12 is It is connected.

FIG. 3 shows a third embodiment of the present invention, which is a circuit for level shifting 2 V _BE or more. The circuit configuration is different from that of the first embodiment of FIG. 1 in that R is provided between the emitter of the transistor Q4, the output terminal V _OUT2 and the current source I _2.
4, R3 between the emitter of the transistor Q3 and the output terminal V _OUT1 and the current source I ₁ , R1 between the emitter of the transistor Q1 and the base of the transistor Q3 and the collector of the transistor Q4, and between the emitter of the transistor Q2 and the transistor Q3. The point is that R2 is interposed between the collector and the base of the transistor Q4. The relationship of input and output is V _OUT1 = V _IN1 + V _{BE (Q1)} + R1 · I ₂ + V _{BE (Q3)} + R3 · I ₁ = V _IN1 + V _T l _n (I _c2 / I _s ) + R 1 · I ₂ + V _T l from _{n (I 1 / I s)} + R3 · I 1 V OUT2 = V IN2 + V T l n (I 1 / I s) + R2 · I 1 + V T l n (I 2 / I s) + R4 · I 2 or more , V _OUT1 −V _OUT2 = V _IN1 −V _IN2 + (R3-
_{R2) I 1 + (R1-} R4) has a I _2, where, V
_{If IN1} = V _IN2 , R1 = R4, R3 = R2, then V _OUT1 −V _OUT2 = 0.

FIG. 4 shows a fourth embodiment, which is 2V _BE.
This is a circuit for level shifting. The circuit configuration differs from that of the embodiment of FIG. 2 in that the emitter of the transistor Q12, the base of the transistor Q14, and the transistor Q13.
R12 is connected between the collectors of the transistors, the emitter of the transistor Q11, the base of the transistor Q13, and the transistor Q14.
The R11 between collector, emitter and a current source I ₁₁ and R14 between the output terminal V _OUT2 is an emitter output terminal V _OUT1 and a current source I ₁₂ of the transistor Q13 of transistors Q14
The point is that R13 is connected between them.

[0012]

As described above in detail, in two level shift circuits that equally level shift by 2 V _BE or more, even if the values of the two current sources are different, the two shift amounts can be the same.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a level shift circuit of the present invention.

FIG. 2 is a circuit configuration diagram showing a second embodiment of the level shift circuit of the present invention.

FIG. 3 is a circuit configuration diagram showing a third embodiment of the level shift circuit of the present invention.

FIG. 4 is a circuit configuration diagram showing a fourth embodiment of the level shift circuit of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional level shift circuit.

[Explanation of symbols]

Q1 to Q4 ... Transistors, V _IN1 , V _IN2 ... Input terminals, V _OUT1 , V _OUT2 ... Output terminals, I ₁ , I ₂ ... Current source,
V _1, V ₂ ... voltage source.

Claims (2)

[Claims] 1. In two level shift circuits which equally shift a voltage by 2 V _BE or more, the base of a first transistor is connected to a first input terminal and the base of a second transistor is connected to a second input terminal, The emitter of the first transistor is connected to the base of the third transistor and the collector of the fourth transistor, and the emitter of the second transistor is connected to the collector of the third transistor and the base of the fourth transistor. Is connected to one end of the first current source and the first output terminal, and to the emitter of the fourth transistor is connected to one end of the second current source and the second output terminal. The other end of which is connected to the first voltage source and the collectors of the first and second transistors are connected to the second voltage source. 2. In the level shift circuit, a first resistor is provided between the emitter of the first transistor, the base of the third transistor, and the collector of the fourth transistor, and the emitter of the second transistor and the third transistor. A second resistor between the collector of the second transistor and the base of the fourth transistor, and a third resistor having the same value as the second resistor between the emitter of the third transistor, the first output terminal and the first current source. And a fourth resistor having the same value as that of the first resistor interposed between the emitter of the fourth transistor, the second output terminal, and the second current source.