JPS6322150B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an absolute value circuit for obtaining the absolute value of an electrical signal, which is often required during various arithmetic operations.

Conventionally, various absolute value circuits have been proposed, but
Many of them used operational amplifiers and the like, which increased the number of circuit elements used, making them unsuitable for use in semiconductor integrated circuits (ICs).

The object of the present invention is to provide an absolute value circuit that does not use an operational amplifier, has a simple circuit configuration, and is suitable for IC implementation.

FIG. 1 is a circuit diagram showing an embodiment of this invention.
1 and 2 are input terminals between which an alternating input signal is supplied, 3 and 4 are respectively input terminals 1
and 2 are transistors for emitter followers whose bases are connected, 5 and 6 are output transistors whose bases are connected to the bases of transistors 3 and 4, respectively, and 7 and 8 are emitter constant current sources (current The values are I ₀₁ and I ₀₂ ), 9 and 1, respectively.
0 is the emitter constant current source of output transistors 5 and 6, respectively (current values are I _A and I _B respectively),
Reference numeral 11 denotes a resistor (to which a voltage generated between the emitter of the emitter follower transistor 4 and the emitter of the output transistor 5 due to the alternating input voltage applied between the input terminals 1 and 2 is applied, through which a corresponding current flows). _Similarly , 12 is a resistor (resistance value
R ₂ ), 13 is the load resistance (resistance value) of the commonly connected collectors of both output transistors 5 and 6.
R ₃ ), 14 are connected to the commonly connected collectors of both output transistors 5 and 6, and together with emitter constant current sources 9 and 10, are constant current sources for suppressing offset output due to output imbalance when the input voltage is near zero. (current value Ic), 15 is a constant voltage source (voltage value E _b ) for operating this circuit, and 16 and 17 are output terminals.

FIG. 2 is an input/output waveform diagram for explaining the operation of this circuit, and the horizontal axis indicates time t. In FIG. 2, A is the input signal v _i , B is the output voltage v ₀ when constant current sources 9, 10, and 14 are not provided, and C is the output voltage v when constant current sources 9, 10, and 14 are provided. ₀
shows. The operation of this circuit will be explained below with reference to FIG.

At time t ₀ shown in FIG. 2, constant voltage source 15 is connected, and at time t ₁ potentials v ₁ and v ₂ are supplied to input terminals 1 and 2, respectively, and between the terminals v _i = v ₁ −
An input voltage of v ₂ is applied as shown in FIG. 2A.

First, constant current sources 9 and 10 for suppressing offset output
The case where there is no 14 and 14 will be explained. Time t ₁
Since v ₁ > v ₂ , that is, v _i > 0 between ~t ₂ ,
Transistor 5 tends to be on, transistor 6 tends to be off, the current I ₁ shown in Figure 1 flows, and I ₂ tends to zero, and the current flowing at this time I ₁ is I ₁ = [v ₁ - (kT/ q)ln(I ₁ /Is) + (kT/q)ln
{(I ₀₁ − I ₁ )/Is} − v ₂ ]/R ₁ = (v ₁ − v ₂ )/R ₁
+{kT/(qR ₁ )}ln{(I ₀₁ −I ₁ )/I ₁ }
…[] is.

However, k: Boltzmann constant T: absolute temperature q: electron charge I _s : reverse saturation current of the transistor.

And the output voltage at this time is [v ₀ ] _v1 > _v2 = (R ₃ / R ₁ ) [v ₁ − v ₂ + (kT/q) ln
{(I ₀₁ −I ₁ )/I ₁ }] ...[].

Then, between time points t ₂ and _{t 3} , v ₁ < v ₂ , i.e., v _i <
0, transistor 5 tends to be off, transistor 6 tends to be on, current I ₂ flows, I ₁ tends to zero, and current I ₂ flowing at this time is I ₂ = (v ₂ − v ₁ )/R ₂ + {kT/(qR ₂ )}ln{(I ₀₂ −
I ₂ )/I ₂ } …[], and the output voltage at this time is [v ₀ ] _v2 > _v1 = (R ₃ / R ₂ ) [v ₂ − v ₁ + (kT/q) ln
{(I ₀₂ −I ₂ )/I ₂ }] ...[].

If we choose R ₁ = R ₂ in the above formulas [] and [],
The gains for the potential difference between the inputs are both R ₃ /R ₁ and are equal, and as shown in Figure 2B, t = t ₁ ~
It can be seen that the absolute value output has the same output amplitude during t ₂ and between t=t ₂ and t ₃ .

Now, if we pay attention to the time point t=t ₂ , v ₁ - v ₂ = 0
The first term on the right side of the above equations [] and [] is zero, but the second term is I ₀₁ > 0, I ₀₂ > 0, so I ₁
>0, I ₂ >0, [I ₁ ] _v1=v2 = {kT/(qR ₁ )}ln{(I ₀₁ −I ₁ )/I ₁
}
…[] [I ₂ ] _v1=v2 = {kT/(qR ₁ )}ln{(I ₀₂ −I ₂ )/I ₂
}
…It does not become zero like []. And time points t ₁ , t ₂ , t ₃
In other words, the output voltage when v ₁ −v ₂ = 0 is [v ₀ ] _t=t1 = {[I ₁ ] _v1=v2 + [I ₂ ] _v1=v2 }R ₃ = [{
kT/
(qR ₁ )}ln{(I ₀₁ −I ₁ )/I ₁ }+{kT/(qR ₂ )}
ln {(I ₀₂ − I ₂ )/I ₂ }] R ₃ ≡v Although it has the disadvantage that it does not become zero and has an offset of a certain value v as shown in Figure 2B, it is absolutely It can be seen that it operates as a value circuit.

Next, a means for eliminating the offset voltage v will be explained. First, connect the constant current source 14 (constant current sources 9 and 10 are not provided, I _A = 0, I _B = 0), and calculate the current I _C of the constant current source 14 as I _C = {kT/(qR ₁ )} ln{(I ₀₁ −I ₁ )/I ₁ }+{kT/
(qR ₂ )}ln{(I ₀₂ −I ₂ )/I ₂ }, the above [] in the state of v ₁ = v ₂ = 0 at time t ₁ , t ₂ , t ₃ , Since the offset current of the formula [] can be supplied, the offset current flowing through the output resistor 13 can be reduced to zero, and as shown in Figure 2C, an improved absolute value output than that shown in Figure 2B can be obtained. It will be done.

Furthermore, by adding constant current circuits 9 and 10, I _C = I _A
I _A , at any current value while satisfying the condition +I _B
By setting _IB , an excellent absolute value output as shown in FIG. 2C can be obtained. At this time,
The current I ₁ flowing between time t ₁ and _{t 2} is I ₁ = (v ₁ − v ₂ )/R ₁ + {kT/(qR ₁ )}ln{(I ₀₁ −
I ₁ )/(I _A + I ₁ )} The current I ₂ flowing between time t ₂ and _{t 3} is I ₂ = (v ₁ − v ₂ )/R ₂ + {kT/(qR ₂ )} ln {( I ₀₂ −
I ₂ )/(I _B + I ₂ )} The current at time t ₁ , t ₂ , t ₃ is I _A = I _B , I ₀₁ = I ₀₂ , [I ₁ ] _t1 = [I ₂ ] _t2 = 0 becomes.

Of course, a similar absolute value circuit can be obtained even if the circuit is complementary to the circuit of the embodiment shown in FIG.

As explained above, the absolute value circuit according to the present invention can be constructed with a simple circuit without using an operational amplifier, and is suitable for IC implementation and has a wide range of applications.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining its operation. In the figure, 1 is the first input terminal, 2 is the second input terminal, 3 is the first transistor, 4 is the third transistor, 5 is the second transistor, 6 is the fourth transistor, and 11 is the fourth transistor. 2 is a resistor, 12 is a first resistor, 13 is a load resistor, and 16 and 17 are output terminals.

Claims (1)

[Claims] 1 Consisting of first and second transistors, both of which have their bases connected to the first input terminal, third and fourth transistors, both of which have their bases connected to the second input terminal, and the first transistor described above. a first resistor connected between an emitter output terminal of the first emitter follower circuit and an emitter of the fourth transistor; and an emitter output of a second emitter follower circuit configured by the third transistor. a second resistor connected between the terminal and the emitter of the second transistor, and a second resistor connected in common to the collectors of the second and fourth transistors to form an output amplification circuit together with the second and fourth transistors; An absolute value circuit characterized by comprising a load resistor.