JPH0529253A - Wiring formation method - Google Patents

Abstract

(57) [Abstract] [Purpose] An Al-based material is uniformly embedded in a high-aspect-ratio contact hole having a barrier metal structure. The photo-assisted LP using, for example, dicyclopentadienyl titanium diazide as a raw material after the inside of the contact hole 3a opened in the SiO ₂ interlayer insulating film 3 is covered with a thin Ti layer 4 by a sputtering method or the like.
The TiN _x layer 4 is formed by the CVD method. This TiN _x
The layer 4 has better step coverage than that formed by the sputtering method, and is formed to have a sufficient thickness even in the inner part of the contact hole 3a. After that, when the Al-1% Si layer 6 is formed by high temperature sputtering, the Al-1
The% Si layer 6 is drawn into the inside of the contact hole 3a due to the interfacial reaction with the TiN _x layer 4, and is finally buried uniformly without generating a void.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method applied to the manufacture of semiconductor devices and the like, and more particularly to a method for uniformly burying an aluminum (Al) -based material in a contact portion having a barrier metal structure.

[0002]

2. Description of the Related Art As seen in recent VLSI, ULSI, etc., as the design rule of semiconductor devices is highly reduced, an opening is formed in an interlayer insulating film for connecting a lower layer wiring and an upper layer wiring. The opening diameter of the connection hole is also miniaturized, and the aspect ratio is becoming larger than 1. The upper layer wiring is generally formed by depositing an Al-based material by a sputtering method, but it is difficult to achieve sufficient step coverage (step coverage) to fill a connection hole having such a high aspect ratio. It is also a cause of disconnection.

Therefore, a high temperature sputtering method has been proposed in recent years as a measure for improving the lack of step coverage. In this method, sputtering is performed while heating the wafer to several hundreds of degrees Celsius through a heater block or the like. According to this method, the step coverage can be improved by the reflow effect of the Al-based material layer due to the high temperature. It is known that in the high temperature sputtering method, when a titanium (Ti) layer or a titanium nitride (TiN _x ) layer is provided as a base of the Al-based material layer, the connection hole is well filled. It is explained that this is because the filling proceeds while the interface reaction occurs between the Ti layer or the TiN _x layer and the Al-based material layer. For this process,
In the examples described below, with reference to the drawings,
The summary is as follows. At the initial stage of film growth, the Al-based material layer grown on the flat surface of the wafer squeezes out to the edge portion of the connection hole, and the tip of this squeezed portion eventually fuses to close the connection hole. Although the inside of the connection hole is hollow, the Al-based material layer is a Ti layer or TiN coating the inner wall of the connection hole.
Interfacial reaction with the _x- layer occurs, and it is gradually drawn into the inside, and finally the connection holes are filled without gaps.

[0004]

Considering the above-mentioned embedding mechanism, A having a Ti layer or a TiN _x layer as an underlayer is used.
The high temperature sputtering of 1 is expected as a technology that can also be applied to the filling of connection holes having a considerably high aspect ratio. However, this is only Ti layer, TiN
It is premised that the underlayer such as the _x layer is formed with good step coverage. These underlayers are usually formed by the sputtering method. However, if the aspect ratio of the connection hole is further increased in the future, the step coverage of the underlayer is deteriorated, and this is likely to limit the practicality of the process. .. This problem will be described with reference to FIG.

FIG. 12A shows the impurity diffusion region 32 in advance.
An interlayer insulating film 33 is formed on the semiconductor substrate 31 formed as a lower layer wiring, a contact hole 33a facing the impurity diffusion region 32 is opened in the interlayer insulating film 33, and the entire surface of the wafer is covered with the Ti layer 34 and TiN. _It shows a state of being covered with a barrier metal having a two-layer structure composed of the _x layer 35. The reason why the barrier metal has a two-layer structure is that the Ti layer 34 achieves a low resistance ohmic contact and the TiN _x layer 35 compensates for the insufficient barrier property.

However, the contact hole 33a
When the aspect ratio of the barrier metal becomes higher, the step coverage of the barrier metal deteriorates significantly. Since the Ti layer 34 is originally formed only thinly, the layer thickness is extremely thin at the bottom of the contact hole 33a and the side wall near the bottom. One of the TiN _x layers 35 is formed to be slightly thicker than the Ti layer 34, but the overhang portion 35a is formed first near the opening end of the contact hole 33a, so that the inner deep portion of the contact hole 33a is formed. Then, film growth is extremely hindered. That is, as long as the underlying film is formed only by the sputtering method, a sufficient amount of Ti is reached to the inner depth of the contact hole 33a having a high aspect ratio.
The layer 34 and the TiN _x layer 35 cannot be formed.

Even if the Al-based material layer 36 is formed by the high temperature sputtering method in such a state, the filling of the contact hole 33a is stopped when the interface reaction with the base becomes difficult to proceed, As shown in FIG. 12 (b), a void 37 remains at the bottom of the contact hole 33a. Therefore, it is an object of the present invention to provide a method of improving the step coverage of a barrier metal and making it possible to fill a connection hole with an Al-based material layer by the high temperature sputtering method without generating voids.

[0008]

The wiring forming method of the present invention is proposed in order to achieve the above-mentioned object, and CVD is formed on at least the bottom surface and side wall surface of the connection hole formed in the insulating film on the substrate. a step of forming the TiN _x layer by law, characterized by a step of forming an Al-based material layer as to fill at least the connection hole while heating the substrate.

[0009]

As a result of studies to achieve the above object, the present inventor considered that a CVD method, which is superior in step coverage than the sputtering method, was adopted as a method for forming the TiN _x layer. Regarding the formation of the TiN _x layer by the CVD method, research has just started in recent years, and it cannot be said that the raw material has been established. However, for example, Monthly Semiconductor World January 1991 issue, 130
On pages 132 to 132 (published by Press Journal), biscyclopentadienyl titanium diazide [hereinafter referred to as Cp ₂ Ti (N ₃ ) ₂ is used as a raw material. ] By performing photo-assisted LPCVD with a TiN film having a good step coverage of 0.5 μm diameter contact holes.
An example of coating with _x layers has been reported.

If the step coverage of the TiN _x layer is good,
Even when the Al-based material layer is formed thereon, the interface reaction between the TiN _x layer and the Al-based material layer proceeds smoothly from the opening end to the bottom of the connection hole, so that the connection hole is uniformly filled. Is possible.

[0011]

EXAMPLE 1 In this example, of the barrier metal having a two-layer structure of Ti layer / TiN _x layer, the TiN _x layer was Cp ₂ Ti (N ₃ ) ₂
In this example, a contact hole is filled with an Al-1% Si layer by a high temperature sputtering method after a film is formed by a photo-assisted LPCVD method using as a raw material. This process will be described with reference to FIGS.

First, as shown in FIG. 1, an SiO ₂ interlayer insulating film 3 having a layer thickness of about 0.8 μm is formed by a CVD method or the like on a silicon substrate 1 on which an impurity diffusion region 2 is formed in advance. _{2 The} above-mentioned impurity diffusion region 2 is formed in the interlayer insulating film 3.
A wafer having a contact hole 4 with a diameter of about 0.4 μm is prepared so that the Ti layer 4 and T
The iN _x layer 5 was sequentially formed.

Here, the Ti layer 4 is made of Ar as an example.
Flow rate 100SCCM, gas pressure 0.47Pa (3.5mT
orr), DC sputtering power 4 kW, and wafer heating temperature of about 150 ° C. Sputtering was performed to form a film having a thickness of about 0.03 μm. In addition, the above Ti
The N _x layer 5 was C sublimated by heating at about 150 ° C. under reduced pressure.
A film of about 0.07 μm was formed on a wafer held at a temperature of about 400 ° C. while irradiating a vapor of p ₂ Ti (N ₃ ) _{2 with} an ultraviolet lamp. At this time, since the cyclopentadienyl (Cp) group is stabilized by resonance, the bond cleaved by photoexcitation is the bond between the Cp group and the Ti atom. As a result, a chemical species containing only the constituent elements of TiN _x is generated in the vapor phase, and the chemical species sufficiently migrates on the surface of the wafer heated under reduced pressure, so that good step coverage is obtained. The TiN _x layer 5 was deposited. Carbon was hardly mixed in the TiN _x layer 5, and the film quality and the barrier property were good.

Next, as an example, Ar flow rate 100 SCC
Al, by performing high temperature sputtering under the conditions of M, gas pressure 0.47 Pa (3.5 mTorr), DC sputtering power 4.5 kW, and wafer heating temperature 500 ° C.
% Si layer 6 was formed. Under the above conditions, the film formation rate is about 0.3 μm / min. The reason why the film formation rate is relatively low is that the contact time between the TiN _x layer 5 and the Al-1% Si layer 6 is This is for ensuring a long time and allowing the interfacial reaction to proceed sufficiently.

In this process, the Al-1% Si layer 6 first starts to grow on the flat surface of the wafer and forms an overhang at the open end of the contact hole 3a as shown in FIG. This overhang eventually merges from the surroundings as shown in FIG. 3, but the Al-1% Si layer 6 continues to descend along the inner wall of the contact hole 3a as shown in FIG. Filled the contact hole 3a uniformly as shown in FIG.

The film formation conditions for the Al-1% Si layer 6 are not limited to the above conditions. For example, the wafer heating temperature is about 470 to 530 ° C. and the gas pressure is 0.27.
It can be appropriately set within a range of about 0.53 Pa (2 to 4 mTorr). The DC sputtering power is preferably set so that the film forming rate is about 0.3 μm / minute, and is usually about 5 kW or less. R
F bias is approximately 200-450V (13.56M
(In the case of Hz), or may not be applied.

Embodiment 2 In this embodiment, a contact hole opened to face a titanium silicide (TiSi ₂ ) layer is formed by Cp ₂ Ti.
This is an example in which a contact hole is filled with an Al layer by a high temperature sputtering method after being covered with a TiN _x layer formed by a photo-assisted LPCVD method using (N ₃ ) ₂ as a raw material. This process will be described with reference to FIGS.

First, as shown in FIG. 6, a field oxide film 12 is formed on a silicon substrate 11 by, for example, the LOCOS method, and an element formation region defined by the field oxide film 12 is provided with a gate insulating film 13 interposed therebetween. DOPO
The gate electrode 14 made of S or the like was formed. Next, using the gate electrode 14 as a mask, the source / drain regions 15 are formed.
CV after the first ion implantation for forming
The side wall 16 made of silicon oxide or the like was formed by a conventional method such as D method and RIE.

Further, after removing the natural oxide film existing on the surface of the element forming region with dilute hydrofluoric acid, 50 are respectively formed on the element forming region and the gate electrode 14 by thermal oxidation, for example.
Å thick SiO ₂ layers 17 and 18 were formed. Here, the natural oxide film is removed in advance in order to make the thickness of the SiO ₂ layer 17 on the element formation region uniform. Also S
The iO ₂ layers 17 and 18 are not formed by surface oxidation of the substrate as described above, but, for example, a polycrystalline silicon layer is deposited on the entire surface of the substrate and then thermally oxidized to form a thick SiO ₂ layer. Alternatively, it may be formed by subsequently performing etching with dilute hydrofluoric acid to reduce the layer thickness to a desired thickness.

Further, using the gate electrode 14 and the sidewall 16 as a mask, a second ion implantation for increasing the impurity concentration in a part of the source / drain region 15 was performed through the SiO ₂ layer 17. .. In this way, the LDD structure is achieved. At this time, the SiO ₂ layer 18 on the gate electrode 14 also functions as a layer for preventing channeling due to implanted ions.

Next, as an example, an argon flow rate of 100 SC
CM, gas pressure 0.47Pa (3.5mTorr), DC
Sputtering power 4kW, Wafer heating temperature 300 ℃
Then, Ti was sputtered under the above conditions, and as shown in FIG. 7, a Ti layer 19 was formed to a thickness of about 0.03 μm on the entire surface of the substrate.

Next, Ar is applied to the wafer shown in FIG.
Lamp annealing is performed at 650 ° C. for 30 seconds in an atmosphere, and a part of the Ti layer 19, the silicon substrate 11 (accurately, the source / drain region 15) and the gate electrode 14 are respectively subjected to the SiO ₂ layers 17 and 18. To form TiSi layers (not shown). Subsequently, the wafer is, for example, H ₂ O ₂ : NH ₄ OH: H ₂ O.
= 2: 1: 2 (molar ratio) was immersed in the mixed solution for 10 minutes to selectively remove the unreacted portion of the Ti layer 19 by etching.

Further, lamp annealing is performed at 900 ° C. for 30 seconds in an N ₂ atmosphere to further react the TiSi layer with the silicon substrate 11 and the gate electrode 14.
As shown in FIG. 8, the TiSi ₂ layer 17a,
18a was formed. Here, the reason why the lamp annealing for silicidation is performed in two steps as described above is to form the TiSi ₂ layers 17a and 18a on the element formation region and the gate electrode with good selectivity. .. If silicidation is performed near 900 ° C. from the beginning, TiSi is even deposited on the field oxide film 12 and the sidewalls 16.
_{Since the two} layers 7a and 8a are formed to extend, there is a high possibility that the leak current between the gate electrode 14 and the source / drain regions 15 will increase.

A series of processes from the above-mentioned formation of the SiO ₂ layers 17 and 18 to the formation of the TiSi ₂ layers 17a and 18a was first proposed by the applicant of the present application in Japanese Patent Laid-Open No. 3-38823 and published monthly. It is also introduced in the June 1991 issue of Semiconductor World, pages 44-48 (published by Press Journal). With respect to this process, since the silicidation reaction is performed through the oxide layer, the SITO X (= silicidatio)
The name "n through oxide" has been proposed. Conventional general salicide (SALICID
Since the TiSi ₂ layer can be selectively formed only in the element formation region as compared with the E = selfaligned silicide) method, a MOS having excellent junction leakage characteristics can be obtained.
You can create transistors. Further, since the silicidation reaction rate at the time of film formation is small, the film quality is extremely dense and uniform, and high barrier property is obtained, and further, the sheet resistance is kept low even after high temperature annealing.

Next, as shown in FIG. 9, an SiO ₂ interlayer insulating film 20 is formed on the entire surface of the wafer by, for example, the CVD method, and then the SiO ₂ interlayer insulating film 20 is patterned to form the source / drain regions 15. Top TiSi ₂ layer 17
Contact hole 20a with a diameter of about 0.4 μm facing a
Opened. Further, by performing photo-assisted CVD under the same conditions as in Example 1, a thickness of about 0.0 is formed on the entire surface of the wafer.
A 7 μm TiN _x layer 21 was formed. The TiN _x layer 2
The step coverage of No. 1 was extremely good.

When the underlying layer of the contact hole 20a is the TiSi ₂ layer 17a as in this embodiment,
Since the TiSi ₂ layer 17 achieves a sufficiently low sheet resistance and a high barrier property, it is not necessary to provide a Ti layer as a base of the TiN _x layer 21 as in Example 1.

Next, high temperature sputtering was performed under the same conditions as in Example 1 to form an Al layer 22 on the entire surface of the wafer. At this time, since the underlying TiN _x layer 21 satisfactorily covers the inner wall portion of the contact hole 20a, the contact hole 20a is filled with the Al film 22 and the TiN _x layer 21 as shown in FIG. The reaction proceeded smoothly due to the interfacial reaction between. Finally, as shown in FIG. 11, the contact hole 20a was uniformly filled with the Al film 22.

In this embodiment, the contact hole 2
Pure Al was used for embedding 0a, but this is SITO.
TiSi formed by the X method and having excellent barrier properties
_This is an advantage obtained by using the _two layers 17a as a base. Conventionally, Al-1 has been used as a wiring material for semiconductor devices.
% Si alloys have been widely used. This is based on the idea that the solid solution of Al to the underlying silicon substrate is prevented by preliminarily containing Si up to the solid solution limit in Al. However, when various heat treatments are performed in the manufacturing process of a semiconductor device, there is a great possibility that Si may be segregated to cause an increase in contact resistance or occurrence of connection failure, which is a serious problem as the diameter of the contact hole is reduced. It was feared that However, as in this example, pure A
If l can be used, such a problem does not occur.

[0029]

As is apparent from the above description, when the present invention is applied, Al is used even in a connection hole having a high aspect ratio.
The system material layer can be uniformly embedded, and a wiring with low resistance and high reliability can be formed. Therefore,
The present invention is extremely suitable for manufacturing a semiconductor device which is designed based on a fine design rule and has a high degree of integration and high performance.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a process of applying a contact
A Ti layer is formed on the entire surface of the wafer having holes by a sputtering method, and TiN _{x is formed} by a photo-assisted LPCVD method.
It is a schematic sectional drawing which shows the state in which layers were sequentially formed.

2 is a schematic cross-sectional view showing an initial state in which an Al-1% Si layer grows on the wafer shown in FIG.

FIG. 3 is a schematic cross-sectional view showing a state in which the growth of the Al-1% Si layer has further advanced.

FIG. 4 is a schematic cross-sectional view showing a state in which an Al-1% Si layer is further drawn inside the contact hole.

FIG. 5 is a schematic cross-sectional view showing a state in which a contact hole is completely filled with an Al-1% Si layer.

FIG. 6 is a view showing an example of a process in which the present invention is applied to the wiring formation of a MOS transistor whose resistance is reduced by a TiSi ₂ layer, in which SiO _{2 is} formed on the element formation region and the gate electrode.
It is a schematic sectional drawing which shows the state in which the layer was formed.

7 is a schematic cross-sectional view showing a state where a Ti layer is formed on the entire surface of the wafer shown in FIG.

FIG. 8 is a schematic cross-sectional view showing a state in which a TiSi ₂ layer is selectively formed on a source / drain region and a gate electrode by a silicidation reaction.

FIG. 9: TiSi _{2 is} formed by patterning the interlayer insulating film.
FIG. 3 is a schematic cross-sectional view showing a state in which a contact hole facing the layer is opened and a TiN _x layer is formed on the entire surface of the wafer by a CVD method.

FIG. 10 is a schematic cross-sectional view showing a state in which an Al layer is being formed on the entire surface of a wafer.

FIG. 11 is a schematic cross-sectional view showing a state in which a contact hole is completely filled with an Al layer.

FIG. 12 is a schematic cross-sectional view for explaining a problem in embedding a conventional contact hole, FIG.
Indicates a state in which the step coverage of the TiN _x layer is deteriorated, and (b) indicates a state in which the contact hole is not completely filled with the Al-based material layer and a void is generated.

[Explanation of symbols]

1, 11 ・ ・ ・ Silicon substrate 2 ・ ・ ・ Impurity diffusion region 3, 20 ・ ・ ・ SiO ₂ interlayer insulating film 3a, 20a ・ ・ ・ Contact hole 4 ・ ・ ・ Ti layer 5, 21 ・ ・ ・ TiN _x layer 6 ··· Al-1% Si layer 15 ... source / drain regions 17a ... TiSi ₂ layer 22 ... Al layer

Claims (1)

Claim: What is claimed is: 1. A step of depositing a titanium nitride layer on at least a bottom surface and a side wall surface of a connection hole opened in an insulating film on a substrate by a CVD method, and at least heating the substrate while heating the substrate. And a step of forming an aluminum-based material layer so as to fill the connection hole.