JPH0529408A - Ic tester - Google Patents

Abstract

PURPOSE:To reduce the time of a test by providing the following: a means which prohibits the reset operation of a voltage at a pin electronics part and the make-and-break operation of a relay in a signal route to an IC under test; and a changeover part which changes over the connection between a plurality of address generation parts and a pattern memory part. CONSTITUTION:After the execution of a pattern A has been finished, a control part 1 does not execute the make-and-break operation of a relay between a pin electronics part 10 and an IC 12 under test and immediately instructs a subaddress control part 4 to perform a test by using a test pattern B. The control part performs a changeover control operation to a changeover part 6 in such a way that an address data in a subaddress generation part 5 is sent out to a pattern memory part 7. The subaddress control part 4 controls the subaddress generation part 5 and generates the test pattern B. While the test pattern B is being executed, the control part 1 instructs a main address control part 2 to set an address at the top of the main memory part 7 in a test pattern C which is executed next; the control part sets a pattern generation treatment on standby until the execution of the test pattern B is finished. Thereby, the time of a test can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester, and more particularly to control of its pattern generator.

[0002]

2. Description of the Related Art A conventional IC tester tests the electrical characteristics of a DUT by applying a power supply voltage or a signal to an IC under test (hereinafter referred to as a DUT) and comparing an output signal from the DUT with an expected value. It is a thing. Especially IC function and A
When testing the C characteristics, data called a test pattern obtained by logically simulating the operation of the IC with a computer is used for the test.

The capacity of the test pattern used for the test becomes longer with the higher integration and higher functionality of the IC, and it may be larger than the capacity of the test pattern memory for execution (hereinafter referred to as the test pattern memory) inside the IC tester. In this case, one test pattern capacity must be less than or equal to the pattern memory capacity, and is divided into a plurality of test patterns larger than the test pattern memory capacity and used for the test.

Further, when a test pattern is created, one IC has a plurality of test patterns in order to create each functional block inside the IC, and it is possible to test using these plurality of test patterns. is there. This tendency is particularly remarkable in microprocessor ICs.

A case where an IC is tested using a plurality of test patterns will be described with reference to FIG. Figure 3
(A) is a block diagram of a pattern generation mechanism of an example of a conventional IC tester. FIG. 3B is an example of a test program using three test patterns A, B, and C.
3C shows a processing operation inside the IC tester in the section P in the test program of FIG. 3B with time.

In FIG. 3A, 1a is a control unit, 2a is an address control unit, 3a is an address generation unit, 7 is a pattern memory unit, 13 is a timing generation unit, 9 is a format unit, 1
Reference numeral 0 is a pin electronics section connected to the DUT 12. In the command statement in the test program of FIG. 3B, “POWER ON” and “POWER OFF” mean application and interruption of the power supply voltage from the IC tray 20b to the DUT 12, respectively, and “TEST“ A ””. "TE
“ST“ B ”” and “TEST“ C ”” mean test using test patterns A, B, and C, respectively.

In this test program, the IC tester 2
The control unit 1a inside 0b applies a predetermined power supply voltage to the DUT by the command of "POWER ON". Next, the control unit 1a sets the voltage level of the driver and the comparator inside the pin electronics unit 10 (hereinafter abbreviated as DC level) by the command of "TEST" A "", and the signal path between the pin electronics unit 10 and the DUT 12 is set. Close the relay and connect electrically. Further, the control unit 1a sends the head address data of the test pattern A in the pattern memory 7 to the address control unit 2a to the address generation unit 3a.

The address generator 3a generates address data based on the clock of the timing generator 13 and sends it to the pattern memory unit 7. The pattern memory unit 7 sends to the format unit 9 the data written in the pattern memory unit 7 corresponding to the address data generated by the address generating unit 3a. The format unit 9 is the pattern memory unit 7.
Data is formed into a predetermined waveform and applied to the DUT 12 via the pin electronics section 10.

After the execution of the test pattern A is completed, the control section 1a opens the above-mentioned relay. Next, the control unit 1a uses the test programs “TEST“ B ”” and “TEST”.
With respect to the command "C"", the same processing as" TEST "A""is performed on the test patterns B and C. FIG. 3C shows this series of processes over time.

[0010]

The above-mentioned conventional IC tester uses a test pattern under the control of the control unit to generate a D pattern.
Every time the UT is tested, DC in the pin electronics section
To set the level, open / close the relay of the signal path to the pin electronics section and the DUT, and set the start address data of the test pattern stored in the test pattern memory section to the address control section. When performing a continuous test without changing the DC level by using, there is a drawback that the setting process for the number of times of tests is required and the test time becomes long.

An object of the present invention is to provide an IC tester having a short test time.

[0012]

The IC tester of the present invention comprises:
When conducting a continuous test by a plurality of test patterns without resetting the voltage levels of the driver and the comparator of the pin electronics part connected to the IC under test, the pin electronics part after the test pattern is completed under the control of the control part. Means for prohibiting resetting of voltage and opening / closing of a relay of a signal path to the IC under test, address control units and address generation units of a plurality of pattern memories for performing generation control of the test pattern executed immediately thereafter, and a plurality of them The address generating unit and the switching unit for switching the connection between the pattern memory unit and.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1A is a block diagram of a pattern generation mechanism according to the first embodiment of the present invention. FIG. 1B is a time chart of the processing operation inside the IC tester at the time of a continuous test using a plurality of test patterns. In FIG. 1A, 1 is a control unit in the IC tester 20, 3 is a main address generation unit, 4 is a sub address control unit,
5 is a sub-address generator, 6 is a switching unit, 7 is a pattern memory unit, 8 is a timing generator, 9 is a format unit, 1
Reference numeral 0 is a pin electronics section connected to the DUT.

When the test program shown in FIG. 3B is executed, the control unit 1 inside the IC tester 20 performs a test pattern A to be executed in advance on the main pattern address control unit 2 and the sub pattern address control unit 4. , B of the test pattern memory unit 7 are allocated, set, and transmitted.

Further, the control unit 1 is a pin electronics 1
The DC level inside 0 is set, and the relay in the signal path between the pin electronics section 10 and the DUT 12 is closed to electrically connect them. The main address controller 2 controls the traveling of the test pattern A under the control of the controller 1. The sub address control unit 4 waits until the execution of the test pattern A is completed.

After the execution of the test pattern A is finished, the control unit 1
Without opening / closing the relay between the pin electronics unit 10 and the DUT 12, the sub address control unit 4 is immediately notified to
The test by the test pattern B is instructed, and the switching unit 6 is controlled so that the address data of the sub address generating unit 5 is sent to the pattern memory unit 7.

The sub address controller 4 controls the sub address generator 5 to generate a test pattern B. The control unit 1
During execution of the test pattern B, the head address data of the pattern memory unit 7 of the test pattern C to be executed next is set to the main address control unit 2, and the pattern generation processing is made to wait until the execution of the test pattern B is completed.

After the execution of the test pattern B is completed, the control unit 1
Without resetting the C level of the pin electronics section 6 and opening / closing processing of the relay of the path, the main address control section 2 is immediately instructed to perform the test with the test pattern C, and the switching section 6 is addressed by the address of the address generation section 3. Switching control is performed so that the data is sent to the pattern memory unit 7.

The main address controller 2 controls the main address generator 3 to generate a test pattern C. The control unit 1
After execution of test pattern C, pin electronics section 1
The relay between 0 and the DUT 12 is cut off, and the continuous test by a plurality of test patterns is completed.

FIG. 2 shows a second embodiment of the present invention, which has a data holding section 11 between the format 9 and the pin electronics section 10. If the total test pattern capacity used for the test is larger than the test pattern memory capacity, the entire test pattern cannot be stored in the test pattern memory, so the test pattern memory other than the test pattern memory is stored in the buffer memory, and the test pattern to be executed is buffered. Read from memory to test pattern memory and execute.

During this read time, in order to prevent the signal to the DUT from changing and becoming indefinite between test pattern executions, the data holding section 11 holds the test pattern data applied immediately before.

[0022]

According to the IC tester of the present invention, when a continuous test by a plurality of test patterns is executed without changing the DC level of the pin electronics section, the control section controls the pin electronics section after the test pattern is completed. D
The C level setting and the opening / closing process of the relay of the signal path to the pin electronics section and the DUT are prohibited, and the start address data of the test pattern of the test pattern to be executed in advance is allocated to the plurality of pattern address control sections and set. Since the test pattern generation control is alternately performed, the DC level of the pin electronics section after the test pattern is set, the relay opening / closing processing of the signal path to the pin electronics section and the DUT, and the address establishment processing of the test pattern to be executed next are performed. It can be omitted to reduce the test time.

[Brief description of drawings]

1A and 1B are a block diagram and a time chart for explaining the operation of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

3A to 3C are a block diagram of an example of a conventional IC tester, a partial diagram of a test program for explaining the operation, and a time chart, respectively.

[Explanation of symbols]

 1 Control Section 2 Main Address Control Section 3 Main Address Generation Section 4 Sub Address Counter Section 5 Sub Address Generation Section 6 Switching Section 7 Pattern Memory Section 8 Timing Generation Section 9 Format Section 10 Pin Electronics Section 11 Data Storage Section 12 DUT 20 IC Tester

Claims (1)

Claim: What is claimed is: 1. When performing continuous tests by a plurality of test patterns without resetting the voltage levels of the driver and the comparator of the pin electronics part connected to the IC under test, the control under the control of the control part. Resetting the voltage of the pin electronics section after the test pattern is completed and
A means for prohibiting the opening and closing of the relay of the signal path to C, an address control section and an address generation section of a plurality of pattern memories for controlling the generation of the test pattern to be executed immediately thereafter, and a plurality of address generation sections and a pattern memory section thereof. An IC tester having a switching section for switching the connection with.