JPH0529560A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To obtain a device structure of an inverter circuit in a semiconductor device and a manufacturing method thereof in which the area of the element can be reduced and the capacity can be increased regardless of the gate width of the transistor. [Structure] After forming sources 8 and 9 in a silicon substrate 1, an epitaxial silicon layer is grown, and a gate electrode 18 and a drain 2 are formed in a direction perpendicular to the main surface of the silicon substrate 1.
Since 7 and 29 are formed, it is possible to obtain a semiconductor device capable of reducing the area of the element and increasing the capacity regardless of the gate width of the transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter circuit in a semiconductor device, and more particularly to a device structure of a semiconductor device capable of reducing the element area and increasing the capacity, and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 15 is a structural sectional view showing a device structure of an inverter circuit in a conventional semiconductor device, in which 1 is a silicon substrate, 2 is a P well, 3 is an N well, 4 is an element isolation region, Reference numeral 5 is an ion for preventing a parasitic channel, 6 is a gate oxide film, 7 is polycrystalline silicon to be a gate electrode, 8 is a source / drain region of an N-channel transistor, 9 is a source / drain region of a P-channel transistor, and 10 is an interlayer. An insulating film, 11 is a contact hole, and 12 is an aluminum wiring. 16 shows a circuit configuration of an inverter circuit in the above semiconductor device.

Next, a manufacturing method will be described. 100 KeV of B on the silicon substrate 1, 1.0 to 5.0 × 10 ¹³ cm
^{About -2} is injected only into the N channel region to form the P well 2. Similarly, P is 60 KeV, 1.0 to 9.0 × 1
The N well 3 is formed by implanting only about 0 ¹² cm ^{-2 in} the P channel region.

Next, the element isolation region 4 is formed of a silicon oxide film. At this time, in the element isolation region 4 of the P well 2, B as a parasitic channel preventing ion 5 is formed under the silicon oxide film.
Is injected at 50 KeV, about 1 to 2 × 10 ¹³ cm ^-2 .

Next, a gate electrode made of a gate oxide film 6 having a film thickness of about 100 to 200 Å and a polycrystalline silicon 7 having a film thickness of about 1500 to 3000 Å is formed.

Next, 50 KeV of As is applied only to the P well 2,
Implanting about 1 to 5 × 10 ¹⁵ cm ^-2 to form the source / drain regions 8 of the N-channel transistor.

Next, B is added to the N well 3 only at 30 KeV,
Implanting about 1 to 5 × 10 ¹⁵ cm ^-2 to form the source / drain regions 9 of the P-channel transistor.

Next, the interlayer insulating film 10 having a film thickness of about 10000 angstrom is deposited and connected. Source and drain regions 8 of the polycrystalline silicon 7 and each transistor,
Only the interlayer insulating film 10 of 9 is removed by etching to form the contact hole 11.

Finally, each element is connected by the aluminum wiring 12. A circuit diagram of the inverter circuit thus formed is shown in FIG.

[0010]

Since the conventional semiconductor device is configured as described above, since two transistors of the inverter circuit are formed, the element area is determined by the gate width of the transistor, and However, there was a problem that the increase in capacity would hinder the increase in capacity.

The present invention has been made to solve the above problems, and provides a semiconductor device capable of reducing the area of the element and increasing the capacity regardless of the gate width of the transistor, and a method of manufacturing the same. The purpose is to

[0012]

In the semiconductor device according to the present invention, the gates, sources, channels, and drains of P-channel and N-channel transistors are formed in the direction perpendicular to the main surface of the semiconductor substrate.

In the method of manufacturing a semiconductor device according to the present invention, the source regions of the N-channel and P-channel transistors are formed on the semiconductor substrate, and the N-type epitaxial silicon layer is grown to form the P-well and the N-well. After forming and, an element isolation region and a gate electrode region are formed. Next, the element isolation region and the gate electrode region are etched in a direction perpendicular to the main surface of the semiconductor substrate, an insulating film is buried therein, and a source wall for forming sources of the N-channel and P-channel transistors is formed. And diffuse to form the sources of N-channel and P-channel transistors. Next, the insulating film in the gate electrode region is etched deeper than the source, the gate oxide film is formed by thermal oxidation, the gate electrode is formed so as to fall below the silicon main surface, and then the N well is formed in the P well and the N well. The channel and the drain of the P-channel transistor are formed, the interlayer insulating film is laminated on the gate oxide film, the source and the drain of the N-channel and the P-channel transistor,
Etching off only the interlayer insulating film in each region of the gate,
A contact hole is formed and each area is connected by aluminum wiring.

[0014]

In the present invention, the gates, sources, channels, and drains of N-channel and P-channel transistors are formed in the vertical direction with respect to the main surface of the semiconductor substrate. The area can be reduced and the capacity can be increased.

The method of manufacturing a semiconductor device according to the present invention is
Since the channel is formed by the epitaxial layer and the source and the drain are formed by ion implantation and diffusion, the channel can be formed by the existing manufacturing process.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a structural cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. In the figure, 1 to 12 show the same parts as in the conventional example. 18 is a gate electrode region, 27
Is a drain region of the N-channel transistor, and 29 is a drain region of the P-channel transistor.

2 to 12 are process cross-sectional views showing a manufacturing process of a semiconductor device, in which 13 is a resist for forming a source of a P-channel transistor,
14 is a resist for forming the source of the N channel transistor, 15 is an epitaxial silicon layer, 16 is a resist for forming a P well, 17 is a resist for forming an element isolation region and a gate electrode region, and 18 is a gate. Electrode region, 19 is a resist for ion implantation for parasitic channel prevention, 20 is a TEOS oxide film, 21 is a resist for forming a source wall of an N-channel transistor, 22 is a source wall, and 23 is a source wall of a P-channel transistor. For resisting, 24 for the source wall of the P-channel transistor, 25 for etching the TEOS oxide film of the gate electrode, 26 for forming the drain of the N-channel transistor, and 27 for the drain of the N-channel transistor. Area, 28 Resist for forming the drain of the P-channel transistor 30 is a resist for forming contact holes.

Next, the manufacturing method will be described. First, using the resist 13 as a mask, B is added to the portion of the silicon substrate 1 which becomes the source 9 of the P-channel transistor shown in FIG.
Implant about 0 to 9 × 10 ¹⁵ cm ^{−2 at 0} KeV. afterwards,
The resist 13 is removed by ashing with O ₂ plasma or the like.
Next, using the resist 14 as a mask, 50 KeV of 5 to 9 × 10 ¹⁵ cm ^{-2 is} implanted into the portion of the silicon substrate 1 which will be the source 8 of the N-channel transistor shown in FIG. After that, the resist 14 is removed by ashing with O ₂ plasma or the like. Next, as shown in FIG. 4, an N-type epitaxial silicon layer 15 is grown, B is 100 KeV, 1 to 1 in the P well 2 which becomes the N channel transistor region of the epitaxial silicon layer 15 using the resist 16 as a mask.
Inject about 5 × 10 ¹³ cm ^-2 . Then, the resist 16 is removed by ashing with O ₂ plasma or the like.

Next, the B of the P well 2 is diffused to form the P well 2
And the N well 3 are formed, the resist 17 is used as a mask to form the element isolation region 4 as shown in FIG. At this time, the gate electrode region 18 is also etched at the same time. Next, as shown in FIG. 6, the element isolation region 4 and the gate electrode region 1
After anisotropic etching of 8 with a fluorine-based gas or the like, B is 50 KeV, 1 to 5 × as a parasitic channel preventing ion 5 formed only in the element isolation region 4 formed in the P well 2 using the resist 19 as a mask. Inject about 10 ¹³ cm ^-2 . After that, the resists 17 and 19 are removed by ashing with O ₂ plasma or the like.

Next, as shown in FIG. 7, a TEOS oxide film 20 is formed.
By depositing, the insulating film can be embedded in the element isolation region 4 and the gate electrode region 18. This is because the TEOS oxide film 20 is deposited on the entire surface of the wafer so as to sufficiently fill the element isolation region 4, and then the BHF having a composition ratio of 15: 1 is deposited.
It is possible to form the TEOS oxide film 20 by etching the entire surface of the wafer by the above method so that the TEOS oxide film 20 remains only in the element isolation region 4 and the gate electrode region 18. Further, by using the resist 21 as a mask, P is formed to form a source wall 22 for connecting the source 8 of the N-channel transistor.
Inject. After that, the resist 21 is removed by ashing with O ₂ plasma or the like. Next, as shown in FIG.
Using 3 as a mask, B is implanted to form a source wall 24 for connecting the source 9 of the P-channel transistor. After that, the resist 23 is removed by ashing with O ₂ plasma or the like.

Next, diffusion is performed to form the source 8 of the N-channel transistor and the source 9 of the P-channel transistor as shown in FIG. 9, and then the TEOS oxide film 20 of the gate electrode 18 is covered with a fluorine-based gas using the resist 25 as a mask. Etching with. At this time, 0.1 more than the sources 8 and 9
Etching is deep to about 0.2 μm. This is to avoid the resistance generated by the offset between the sources 8 and 9 and the gate electrode 18. Then, the resist 25 is removed by ashing with O ₂ plasma or the like. Next, as shown in FIG. 10, a gate oxide film 6 having a film thickness of about 100 to 200 angstrom is formed by thermal oxidation, and polycrystalline silicon 7 is deposited on the entire surface of the wafer so that the gate electrode 18 is sufficiently buried. The entire surface of the wafer is etched by the gas so that the gate electrode 18 is about 0.5 to 2 μm lower than the silicon main surface. Then, using the resist 26 as a mask, As is implanted into the region of the drain 27 of the N-channel transistor at about 50 KeV and 1 to 5 × 10 ¹⁵ cm ^-2 . After that, the resist 26 is removed by ashing with O ₂ plasma or the like.

Next, using the resist 28 as a mask, FIG.
B is implanted into the region of the drain 29 of the P-channel transistor shown in FIG. 1 at about 30 KeV and about 1 × 5 × 10 ¹⁵ cm ⁻² . After that, the resist 28 is removed by ashing with O ₂ plasma or the like. Next, as shown in FIG. 12, the drain 2 is formed by diffusion.
After forming 7, 29, the interlayer insulating film 10 having a film thickness of about 10000 angstrom is deposited. Then, only the polycrystalline silicon 7 to be connected by using the resist 30 as a mask and the interlayer insulating film in the regions of the sources 8 and 9 and the drains 27 and 29 of each transistor are removed by etching with a fluorine-based gas to form the contact holes 11. . Then, the resist 30 is removed by ashing with O ₂ plasma or the like. Finally, as shown in FIG. 1, each element is connected by aluminum wiring 12.

In this embodiment, the source, channel, and drain of the transistor are stacked vertically with respect to the main surface of the semiconductor substrate 1 so that the P-channel transistor and the N-channel transistor forming the inverter circuit face each other. Since the insulating film 6 and the gate electrode 7 are arranged on the side surface of the channel, regardless of the gate width of the transistor,
A semiconductor device can be obtained in which the area of the element can be reduced and the capacity can be increased.

In the above-mentioned embodiment, the source and drain of the transistor are formed by injecting and diffusing B and As into the silicon substrate 1 and the epitaxial silicon layer 15, but the N-type and P-type are described. It may be formed by alternately laminating the polycrystalline silicon of, and the same effect as that of the above-described embodiment is obtained.

The second embodiment of the present invention thus configured will be described below with reference to the drawings. 13 and 14 are process cross-sectional views showing a manufacturing process of a semiconductor device according to another embodiment of the present invention. In the drawings, the same reference numerals as those in the above-mentioned embodiments indicate the same or corresponding portions.

Next, the manufacturing process will be described. After forming the element isolation region 4 and the gate electrode 18 on the silicon substrate 1 as shown in FIG. 13, the N-type polycrystalline silicon 8, P-type polycrystalline silicon 2, and N-type polycrystalline silicon 27 are formed in the N-channel region. Depot in order. Further, P-type polycrystalline silicon 9, N-type polycrystalline silicon 3, and P-type polycrystalline silicon 29 are deposited in this order in the P-channel region. Then, as shown in FIG. 14, after masking the gate electrode 18 with the resist 31, etching is performed with a fluorine-based gas or the like until each polycrystalline silicon on the element isolation region 4 is completely removed. As a result, the same structure as that of the above-described embodiment shown in FIG. 11 is obtained.

In the above embodiment, the source 8 and the source 9 of each transistor are formed as shown in FIG. 4 and then the epitaxial silicon layer 15 is grown to form the channel and drain regions. 1M ~
Source 8, 9 by injection with high acceleration of about 10 MV
By forming, the source, channel and drain of each transistor can be formed in the silicon substrate 1.

In the above embodiment, the gate oxide film 6
Has been described as an example of being formed by thermal oxidation,
Oxygen ions are implanted into the area where the gate oxide film 6 is formed,
It can also be obtained by annealing.

Further, although the above embodiment has been described by taking as an example the use in the inverter circuit, by using two sets of the same inverter circuit, the static random
It can be configured as a memory cell of the access memory.

[0030]

As described above, according to the semiconductor device of the present invention, the source, channel, and drain of the transistor are stacked in the direction perpendicular to the main surface of the semiconductor substrate,
P-channel transistor and N forming the inverter circuit
Since the insulating film and the gate electrode are arranged on the side surfaces of the channel facing the channel transistor, there is an effect that a device area can be reduced and a semiconductor device having a large capacity can be obtained regardless of the gate width of the transistor.

According to the method of manufacturing the semiconductor device of the present invention, the source regions of the N-channel and P-channel transistors are formed on the semiconductor substrate, the N-type epitaxial silicon layer is grown, and the P-well and the N-well are formed. After forming and, the element isolation region and the gate electrode region are formed, and then the element isolation region and the gate electrode region are etched in the direction perpendicular to the main surface of the semiconductor substrate, and an insulating film is buried and formed therein. A source wall for forming the sources of the N-channel and P-channel transistors is formed, diffusion is performed to form the sources of the N-channel and P-channel transistors, and then the insulating film of the gate electrode is etched deeper than the sources. , The gate oxide film is formed by thermal oxidation, and the gate electrode is formed so as to be lower than the silicon main surface. And drains of N-channel and P-channel transistors are formed in the N-well, and an interlayer insulating film is laminated on the gate oxide film, and only the interlayer insulating films of the source, drain and gate regions of the N-channel and P-channel transistors are formed. Since the contact holes are formed by etching and the respective regions are connected by the aluminum wiring, there is an effect that they can be formed by the existing manufacturing process.

[Brief description of drawings]

FIG. 1 is a structural cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 3 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 8 is a process sectional view showing a manufacturing process for a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 10 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 11 is a process sectional view showing a manufacturing process for a semiconductor device according to an embodiment of the present invention.

FIG. 12 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 13 is a process sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 14 is a process sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 15 is a cross-sectional view showing the structure of a conventional semiconductor device.

FIG. 16 is a circuit diagram showing a circuit configuration of a conventional inverter circuit.

[Explanation of symbols]

1 Silicon substrate 2 P well 3 N wells 4 element isolation region 5 Ions for preventing parasitic channels 6 Gate oxide film 7 Polycrystalline silicon Source region of 8 N-channel transistor 9 P-channel transistor source region 10 Interlayer insulation film 11 contact holes 12 Aluminum wiring 18 Gate electrode area 27 N-channel transistor drain region 29 P-channel transistor drain region

Claims (6)

[Claims] 1. A semiconductor device including an inverter circuit formed by a pair of P-channel transistors and N-channel transistors, wherein each of the P-channel or N-channel transistors stacked in a direction perpendicular to a main surface of a semiconductor substrate. Source of
A channel and a drain, and an insulating film and a gate electrode laminated in a direction perpendicular to the main surface of the semiconductor substrate on a side surface of the channel that faces the P-channel transistor and the N-channel transistor that form the inverter circuit. A semiconductor device characterized by: 2. The source, channel, and drain of each of the N-channel or P-channel transistors have an element isolation region and a gate electrode formed on a substrate, and P-type and N-type silicon are alternately laminated in three layers. The semiconductor device according to claim 2, wherein 3. A method of manufacturing a semiconductor device having an inverter circuit formed by a pair of P-channel transistors and N-channel transistors on a silicon semiconductor substrate, wherein source regions of the N-channel and P-channel transistors are on the semiconductor substrate. Forming an N-type epitaxial silicon layer, forming a P well and an N well, and then forming an element isolation region and a gate electrode region, and forming the element isolation region and the gate electrode region on the semiconductor substrate. A process of etching in the direction perpendicular to the main surface and burying an insulating film there, and forming a source wall for forming the sources of the N-channel and P-channel transistors and diffusing it
Step of forming source of channel and P-channel transistor, etching insulating film in gate electrode region deeper than source, forming gate oxide film by thermal oxidation, forming gate electrode so as to be lower than silicon main surface A step of forming drains of N-channel and P-channel transistors in the P-well and N-well, and stacking an interlayer insulating film on the gate oxide film to form the source, drain and gate of the N-channel and P-channel transistors. A method of manufacturing a semiconductor device, comprising the steps of etching only an interlayer insulating film in each region to form a contact hole and connecting each region with an aluminum wiring. 4. The source, channel, and drain of each of the N-channel or P-channel transistors are N-type,
The method of manufacturing a semiconductor device according to claim 3, wherein the P-type ion species are formed by implanting and diffusing. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the implantation of each of the ion species is performed with different acceleration voltages for the source, the channel, and the drain. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the gate oxide film is formed by implanting oxygen ions into a portion where the gate oxide film is to be formed and annealing it.